JPH03250667A - Mos field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent occurrence of punch-through as well as to realize a well without a residual stress by providing a first well and a second well of second conductivity type formed to enclose one source/drain region and the other source/drain region of first conductivity type, which are formed separately on both sides of a gate on the main surface of a semiconductor substrate. CONSTITUTION:A first well 17 and a second well 18 being an N-type impurity region are formed on the main surface of a semiconductor substrate 1 on both sides of a gate 2. The wells 17, 18 have parts 17a, 18a vertically overlapping the gate 2. A source region 3 being a P-type impurity diffusion layer is formed inside the well 17, while a drain region 4 being a P-type impurity diffusion region is formed inside the well 18. Thus a depletion layer in the vicinity of the drain 4 does not spread to the source region 3 so that punch-through can be effectively prevented. Since the wells 17, 18 are small wells which enclose only the source/drain regions 3, 4, thermal treatment at a high temperature is not necessary resulting in no distortion due to thermal stress.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention generally relates to a MOS field effect transistor, and more specifically relates to a MOS field effect transistor that is improved so as not to cause distortion in a semiconductor substrate. . The invention further relates to a method of manufacturing such a MOS field effect transistor.

[Prior Art] A MOS field effect transistor (hereinafter abbreviated as MOSFET) controls the flow of majority carriers by applying a voltage to its gate, just as the amount of water is adjusted by opening and closing a tap. It is a device that

FIG. 11 is a sectional view showing the basic structure of a conventional MOSFET. Referring to FIG. 11, a gate 2 is provided on a semiconductor substrate 1. As shown in FIG. A source 3 and a drain 4 are formed on the main surface of semiconductor substrate 1 and on both sides of gate 2 . When a voltage is applied to the gate 2, the channel region 5 directly under the gate 2 is inverted, and the source 3 and drain 4 are
Or conductive. By the way, M having the above structure
In an OSFET, when the channel length is short, it spreads to the depletion layer 6 near the drain 4 or the source region 3, as shown in the figure.
A phenomenon occurs in which the current cannot be controlled due to the voltage of the gate 2. This phenomenon is called MOSFET bunch-through. Note that in FIG. 11, the portion indicated by reference numeral 7 is the end of the depletion layer.

In order to prevent this punch-through, a semiconductor device in which a MOSFET is formed in a well has been proposed. 12th
FIG. A is a cross-sectional view of a conventional semiconductor device in which a buried channel MOSFET is formed in a well formed in a semiconductor substrate. FIG. 13 is a plan view of the semiconductor device shown in FIG. 12A. Referring to these figures, an N-type impurity diffusion layer 8 called a well is formed on the main surface of a P- type semiconductor substrate 1. The definitions of P type and N type will be described later. On the surface of the impurity diffusion layer 8,
An impurity layer 9 is provided for controlling the threshold voltage. A gate 2 into which N-type impurity ions are implanted is provided on the semiconductor substrate 1 . In the impurity diffusion layer 8 and on both sides of the gate 2, a source 3 and a drain 4, which are formed by diffusing P-type impurities, are provided.

Field oxide film 1 provided on the main surface of semiconductor substrate 1
0 is for separating the element region 11 from other element regions. Conventional MOSFE configured like this
In T, the source 3 and drain 4 are formed in a well (N-type impurity diffusion layer 8) having opposite conductivity types, so even if the channel length is shortened, the depletion layer near the drain 4 remains It no longer spreads to the source region, and punch-through is effectively prevented.

Note that FIG. 12A shows a buried channel type MOSFET, which will be briefly explained.

FIG. 12B shows the distribution of the number of ions present on the main surface of the semiconductor substrate plotted against the distance in the length direction of the channel. The vertical axis represents the number of ions defined next, and the horizontal axis represents the distance in the length direction of the channel.

N=nN-np P=n, -nN In the above formula, nN represents the number of N-type atoms, and nP represents the number of P-type atoms. If nN - nP>0 in a certain region, then N>0, and that region is an N-type impurity region from a metallurgical point of view.

Also, if nP-nN>Q in a certain region, then p>.

This region is a P-type impurity region from a metallurgical standpoint.

With reference to FIGS. 12A and 12B, metallurgically,
The portion directly below the gate 2, ie, the channel region, is of P- type. Even if no voltage is applied to the gate 2, the source 3 and drain 4 already appear to be conducting. However, an N-type impurity is implanted into the gate 2, and under the influence of this electric field, the potential of the channel region becomes N-type, as shown in FIG. 12C. That is, by placing the N-type gate 2 on the semiconductor substrate 1, the source region 3 and the drain region 4 are electrically isolated.

By applying a positive voltage to the gate 2, the potential of the channel region becomes P type, and the source region 3 and drain region 4 become conductive.

Next, a method for manufacturing the conventional MOS FET shown in FIG. 12A will be explained with reference to FIGS. 14A to 14E.

Referring to FIG. 14A, a P-type semiconductor substrate 1 (boron,
N-type impurity ions 12 (phosphorus) were implanted over the entire surface of the 1X10" cm-3), and then heated at 1000°C or higher for 10
By time thermal diffusion, an N-type impurity diffusion layer 8 (phosphorus, lXl) called a well is formed on the main surface of the semiconductor substrate 1.
0” cm3).

Next, referring to FIG. 14B, P-type impurity ions 13 (boron) are implanted into the entire surface of the impurity diffusion layer 8, thereby controlling the threshold voltage on the surface of the impurity diffusion layer 8. Impurity layer 9 (holon, lXl0' 7c
m-3) is formed.

Next, referring to FIG. 14C, gate oxide film 14 is formed on the surface of semiconductor substrate 1 by subjecting semiconductor substrate 1 to thermal oxidation treatment. Thereafter, an electrode material containing N-type impurity ions is deposited on the gate oxide film 14 (not shown) and patterned into a predetermined shape, thereby forming the N-type gate 2.

Next, referring to FIG. 14D, an oxide film is deposited on the entire surface of the semiconductor substrate 1 including the gate 2 (not shown) and anisotropically etched to form a sidewall spacer on the side wall of the gate 2. form 15.

Next, referring to FIG. 14E, using the gate 2 and sidewall spacer 15 as a mask, P-type impurity ions 16 (boron) are implanted into the surface of the semiconductor substrate 1, thereby forming the surface of the impurity diffusion layer 8. A source region 3 (boron, lXl0" cm-3) and a drain region 4 (boron, lx1020 cm, -") are formed.

Next, although not shown, an interlayer insulating film is formed over the entire surface of the semiconductor substrate 1 including the gate 2, a contact hole is formed in this interlayer insulating film, and then an aluminum wiring is formed to obtain a MOSFET.

[Problems to be Solved by the Invention] Since the conventional MOSFET was configured as described above, referring to FIGS. 12A and 14A, in order to form the N-type impurity diffusion layer 8 that will become the well, ,1000℃
It was necessary to perform the above-mentioned high-temperature heat treatment. This high-temperature heat treatment generates stress due to thermal stress in the semiconductor substrate 1, and this thermal stress remains as residual stress in the semiconductor substrate 1 even after the temperature returns to room temperature. Due to this residual stress,
The semiconductor substrate 1 becomes distorted. The tendency for the semiconductor substrate 1 to be distorted due to residual stress becomes more pronounced as the diameter of the semiconductor substrate 1 becomes larger. Deformation of the semiconductor substrate causes process non-uniformity and instability between the center and the periphery of the semiconductor substrate. As a result, there is a problem in that a difference occurs in device characteristics between the central portion and the peripheral portion of the semiconductor substrate, which in turn causes a decrease in device yield.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a MOS field effect transistor having a well that is improved to prevent punch-through and has no residual stress.

Another object of the invention is to provide an improved MOS field effect transistor with increased speed.

Still another object of the present invention is to provide a method for manufacturing a MOS field effect transistor having a well, which is improved so that a high-temperature heat treatment step is not required.

Still another object of the present invention is to provide a method for manufacturing a MOS field effect transistor that is improved so that the delay time is reduced.

[Means for Solving the Problems] A MOS field effect transistor according to a first aspect of the invention has a structure in which one source/drain region is connected to another source/drain region.
This device controls the flow of majority carriers toward the drain region by applying a voltage to the gate. The field effect transistor includes a semiconductor substrate having a main surface and a transistor that controls the flow of majority carriers.

The transistor includes a gate provided on the semiconductor substrate Q, one source/drain region and the other source/drain region of a first conductivity type. Further, the field effect transistor includes a first well and a second well of a second conductivity type, which are formed on the main surface of the semiconductor substrate and are spaced apart from each other on both sides of the gate. There is.

The first well is formed to surround one of the source/drain regions. The second well is formed to surround the other source/drain region.

A MOS field effect transistor according to a second aspect of the invention includes a semiconductor substrate having a main surface. An N-type gate is formed on the semiconductor substrate. On the main surface of the semiconductor substrate, on both sides of the gate, 1
A pair of P-type source/drain regions is provided. A channel region is formed on the main surface of the semiconductor substrate directly below the gate. The channel region is divided into a central portion and a pair of end portions formed to sandwich the central portion from both sides. The conductivity type of the central portion is more inclined to P type than the conductivity type of the end portions.

A method of manufacturing a MOS field effect transistor according to a third aspect of the invention relates to a method of manufacturing a MOS field effect transistor having a gate, one source/drain region, and the other source/drain region. First, a semiconductor substrate having a main surface is prepared. Thereafter, the gate is formed on the main surface of the semiconductor substrate. Thereafter, using the gate as a mask, impurity ions of a second conductivity type are implanted into the main surface of the semiconductor substrate by a rotational ion implantation method, so that impurity ions are implanted into the main surface of the semiconductor substrate and on both sides of the gate. A first well and a second well of a second conductivity type are formed. The first well is a small well that surrounds only one of the source/drain regions.

Further, the second well is a small well that surrounds only the other source/drain region.

Thereafter, using the gate as a mask, impurity ions of a first conductivity type are implanted into the main surface of the semiconductor substrate, thereby forming the one source/drain region in the first well, and The other source/drain region is formed in the second well.

According to a preferred embodiment of the method for manufacturing an MO3 field effect transistor according to the third aspect of the present invention, the rotational ion implantation method includes the steps of generating a beam of impurity ions, and directing the semiconductor substrate to the beam. The method includes the steps of arranging the semiconductor substrate so as not to be perpendicular to each other, and rotating the semiconductor substrate.

A method for manufacturing an MO3 field effect transistor according to a fourth aspect of the invention includes an MO8 field effect transistor having a gate, one source/drain region, and the other source/drain region.
The present invention relates to a method for manufacturing an O8 field effect transistor. First, a J-th conductivity type semiconductor substrate having a main surface is prepared. Thereafter, impurity ions of a second conductivity type are implanted into the main surface of the semiconductor substrate with an energy that provides an impurity concentration distribution having a maximum concentration at a position away from the main surface, thereby creating a second conductivity type in the semiconductor substrate. Form an impurity layer of the mold. Next, the gate is formed on the main surface of the semiconductor substrate. Thereafter, using the gate as a mask, impurity ions of a second conductivity type are implanted into the main surface of the semiconductor substrate by a rotational ion implantation method, whereby the impurity ions of the second conductivity type are implanted from the main surface of the semiconductor substrate into the impurity layer of the second conductivity type. spread to,
A first well and a second well are formed. The first well is a small well that surrounds one of the source/drain regions. The second well is a small well that surrounds the other source/drain region.

Thereafter, using the gate as a mask, impurity ions of a first conductivity type are implanted into the main surface of the semiconductor substrate, thereby forming the one source/drain region in the first well, and The other source/drain region is formed in the second well.

According to a preferred embodiment of the method according to the fourth aspect of the present invention, prior to forming the second conductivity type impurity layer in the semiconductor substrate, first conductivity type impurity ions are added to the main surface of the semiconductor substrate. Injected.

[Function] According to the MO8 field effect transistor according to the first aspect of the present invention, the well formed to prevent punch-through is a small well that surrounds only the source/drain region. The high-temperature heat treatment that was necessary to form the . Hence,
The obtained M0S field effect transistor has no residual strain caused by thermal stress. As a result, the ~10S field effect transistor becomes a highly reliable device.

In the MO8 field effect transistor according to the second aspect of the present invention, the conductivity type of the central portion of the channel region is more inclined to P type than the conductivity type of the end portions, so that high speed is achieved in the central portion of the channel region. This increases the speed of the transistor as a whole.

According to the method for manufacturing a MOS field effect transistor according to the third aspect of the present invention, the well is formed to prevent punch-through or is small enough to surround only the source/drain region. The high-temperature heat treatment process that was required for the formation is no longer necessary.

Therefore, it is possible to suppress the occurrence of distortion in the semiconductor substrate. Consequently, no difference is caused in device characteristics between the central portion and the peripheral portion of the semiconductor substrate. the result,
Device yield is improved.

According to the method for manufacturing an MO3 field effect transistor according to the fourth aspect of the present invention, energy is applied to the main surface of a semiconductor substrate of the first conductivity type to provide an impurity concentration distribution having a maximum concentration at a position away from the main surface. Impurity ions of a second conductivity type are implanted, thereby forming an impurity layer of a second conductivity type in the semiconductor substrate. Therefore, impurities of the first conductivity type, which serve as threshold setting impurities, remain on the main surface of the semiconductor substrate. Therefore, the process of implanting impurity ions for setting the threshold value is not necessary, and the process is simplified.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a sectional view of a buried channel type MO8 field effect transistor according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 1B is a diagram in which the distribution of the number of ions present on the main surface of the semiconductor substrate is plotted against the distance in the length direction of the channel. FIG. 1C is a diagram in which the potential distribution on the main surface of the semiconductor substrate is plotted against the distance in the length direction of the channel. The definition of the number of ions (N, P) is as described above. Referring to these figures, a gate 2 is provided on a P- type semiconductor substrate 1 with a gate oxide film 14 interposed therebetween. N-type impurity ions are introduced into the gate 2 . On the main surface of semiconductor substrate 1 and on both sides of gate 2, first well 17 and second well 18, which are N-type impurity regions, are formed. First well 17
has a portion 17a that vertically overlaps with the gate 2, and the second well 18 has a portion 18a that vertically overlaps with the gate 2.

The main surface of the semiconductor substrate 1 and the first well 17
A source region 3, which is a P-type impurity diffusion layer, is formed therein. The main surface of the semiconductor substrate 1 and the second
In the well 18, a drain region 4, which is a P-type impurity diffusion layer, is formed. Within the semiconductor substrate 1,
Further, an N-type impurity diffusion layer 19 is formed under the first well 17 and the second well 18. gate 2
, that is, the first well 17 and the second well 17.
P- type impurity ions are introduced into the region 20 located between the well 18 and the well 18 . Note that field oxide film 10 provided on the main surface of semiconductor substrate 1 is for separating element region 11 from other element regions.

Next, the operation will be explained.

Referring to FIGS. 1A and 1B, metallurgically, overlapping portions 17a and 18a are N-type impurity regions, and are regions located between first well 17 and second well 18. 20 is a P-type impurity region. However, N-type impurity ions are implanted into gate 2, and under the influence of the electric field of this gate, as shown in FIG. It is an area that is slightly biased towards the type.

That is, referring to FIGS. 1A and 1C, by placing N-type gate 2 on semiconductor substrate 1, source region 3 and drain region 4 are electrically isolated. When voltage is applied to gate 2, the channel region (17a,
20. The potential of 18a) is reversed to P type, and the source 3 and drain 4 are electrically connected.

In the MOSFET configured as described above, the source 3 and the drain 4 are formed in the first well 17 and the second well 18, respectively.
The nearby depletion layer does not extend to the source region 3, and punch-through is effectively prevented. The first well 17 and the second well 18 are formed to prevent punch-through, or the wells are small enough to surround only the source/drain region 3.4, so conventionally, a large well is formed. The high-temperature heat treatment required for this purpose is no longer necessary. Therefore, the obtained MOSFET
There is no residual strain caused by thermal stress. As a result, the MOSFET becomes a highly reliable device. Also,
Since P-type impurity ions are introduced into the central part (20) of the channel region, the central part (20) of the channel region
0), the high speed is partially improved, the overall threshold voltage vTM can be lowered, and the delay time of the transistor can be shortened. Furthermore, since the N-type impurity diffusion layer 19 exists in the semiconductor substrate 1, even if the source region 3 and the drain region 4 are electrically connected, there is a flow from the region 20 directly under the gate to the bottom of the P-type semiconductor substrate 1. The current will not escape.

Next, the method for manufacturing the MOSFET shown in FIG.
This will be explained with reference to Figures A to 3D.

Referring to FIG. 3A, a P~ type semiconductor substrate 1 (holon,
N-type impurity ions 12 (phosphorus) are implanted into the surface of the 3A-13A with an energy of 400 to 500 KeV. Then, heat treatment is performed at a temperature of 900° C. or less for 30 to 60 minutes. 4A, an N-type impurity layer 19 (phosphorus, lXl0" cm, -3) having an impurity concentration distribution with a maximum concentration at a position away from the main surface of semiconductor substrate 1 is formed on semiconductor substrate 1. formed within. In this case, the main surface of the semiconductor substrate 1 has the same impurity concentration as the semiconductor substrate 1 (boron, 1x1.0" cm-3
) is left behind.

Next, referring to FIG. 3B, a gate oxide film 14 is formed on the semiconductor substrate 1. Thereafter, N is deposited on the gate oxide film 14 by a CVD method using phosphine and silane gas.
Deposit a mold polysilicon layer. Subsequently, gate 2 is formed by patterning this N-type polysilicon layer into a predetermined shape. Next, using the gate 2 as a mask, N-type impurity ions 22 (phosphorus) are implanted into the main surface of the semiconductor substrate 1 by an oblique rotational ion implantation method. The implant energy is 120-18QKeV. by this,
A small first well 17 and a second well 18 of N type (phosphorus, 1×10 17 cm −3 ) are formed extending from the main surface of semiconductor substrate 1 into N type impurity layer 19 .

The oblique rotational ion implantation is performed by the method shown in FIG. That is, the semiconductor substrate 1 is arranged so as not to be perpendicular to the beam 23 of impurity ions. Then, while rotating the semiconductor substrate 1, the impurity ion beam 2 is
3 is irradiated toward the surface of the semiconductor substrate 1. Incline angle θ
is preferably in the range of 15 to 60 degrees.

Next, referring to FIG. 3C, an oxide film is deposited over the entire surface of the semiconductor substrate 1 including the gate 2. Thereafter, this oxide film is etched back by anisotropic etching to form sidewall spacers 24 on the side walls of gate 2.

Next, referring to FIG. 3D, P-type impurity ions 25 (boron) are implanted into the entire surface of the semiconductor substrate 1, thereby forming a P-type source region 3 (boron, boron) in the first well 17.
A P-type drain region 4 (boron, ], X102 is formed in the second well 18.
°cm-3).

Next, although not shown, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 1, a contact hole is formed in this interlayer insulating film, and then an aluminum wiring is formed.
A SFET is formed.

According to this method, the first well 17 and the second well 18 are small enough to accommodate the source region 3 and the drain region 4, respectively, which is conventionally necessary to form a large well. High-temperature heat treatment process becomes unnecessary. As a result, it is possible to suppress the occurrence of distortion in the semiconductor substrate 1, and as a result, no difference is caused in device characteristics between the central portion and the peripheral portion of the semiconductor substrate 1. As a result, the yield of devices is improved. Further, according to this method, since no distortion occurs in the semiconductor, it is possible to increase the diameter of the wafer.

FIGS. 6A to 6D show other manufacturing steps of the MOSFET shown in FIG. 1A, and are shown in cross-sectional views.

Referring to FIG. 6A, a P-type semiconductor substrate 1 (boron,
N-type impurity ions 12 (phosphorous) are implanted onto the surface of the 1X10" cm-3) at an energy of 400 to 500 KeV. Thereafter, at a temperature of 900° C. or lower for 30 to 60 minutes,
Perform heat treatment.

Then, referring to FIGS. 6A and 4A, an N-type impurity layer 19 (phosphorus, 1xlO"c) having an impurity concentration distribution having a maximum concentration at a position away from the main surface of semiconductor substrate 1 is formed.
m-") is formed in the semiconductor substrate 1. At this time, a P-type impurity having the same impurity concentration as the semiconductor substrate 1 (holon, 1×IQ150,7l-3) is formed on the main surface of the semiconductor substrate 1. Layer 21 remains.

Next, referring to FIG. 6B, gate oxide film 14 is formed on semiconductor substrate 1. After that, a CVD method using phosphine and silane gas is applied to the gate oxide film 14.
Deposit an N-type polysilicon layer. Subsequently, gate 2 is formed by patterning this N-type polysilicon layer into a predetermined shape. Next, an oxide film is deposited over the entire surface of the semiconductor substrate 1 including the gate 2. After that, by etching back this oxide film by anisotropic etching, a sidewall spacer 2 is formed on the sidewall of the gate 2.
form 4. Next, referring to FIG. 6C, N-type impurity ions 22 (phosphorous) are implanted into the main surface of semiconductor substrate 1 by oblique rotational ion implantation using gate 2 and sidewall spacer 24 as masks. The injection energy is
The implant energy must be greater than that used in the step shown in Figure 3B. As a result, N-type (phosphorus,
A small first well 17 and a second well 18 of lXl0' 7 cm-3) are formed.

After forming the sidewall spacers 24, impurity ions for forming wells are implanted, so that the first well 17 and the second well 18 can be formed deeply.

Next, referring to FIG. 6D, P-type impurity ions 25 (for example, boron) are implanted into the entire surface of the semiconductor substrate 1, thereby forming a P-type source region 3 in the first well 17.
(Boron, IXI020cm=3) and the second
P-type drain region 4 (boron, lX
1028 cm-3).

MOS
FET is obtained.

FIG. 7 shows an LDD (Lig) according to another embodiment of the present invention.
FIG. 2 is a cross-sectional view of a MOSFET having a (btly Doped Drain Sou+cc) structure.

The embodiment shown in FIG. 7 is the same as the embodiment shown in FIG. 1A except for the following points, so the same or corresponding parts are given the same reference numerals and the description thereof will not be repeated. .

The MOSFET shown in Fig. 7 is the MOSFE shown in Fig. 1A.
The difference from T is that in the small first well 17,
A P- impurity layer 26 is formed adjacent to the source region 3, and a P- impurity layer 27 is formed adjacent to the drain region 4 in the small second well 18. P- impurity layer 26.27 is 10"cm"
The P- concentration is on the order of 3. By making the structure of the MOSFET LDD type, there is an effect that resistance to hot electrons is increased.

Next, a method for manufacturing the Lr>D type MOS FET shown in FIG. 7 will be described with reference to FIGS. 8AF to 8E.

Referring to FIG.
N-type impurity ions 1 on the surface of
2 (phosphorus) is injected with an energy of 400 to 500 Ke. After that, at a temperature of 900°C or less, for 30 to 60 minutes,
Perform heat treatment. Then, referring to FIGS. 8A and 4A, an N-type impurity layer 19 (
phosphorus.

1xlO' 7cm-3) is formed in the semiconductor substrate 1. In this case, the semiconductor substrate 1 is provided on the main surface of the semiconductor substrate 1.
A P-type impurity layer 21 having the same impurity concentration (boron, lx1015 cm-") is left. Next, referring to FIG. 8B, a gate oxide film 14 is formed on the semiconductor substrate 1. Thereafter, CV using phosphine and silane gas
An N-type polysilicon layer is deposited on the gate oxide film 14 by method D. Subsequently, by patterning this N-type polysilicon layer into a predetermined shape, gate 2 is formed.
form. Next, using the gate 2 as a mask, impurity ions (boron) with a P- concentration are implanted into the surface of the semiconductor substrate 1. As a result, a P- impurity layer 26.27 (boron 1 × 10 I a c m
-3) is formed.

Next, referring to FIG. 8C, using gate 2 as a mask,
N-type impurity ions 22 (phosphorus) are implanted into the main surface of semiconductor substrate 1 by an oblique rotational ion implantation method. The implant energy is 120-180 KeV. As a result, a small first well 1 of N type (phosphorus, 1×10 17 cm −3 ) spreads from the main surface of the semiconductor substrate 1 into the N type impurity layer 19 .
7 and a second well 18 are formed.

Next, referring to FIG. 8D, an oxide film is deposited over the entire surface of the semiconductor substrate 1 including the gate 2. Thereafter, this oxide film is etched back by anisotropic etching to form sidewall spacers 24 on the side walls of gate 2.

Next, referring to FIG. 8E, P-type impurity ions 25 are implanted into the entire surface of semiconductor substrate 1 using gate 2 and sidewall spacers 24 as masks. As a result, a source region 3 (boron 1 x 102 °cm-3) adjacent to the P- impurity layer 26 is formed in the first well 17, and a source region 3 (boron 1 x 102 °cm-3) adjacent to the P- impurity layer 27 is formed in the second well 18. A toluin region 4 (holon 1×10 2 °cm −3 ) is formed.

Next, although not shown, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 1, a contact hole is formed in this interlayer insulating film, and an aluminum wiring is then formed.
The MOSFET shown in the figure is obtained.

In the above embodiment, referring to FIG. 1A, a case was exemplified in which an N-type impurity layer 19 was provided in a P-type semiconductor substrate 1 and N-type wells 17 and 18 were formed. The present invention is not limited to this, and an N-type semiconductor substrate may be used. In this case, it is not necessary to form the N-type impurity layer 19.

FIG. 9A is a cross-sectional view of a buried channel MO3FET according to still another embodiment of the present invention, and FIG. 9B is a diagram in which the distribution of the number of ions is plotted against the distance in the longitudinal direction of the channel. 9C is a diagram in which the potential distribution is plotted against the distance in the length direction of the channel.

In the embodiment shown in FIG. 1A, with reference to FIG. 1C, the potential of the channel region (particularly regions 17a and 18a) is largely inclined to N type, so that the threshold voltage vT
H was high and high speed could not be achieved. 9th AI
The MOSFETs shown in ffl to 9th CIM have been improved so that the threshold voltage vTH can be lowered.

The embodiment shown in FIG. 9A is similar to the embodiment shown in FIG. 1A except for the following points, and corresponding parts are given the same reference numerals and their explanations will be omitted.

Referring to FIGS. 9A and 9B, the central portion (20) of the channel region is of P type, and a pair of end portions (17a, 17a,
18a) is of the P-type.

The definitions of N and P are as described above.

In addition, in the figure, the curve shown by a dashed-dotted line is drawn for comparison, and is the curve shown in FIG. 1B. With this configuration, the N-type potential in the channel region becomes smaller, as shown in FIG. ). As a result, the threshold voltage VTH
becomes lower, which in turn makes the channel region more likely to invert.

In turn, the speed will increase.

Next, the method for manufacturing the MOSFET shown in FIG. 9A will be described in the first step.
This will be explained with reference to FIGS. 0A to 10E.

Referring to FIG. 10A, semiconductor substrate 1 (holon lXl0
”cm-3)+7) P-type impurity ions (
Boron) is implanted into the P-type impurity layer 30 (boron, lXl
0” cm-3).

Although the concentration of boron is exemplified as IXI O'' cm-3, it is preferably in the range of 1 x 1018 to 1X10'' cm-3.

Next, referring to FIG. 10B, N-type impurity ions 12 (phosphorus) are applied to the main surface of semiconductor substrate 1 at a voltage of 400 to 500 KeV.
Inject with energy. Thereafter, heat treatment is performed at a temperature of 900° C. or lower for 30 to 60 minutes. Then, with reference to FIGS. 10B and 4B, N has an impurity concentration distribution that has a maximum concentration at a position away from the main surface of semiconductor substrate 1.
A type impurity layer 19 (phosphorous, 1xlO" cm-3) is formed in the semiconductor substrate l.

Next, referring to FIG. 10C, a gate oxide film 14 is formed on the semiconductor substrate 1. Thereafter, an N-type polysilicon layer is deposited on the gate oxide film 14 by a CVD method using phosphine and silane gas (not shown). Subsequently, gate 2 is formed by patterning this N-type polysilicon layer into a predetermined shape. Next, using the gate 2 as a mask, N-type impurity ions 22 (phosphorus) are implanted into the main surface of the semiconductor substrate 1 by an oblique rotational ion implantation method. The implant energy is 120-180 KeV.

This causes N-type (phosphorus) to spread from the main surface of semiconductor substrate 1 into N-type impurity layer 19 .

A small first well 17 and a second well 18 of lXl0'``cm-'') are formed. The oblique rotational ion implantation is performed by the method shown in FIG. Next, referring to FIG. 10D, the semiconductor substrate 1 including the gate 2
An oxide film is deposited over the entire surface (not shown). after that,
By etching back this oxide film by anisotropic etching, sidewall spacers 24 are formed on the side walls of gate 2. Next, referring to FIG. 10E, P-type impurity ions 25 (holons) are added to the entire surface of the semiconductor substrate 1.
is implanted, thereby forming a P-type source region 3 (Poron I x 102 °cm-3) in the first well 17 and a P-type drain region 4 (Poron I x 102 °cm-3) in the second well 18.
boron, l×102°cm3).

Next, although not shown, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 1, a contact hole is formed in this interlayer insulating film, and then an aluminum wiring is formed.
A SFET is formed.

[Effects of the Invention] As explained above, the MO according to the first aspect of the invention
According to SFETs, the wells formed to prevent punch-through are small wells that accommodate only the source/drain regions, so there is no need for the high heat treatment that was conventionally required to form large wells. Become. Therefore, no strain caused by thermal stress remains in the obtained MOsFET. As a result, the MO8FET becomes a highly reliable device.

According to the MOSFET according to the second aspect of the invention, the conductivity type of the central portion of the channel region is more inclined to P type than the conductivity type of the end portions, so that the high speed is partially reduced in the central portion of the channel region. The speed of the transistor as a whole increases.

According to the method for manufacturing a MOSFET according to the third aspect of the present invention, the well formed to prevent punch-through is a small well that accommodates only the source/drain region. The high-temperature heat treatment process that was necessary for this process is no longer necessary. Therefore, it is possible to suppress the occurrence of distortion in the semiconductor substrate, and as a result, there is no difference in device characteristics between the central portion and the peripheral portion of the semiconductor substrate. As a result, the yield of devices is improved.

According to the method for manufacturing a MOSFET according to the fourth aspect of the present invention, impurity ions of the second conductivity type are added to the main surface of the semiconductor substrate with energy that provides an impurity concentration distribution having a maximum concentration at a position away from the main surface. is implanted, thereby forming an impurity layer of a second conductivity type in the semiconductor substrate.

Therefore, some impurities of the first conductivity type remain on the main surface of the semiconductor substrate. Therefore, the process of implanting impurity ions for threshold setting is not necessary, and the process is simplified.

[Brief explanation of drawings]

FIG. 1A is a cross-sectional view of a MOS field effect transistor according to an embodiment of the present invention. FIG. 1B shows the distribution of ion numbers plotted against distance along the length of the channel. FIG. 1C is a diagram of the potential distribution plotted against the lengthwise distance of the channel. FIG. 2 is a plan view of the MO3 field effect transistor shown in FIG. 1A. 3A to 3D show the manufacturing process of the MO8 field effect transistor shown in FIG. 1A, and are represented in cross-sectional views. FIG. 4A is a diagram showing the impurity concentration distribution obtained when the ion implantation shown in FIG. 3A is performed. FIG. 4B is a diagram showing the impurity concentration distribution obtained when the ion implantation shown in FIG. 10B is performed. FIG. 5 is a schematic diagram showing a method of rotational ion implantation. FIGS. 6A to 6D are process diagrams showing another method of manufacturing the MO8 field effect transistor shown in FIG. 1A, and are shown in cross-sectional views. FIG. 7 shows an LDD type MO3 according to another embodiment of the present invention.
It is a sectional view of FET. Figures 8A to 8E show the LDD type MO3F shown in Figure 7.
1 is a diagram showing the manufacturing process of ET, and is represented in a cross-sectional view. FIG. 9A shows an N10 according to still another embodiment of the present invention.
It is a sectional view of 3FET. FIG. 9B is a diagram in which the distribution of ion numbers is plotted against the distance in the length direction of the channel. FIG. 9C is a diagram in which the potential distribution is plotted against the lengthwise distance of the channel. 10A to 10E show the manufacturing process of the MO8 field effect transistor shown in FIG. 9A, and are represented in cross-sectional views. FIG. 11 is a diagram for explaining the punch-through phenomenon of MOSFET. FIG. 12A is a cross-sectional view of a conventional MO8 field effect transistor. FIG. 12B is a diagram in which the distribution of ion numbers is plotted against the distance along the length of the channel. FIG. 12C is a diagram of the potential distribution plotted against the lengthwise distance of the channel. FIG. 13 is a plan view of the MO3 field effect transistor shown in FIG. 12A. 14A to 14E show the conventional M shown in FIG. 12A.
1 is a process diagram showing a method for manufacturing an O8 field effect transistor, and is represented by a cross-sectional view. In the figure, 1 is a semiconductor substrate, 2 is a gate, 3 is a source region, 4 is a drain region, 17 is a first well, and 18 is a second well. In each figure, the same reference numerals indicate the same or corresponding parts. Fraud A figure ground 2 yo 2 Figure 4A aim 4B figure surface force; complete (shu, rn) L7 figure m-Ko island 9A figure- Iken book + 2A figure size warabisuntoge procedural amendment (self-motivated) ) March 11, 1991 1. Display of the case 1990 Patent Application No. 56655 2. Name of the invention MO3 field effect transistor and its manufacturing method 3. Person making the amendment Relationship with the case

Claims (4)

[Claims] (1) From one source/drain region to the other source/drain region
A MOS field effect transistor that controls the flow of majority carriers toward a drain region by a voltage applied to a gate, comprising: a semiconductor substrate having a main surface; and a transistor that controls the flow of majority carriers, the transistor comprising: a gate provided on the semiconductor substrate; one source/drain region and the other source/drain region of a first conductivity type; A first well and a second well of a second conductivity type are formed on both sides and spaced apart from each other, and the first well is formed so as to surround the one source/drain region. . A MOS field effect transistor, wherein the second well is formed to surround the other source/drain region. (2) From one source/drain region to the other source/drain region
A MOS field effect transistor in which the flow of majority carriers toward a drain region is controlled by a voltage applied to a gate, the transistor comprising: a semiconductor substrate having a main surface; an N-type gate formed on the semiconductor substrate; and the semiconductor substrate. a pair of P-type source/drain regions provided on both sides of the gate on the main surface of the semiconductor substrate; a channel region formed directly under the gate on the main surface of the semiconductor substrate; The channel region is divided into a central portion and a pair of end portions formed to sandwich the central portion from both sides, and the conductivity type of the central portion is higher than the conductivity type of the end portions.
A MOS field effect transistor that leans more toward P-type. (3) A method for manufacturing a MOS field effect transistor having a gate, one source/drain region, and the other source/drain region, the step of forming the gate on the main surface of a semiconductor substrate; Using the gate as a mask, impurity ions of the second conductivity type are implanted into the main surface of the semiconductor substrate by a rotational ion implantation method, thereby forming impurity ions on the main surface of the semiconductor substrate and on both sides of the gate. forming a first well and a second well of two conductivity types; using the gate as a mask, implanting impurity ions of a first conductivity type into the main surface of the semiconductor substrate; a step of forming the one source/drain region in the well, and forming the other source/drain region in the second well. (4) A method for manufacturing a MOS field effect transistor having a gate, one source/drain region, and the other source/drain region, the step of preparing a first conductivity type semiconductor substrate having a main surface. and implanting impurity ions of a second conductivity type into the main surface of the semiconductor substrate with energy that provides an impurity concentration distribution with a maximum concentration away from the main surface, thereby implanting a second conductivity type into the semiconductor substrate. forming an impurity layer on the main surface of the semiconductor substrate; and using the gate as a mask, impurity of a second conductivity type is implanted into the main surface of the semiconductor substrate by a rotational ion implantation method. A first well and a second well are implanted with ions, thereby extending from the main surface of the semiconductor substrate into the second conductivity type impurity layer.
using the gate as a mask, implanting impurity ions of a first conductivity type into the main surface of the semiconductor substrate, thereby forming one source/drain region in the first well. and forming the other source/drain region in the second well.