JPH03250765A - Solid-state image sensing element - Google Patents

Solid-state image sensing element

Info

Publication number
JPH03250765A
JPH03250765A JP2047932A JP4793290A JPH03250765A JP H03250765 A JPH03250765 A JP H03250765A JP 2047932 A JP2047932 A JP 2047932A JP 4793290 A JP4793290 A JP 4793290A JP H03250765 A JPH03250765 A JP H03250765A
Authority
JP
Japan
Prior art keywords
region
epitaxial layer
conductivity type
resistivity
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2047932A
Other languages
Japanese (ja)
Inventor
Kazuaki Kojima
数明 小嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2047932A priority Critical patent/JPH03250765A/en
Publication of JPH03250765A publication Critical patent/JPH03250765A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To contrive to suppress generation of a fine white point at the time of high temperature by a method wherein a semiconductor substrate is constituted of a one conductivity type base region, a first epitaxial layer and a second epitaxial layer and a channel region is formed in this second epitaxial layer. CONSTITUTION:A semiconductor substrate 20 is constituted of a one conductivity type base region 21, a one conductivity type first epitaxial layer 22, which is laminated on this region 21 and has a resistivity of 1OMEGA-cm or lower, and a one conductivity type second epitaxial layer 23, which is laminated on this layer 22 and has a resistivity of a degree identical with that of the region 21. A channel region is formed in this layer 23. Here, a compound material is formed of B being contained in large quantities in the layer 22 and heavy metals, such as Fe, Cu and the like, which are mixed in the Si substrate 20, and the heavy metals are removed to outside of an active region. Thereby, a crystal defect in the active region is decreased and the generation of a fine white point is suppressed.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、CCD固体撮像素子に係り、特に暗電流低減
のための基板の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a CCD solid-state image sensing device, and particularly to the structure of a substrate for reducing dark current.

(ロ)従来の技術 CCD固体撮像素子を形成するSi(シリコン)基板に
は、P塑成いはN型が用いられ、基板のタイプに依り素
子構造も異なる。P型基板を用いる場合、基板の一面に
N型の拡散領域を設け、この拡散領域が情報電荷の蓄積
転送チャネルとして用いられる。この拡散領域は、LO
GO9等のチャネル分離領域に依り区画されており、こ
のチャネル分離領域内に拡散領域から漏れ出す過剰な情
報電荷を受けるオーバーフロードレインが形成される。
(b) Prior Art The Si (silicon) substrate forming the CCD solid-state image pickup device is of P type or N type, and the device structure differs depending on the type of substrate. When a P-type substrate is used, an N-type diffusion region is provided on one surface of the substrate, and this diffusion region is used as an information charge storage and transfer channel. This diffusion region is LO
It is divided by a channel isolation region such as GO9, and an overflow drain is formed in this channel isolation region to receive excess information charges leaking from the diffusion region.

一方、N型基板を用いる場合、基板の一面にP型の拡散
領域、所謂P−Well領域を形成した後に、このP−
Well領域内に蓄積転送チャネルとなるN型拡散領域
が形成される。このようにN型基板を用いる場合には、
拡散領域内の過剰な情報電荷をN型基板側にυ1出する
縦型オーバーフロードレイン構造となるために、拡散領
域を区画するチヘ・ネル分離領域内にオーバーフ「1−
Fレインを形成する必要がなく、微細化、即ち画素の高
密度化に有効であり、今後の発展が期待される。しかし
ながら、P型基板を用いたCCDに於いても、N型基板
を用いた場合に比して赤外線領域で感度が高く、赤外線
カメラや高感度カメラ等の特定の用途には広く利用され
ている。
On the other hand, when using an N-type substrate, after forming a P-type diffusion region, a so-called P-Well region, on one surface of the substrate, this P-well region is formed.
An N-type diffusion region that becomes a storage transfer channel is formed in the well region. When using an N-type substrate in this way,
In order to create a vertical overflow drain structure in which excess information charges in the diffusion region are discharged to the N-type substrate side by υ1, an overflow “1-
There is no need to form an F-rain, and it is effective for miniaturization, that is, for increasing pixel density, and future development is expected. However, even CCDs using P-type substrates have higher sensitivity in the infrared region than those using N-type substrates, and are widely used for specific applications such as infrared cameras and high-sensitivity cameras. .

第3図はP型基板を用いたCCDを示す図で、同図(a
)はフレームトランスファ型の撮像部の平面図、同図(
b)はそのX−Y断面図である。
Figure 3 shows a CCD using a P-type substrate.
) is a plan view of the frame transfer type imaging unit, and the same figure (
b) is its X-Y sectional view.

P型のSi基板(10)の−主面には、チャネル分離領
域(1)で区画されるN型の拡散領域(2)(断面図で
省略しである)が互いに平行に配列され、埋込みチャネ
ル構造を成している。またSi基板(10)上には、拡
散領域(2)と交差し、複数の転送電極(3)がSin
、膜〈4)を介して配列形成される。この転送電極(3
)は、一部が重なり合う2層構造を成しており、このう
ち上層側はチャネル分離領域(1)上でその幅が狭く形
成される。そして、転送電極(3)に、多相、例えば4
相の転送りロック≠、〜≠4が印加されてSi基板(1
0)内を情報電荷が転送される。
On the main surface of the P-type Si substrate (10), N-type diffusion regions (2) (not shown in the cross-sectional view) separated by the channel separation region (1) are arranged parallel to each other and are embedded. It has a channel structure. Further, on the Si substrate (10), a plurality of transfer electrodes (3) intersect with the diffusion region (2).
, are formed in an array through the membrane <4). This transfer electrode (3
) has a two-layer structure that partially overlaps, and the upper layer has a narrower width above the channel separation region (1). Then, the transfer electrode (3) is provided with a multiphase, for example, 4
Phase transfer lock≠, ~≠4 is applied and the Si substrate (1
Information charges are transferred within 0).

このようなCCDに於いては、Si基板(10)の表面
近傍に結晶欠陥が存在すると、Si基板(10)中を転
送される情報電荷が結晶欠陥にトラップされて転送効率
が低下するため、Si基板(10)表面にはエピタキシ
ャル層(12)が形成きれて結晶欠陥の低減が図られて
いる。即ち、Si基板(10)は、B(ボロン)等のP
型不純物を含むベース領域(11)とこのベース領域(
11)上に積層形成されたP型のエピタキシャル層(1
2)からなり、エピタキシャル層(12〉内に転送チャ
ネルが形成されるように構成きれている。このエピタキ
シャル層(12)は、ベース領域(11)と同程度の不
純物濃度を有しており、抵抗率は10〜20Ω−■程度
に設定される。
In such a CCD, if there are crystal defects near the surface of the Si substrate (10), the information charges transferred in the Si substrate (10) will be trapped in the crystal defects, reducing the transfer efficiency. An epitaxial layer (12) is completely formed on the surface of the Si substrate (10) to reduce crystal defects. That is, the Si substrate (10) is made of P such as B (boron).
The base region (11) containing type impurities and this base region (
11) P-type epitaxial layer (1
2), and is structured so that a transfer channel is formed in the epitaxial layer (12). This epitaxial layer (12) has an impurity concentration comparable to that of the base region (11), The resistivity is set to about 10 to 20 Ω-■.

また、製造工程でSi基板(10)表面に付着するNa
(ナトリウム)等のアルカリ金属に依る転送チルネルへ
の影響を低減するために、Si基板(10)にはIG(
イントリンシックゲッタリング)処理が旅される。この
IG処理は、Si基板(10)内部に存在する過飽和酸
素を利用してSi基板(10)内部に偏析領域を形成す
るもので、Si基板(10)を高温に加熱して表面近傍
の酸素を基板外に拡散させた後に内部の酸素を析出許せ
ている。このようなIG処理に依れば、Si基板(10
)の表面近傍が酸素の析出や結晶欠陥のない領域となり
、Si基板(10)内部に不純物を捕捉する領域が形成
される。
In addition, Na adhering to the surface of the Si substrate (10) during the manufacturing process
In order to reduce the influence of alkali metals such as (sodium) on the transfer channel, the Si substrate (10) is
Intrinsic gettering) processing is carried out. This IG process uses supersaturated oxygen present inside the Si substrate (10) to form a segregation region inside the Si substrate (10), and heats the Si substrate (10) to a high temperature to remove oxygen near the surface. After diffusing to the outside of the substrate, the internal oxygen is allowed to precipitate. According to such IG processing, Si substrate (10
) becomes a region free from oxygen precipitation and crystal defects, and a region for trapping impurities is formed inside the Si substrate (10).

(ハ)発明が解決しようとする課題 ところで、小型化が図られている最近のビデオカメラに
於いては、装置の筐体内に極めて多くの回路素子が高密
度に搭載されているために、内部温度の上昇が問題とな
っている。特にCCDは、周辺温度が高くなると暗電流
の増大やノイズの発生等を招くといった問題を有してい
る。このようなノイズのひとつとして、主に高温時に発
生する微小な白点があげられる。このような白点はcc
Dの駆動方法の工夫や、信号処理の段階での映像信号の
補正に依って除去することは困難であり、CCD自体の
対策が望まれる。
(c) Problems to be Solved by the Invention Incidentally, in recent video cameras, which are becoming smaller in size, an extremely large number of circuit elements are mounted in a high density inside the housing of the device. Rising temperatures have become a problem. In particular, CCDs have problems such as an increase in dark current and generation of noise when the ambient temperature increases. One type of such noise is minute white spots that occur mainly at high temperatures. Such white spots are cc
It is difficult to eliminate this by devising a driving method for D or by correcting the video signal at the signal processing stage, and countermeasures for the CCD itself are desired.

そこで本発明は、高温時に於ける微小白点の発生を抑圧
できるCCD固体撮像素子の提供を目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a CCD solid-state image sensor that can suppress the occurrence of minute white spots at high temperatures.

(ニ)課題を解決するための手段 本発明は上述の課題を解決するためになされたもので、
半導体基板の一主面にチャネル分離領域で区画されたチ
ャネル領域が形成され、このチャネル領域上に複数の転
送電極が配列形成されるCCD固体撮像素子に於いて、
第1の特徴とするところは、上記半導体基板が、−導電
型のベース領域と、このベース領域上に積Mきれ1Ω−
m以下の抵抗率を有する一導電型の第1のエピタキシャ
ル層と、この第1のエピタキシャル層上に積層され上記
ベース領域と同程度の抵抗率を有する一導電型の第1の
エピタキシャル層と、からなり、この第2のエピタキシ
ャル層内に上記チャネル領域が形成されることにある。
(d) Means for solving the problems The present invention has been made to solve the above problems,
In a CCD solid-state imaging device, a channel region defined by a channel separation region is formed on one principal surface of a semiconductor substrate, and a plurality of transfer electrodes are arranged and formed on this channel region.
The first feature is that the semiconductor substrate has a base region of -conductivity type and a resistivity of 1Ω-
a first epitaxial layer of one conductivity type having a resistivity of m or less; a first epitaxial layer of one conductivity type laminated on the first epitaxial layer and having a resistivity comparable to that of the base region; The channel region is formed within this second epitaxial layer.

また第2の特徴とするところは、上記半導体基板が、−
導電型のベース領域と、このベース領域の一面に一導電
型の不純物が注入されて1Ω−m以下の抵抗率を有する
拡散層と、この拡散層上に積層され上記ベース領域と同
程度の抵抗率を有するエピタキシャル層と、からなり、
このエピタキシャル層内に上記チャネル領域が形成され
ることにある。
A second feature is that the semiconductor substrate is -
A base region of a conductivity type, a diffusion layer having a resistivity of 1 Ω-m or less by implanting impurities of one conductivity type into one surface of the base region, and a diffusion layer laminated on this diffusion layer and having a resistance similar to that of the base region. an epitaxial layer having a
The channel region is formed within this epitaxial layer.

そして第3の特徴とするところは、上記半導体基板が、
1Ω−m以下の抵抗率を有する一導電型のベース領域と
、このベース領域上に積層されベース領域より高い抵抗
率を有する一導電型のエピタキシャル層と、からなり、
このエピタキシA・ル層内に上記チャネル領域が形成さ
れることにある。
The third feature is that the semiconductor substrate is
Consisting of a base region of one conductivity type having a resistivity of 1 Ω-m or less, and an epitaxial layer of one conductivity type laminated on the base region and having a resistivity higher than that of the base region,
The channel region is formed within this epitaxial layer.

く本)作  用 本発明に依れば、微小白点の原因となる結晶欠陥を発生
させる重金属等の不純物が、抵抗率の低減のために多量
に含まれる不純物と複合体を形成し、この複合体が半導
体基板内に偏析される。
According to the present invention, impurities such as heavy metals that generate crystal defects that cause minute white spots form a complex with impurities contained in large amounts to reduce resistivity. The composite is segregated within the semiconductor substrate.

従って、活性領域に含まれる鉄、銅等の重金属が除去き
れて結晶欠陥が減少し、微小白点の発生が抑圧される。
Therefore, heavy metals such as iron and copper contained in the active region are completely removed, crystal defects are reduced, and the generation of minute white spots is suppressed.

(へ)実施例 本発明の実施例を図面に従って説明する。(f) Example Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明固体撮像素子の要部断面図であり、第3
図と同一部分が示しである。この図に於いて、電極構造
は第3図と同一で、同一部分には同一符号を付してあり
、また、チャネルストップ領域及び埋込みチャネル構造
を成すN型の拡散領域についても第3図と同一構成とな
っている。
FIG. 1 is a cross-sectional view of main parts of the solid-state image sensing device of the present invention, and FIG.
The same parts as the figure are shown. In this figure, the electrode structure is the same as in Fig. 3, and the same parts are given the same reference numerals, and the channel stop region and the N-type diffusion region forming the buried channel structure are also the same as in Fig. 3. They have the same configuration.

本発明の特徴とするところは、Si基板(20)のP型
のベース領域(21)とエピタキシャル層(23)との
間にP+型のエピタキシャル層(22)を形成すること
にある。即ち、P型の不純物を含むベース領域(21)
上<7=このベース領域(21)よりP型の不純物、例
えばBを高濃度に含んだエピタキシャル層(22)を積
層した後に、転送チャネルの形成きれるエピタキシャル
層(23)が再度形成される。ベース領域(21)上の
エピタキシャルJ’1i(22)は、ベース領域<21
〉及び転送チヘ・ネルの形成されるエピタキシャル層(
23)より、P型の不純物の濃度が一桁程度高く形成さ
れ、抵抗率は1Ω−m以下に設定される。
A feature of the present invention is that a P+ type epitaxial layer (22) is formed between a P type base region (21) and an epitaxial layer (23) of a Si substrate (20). That is, the base region (21) containing P-type impurities
Upper<7=After laminating an epitaxial layer (22) containing a high concentration of P-type impurities such as B from this base region (21), an epitaxial layer (23) in which a transfer channel can be formed is formed again. The epitaxial J'1i (22) on the base region (21) is
〉 and epitaxial layer where transfer channels are formed (
23), the concentration of P-type impurities is about one order of magnitude higher, and the resistivity is set to 1 Ω-m or less.

ベース領域(2I)及びエピタキシャル層(23)の抵
抗率に一ついては、第3図と同一の10〜20Ω−σ程
度である。
The resistivity of the base region (2I) and the epitaxial layer (23) is about 10 to 20 Ω-σ, which is the same as in FIG.

この上うなSi基板(20)に於いては、エピタキシャ
ル層(22)内に多量に含まれているBがSi基板(2
0〉内に混入しているFe、 Cu等の重金属と複合体
を形成し、重金属が活性領域外にυ1除きれる。このた
め、活性領域の結晶欠陥が減少し、微)」\白点の発生
が抑圧される。従って、エピタキシャル層(21)内の
Bの濃度が高いほど、即ちエピタキシャル層(21)の
抵抗率は低いほど微小山点の発生を抑圧する効果は大き
くなる。
Furthermore, in the Si substrate (20), a large amount of B contained in the epitaxial layer (22) is absorbed by the Si substrate (20).
A complex is formed with heavy metals such as Fe and Cu mixed in the active region, and the heavy metals are removed outside the active region. Therefore, crystal defects in the active region are reduced, and the occurrence of fine white spots is suppressed. Therefore, the higher the concentration of B in the epitaxial layer (21), that is, the lower the resistivity of the epitaxial layer (21), the greater the effect of suppressing the generation of minute peaks.

また、本実施例に於いては、ベース領域(21)上にP
1型のエピタキシトル層り22)を積層する場合を例示
したが、ベース領域(21)にB等のP型不純物を注入
拡散することで、ベース領域(21)の表面近傍に高濃
度のP+型拡散層を形成した後に、転送チャネルの形成
されるエピタキシャル層(23〉を積層しても良い、こ
の場合、P+型拡散層がP+型のエピタキシャル層(2
2)と同様に作用する。
In addition, in this embodiment, P is placed on the base region (21).
Although the case where a type 1 epitaxial layer 22) is laminated is illustrated, by implanting and diffusing P type impurities such as B into the base region (21), a high concentration of P+ is created near the surface of the base region (21). After forming the type diffusion layer, the epitaxial layer (23) in which the transfer channel is formed may be laminated. In this case, the P+ type diffusion layer is layered with the P+ type epitaxial layer (23).
It works in the same way as 2).

第2図は、本発明の他の実施例を示す断面図である。こ
の図に於いても、第3図と同一部分を示しである。
FIG. 2 is a sectional view showing another embodiment of the invention. This figure also shows the same parts as FIG. 3.

ここでSi基板(30)は、高濃度にP型不純物を含む
ベース領域(31)及びベース領域(31)よりP型の
不純物濃度が低いエピタキシャル層(32)からなり、
このエピタキシャル層(32)上に転送電極(3)が配
列形成される。即ち、1Ω−印以下の抵抗率を有するベ
ース領域(31)上に10〜20Ω−σ程度の抵抗率を
有するエピタキシャル領域(32)を積層してSi基板
(30)が形成きれている。従って、ベース領域(31
)自体が第1図のP+型のエピタキシャル領域(22)
と同様に作用し、重金属が除去される。従って、このよ
うなSi基板<31)に於いても、活性領域となるエピ
タキシャル層(32)内(7) 重金属が排除されて結
晶欠陥が減少し、微小山点の発生が抑圧される。
Here, the Si substrate (30) consists of a base region (31) containing a high concentration of P-type impurities and an epitaxial layer (32) having a lower concentration of P-type impurities than the base region (31),
Transfer electrodes (3) are arranged and formed on this epitaxial layer (32). That is, the Si substrate (30) is completely formed by laminating an epitaxial region (32) having a resistivity of about 10 to 20 Ω-σ on a base region (31) having a resistivity of 1 Ω-mark or less. Therefore, the base area (31
) itself is the P+ type epitaxial region (22) in Figure 1.
It acts in the same way as heavy metals are removed. Therefore, even in such a Si substrate (<31), heavy metals in the epitaxial layer (32) (7) serving as the active region are eliminated, crystal defects are reduced, and the generation of minute peaks is suppressed.

尚、本実施例に於いては、フレームトランスファ型のC
CD固体撮像素子について示しであるが、CCDの方式
に拘わらず、インターライン型等に於いても上述の如き
Si基板(20) 、 (30)を採用すれば、微細白
点の発生の抑圧が図れる。
In this embodiment, frame transfer type C
Although the illustration is about a CD solid-state image sensor, regardless of the CCD method, even in an interline type etc., if the above-mentioned Si substrate (20), (30) is adopted, the generation of fine white spots can be suppressed. I can figure it out.

(ト)発明の効果 本発明に依れば、活性領域の結晶欠陥が低減されるため
に微小白点の発生が抑圧される。従って、周辺温度が高
くなっても安定して良好な映像信号を得ることができ、
ビデオカメラの小型化に依る回路素子の高密度実装に有
効なCCD固体撮像素子を提供できる。
(G) Effects of the Invention According to the present invention, the crystal defects in the active region are reduced, so the generation of minute white spots is suppressed. Therefore, it is possible to obtain a stable and good video signal even when the ambient temperature becomes high.
It is possible to provide a CCD solid-state image sensor that is effective for high-density mounting of circuit elements due to miniaturization of video cameras.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明固体撮像素子の一実施例を示す断面図、
第2図は他の実施例を示す断面図、第3図は従来の固体
撮像素子を示す平面図及び断面図である。 図 図 1 ・そイ才1し→島伎卆拳幻へ。 2・搭賽Q@竺 20: Si :l各づ口i zj:へ°1−ス斗1りV Ho: ’:i$嗜 へ”−ス卆I煩” 2   工r”7身ち−レノ− 3o 二 S4二ff 31、  べ・−又命シ坊′ 32; 1ピ7ヤーfル眉 第 図(a)
FIG. 1 is a sectional view showing an embodiment of the solid-state image sensor of the present invention;
FIG. 2 is a sectional view showing another embodiment, and FIG. 3 is a plan view and a sectional view showing a conventional solid-state image sensor. Diagram 1 ・Soisai1shi → Shimaki Boukengen. 2. Boarding Q @ 竺20: Si :lEach Zuguchii zzj:He°1-Suto1riV Ho: ':i$昭へ"-Su卆I菆" 2 工r"7体ち- Reno 3 o 2 S4 2 ff 31, be-mata life 32; 1 pin 7 yard eyebrow diagram (a)

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の一主面にチャネル分離領域で区画さ
れたチャネル領域が形成され、このチャネル領域上に複
数の転送電極が配列形成されるCCD固体撮像素子に於
いて、 上記半導体基板が、 一導電型のベース領域と、 このベース領域上に積層され1Ω−cm以下の抵抗率を
有する一導電型の第1のエピタキシャル層と、 この第1のエピタキシャル層上に積層され上記ベース領
域と同程度の抵抗率を有する一導電型の第2のエピタキ
シャル層と、 からなり、この第2のエピタキシャル層内に上記チャネ
ル領域が形成されることを特徴とする固体撮像素子。
(1) In a CCD solid-state imaging device in which a channel region defined by a channel separation region is formed on one principal surface of a semiconductor substrate, and a plurality of transfer electrodes are arranged and formed on this channel region, the semiconductor substrate has the following features: a base region of one conductivity type; a first epitaxial layer of one conductivity type laminated on the base region and having a resistivity of 1 Ω-cm or less; and a first epitaxial layer laminated on the first epitaxial layer and having the same resistivity as the base region. a second epitaxial layer of one conductivity type having a certain resistivity, and the channel region is formed in the second epitaxial layer.
(2)半導体基板の一主面にチャネル分離領域で区画さ
れたチャネル領域が形成され、このチャネル領域上に複
数の転送電極が配列形成されるCCD固体撮像素子に於
いて、 上記半導体基板が、 一導電型のベース領域と、 このベース領域の一面に一導電型の不純物が注入され1
Ω−cm以下の抵抗率を有する拡散層と、この拡散層上
に積層され上記ベース領域と同程度の抵抗率を有する一
導電型のエピタキシャル層と、 からなり、このエピタキシャル層内に上記チャネル領域
が形成されることを特徴とする固体撮像素子。
(2) In a CCD solid-state imaging device in which a channel region defined by a channel separation region is formed on one main surface of a semiconductor substrate, and a plurality of transfer electrodes are arranged and formed on this channel region, the semiconductor substrate has the following features: A base region of one conductivity type, and an impurity of one conductivity type implanted into one surface of this base region.
It consists of a diffusion layer having a resistivity of Ω-cm or less, and an epitaxial layer of one conductivity type laminated on the diffusion layer and having a resistivity comparable to that of the base region, and the channel region is formed in the epitaxial layer. A solid-state imaging device characterized in that: is formed.
(3)半導体基板の一主面にチャネル分離領域で区画さ
れたチャネル領域が形成され、このチャネル領域上に複
数の転送電極が配列形成されるCCD固体撮像素子に於
いて、 上記半導体基板が、 1Ω−cm以下の抵抗率を有する一導電型のベース領域
と、 このベース領域上に積層されベース領域より高い抵抗率
を有する一導電型のエピタキシャル層と、からなり、こ
のエピタキシャル層内に上記チャネル領域が形成される
ことを特徴とする固体撮像素子。
(3) In a CCD solid-state imaging device in which a channel region defined by a channel separation region is formed on one main surface of a semiconductor substrate, and a plurality of transfer electrodes are arranged and formed on this channel region, the semiconductor substrate has the following features: It consists of a base region of one conductivity type having a resistivity of 1 Ω-cm or less, and an epitaxial layer of one conductivity type laminated on this base region and having a resistivity higher than that of the base region, and the channel is formed in this epitaxial layer. A solid-state imaging device characterized in that a region is formed.
JP2047932A 1990-02-28 1990-02-28 Solid-state image sensing element Pending JPH03250765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2047932A JPH03250765A (en) 1990-02-28 1990-02-28 Solid-state image sensing element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2047932A JPH03250765A (en) 1990-02-28 1990-02-28 Solid-state image sensing element

Publications (1)

Publication Number Publication Date
JPH03250765A true JPH03250765A (en) 1991-11-08

Family

ID=12789146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2047932A Pending JPH03250765A (en) 1990-02-28 1990-02-28 Solid-state image sensing element

Country Status (1)

Country Link
JP (1) JPH03250765A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57134960A (en) * 1981-02-16 1982-08-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS6284560A (en) * 1985-07-01 1987-04-18 テキサス インスツルメンツ インコ−ポレイテツド CTD/CMOS process
JPS6466932A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Epitaxial silicon wafer
JPH01274468A (en) * 1988-04-27 1989-11-02 Nec Corp Manufacture of solid-state image sensing device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57134960A (en) * 1981-02-16 1982-08-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS6284560A (en) * 1985-07-01 1987-04-18 テキサス インスツルメンツ インコ−ポレイテツド CTD/CMOS process
JPS6466932A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Epitaxial silicon wafer
JPH01274468A (en) * 1988-04-27 1989-11-02 Nec Corp Manufacture of solid-state image sensing device

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