JPH0325077B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a signal tuning detection circuit used in a tuning section of a television receiver. Conventional configurations and their problems In a tuning device using an electronic tuner, when a certain tuning voltage is applied to the tuner, it is often necessary to detect whether or not it is tuned to a desired television signal. There are various types of signal tuning detection circuits.
FIG. 1 shows an example of a conventional example. Composite video signal 1
A synchronization signal separation circuit 2 separates a composite synchronization separation signal 3 from the synchronization signal separation circuit 2 . Further, through a vertical and horizontal separation amplifier circuit 4, a horizontal oscillation circuit 5 and a vertical oscillation circuit 6 obtain a horizontal oscillation pulse 7 and a vertical oscillation pulse 8, respectively. These are essentially pulses used for deflection. 9 is a tuning signal detection section. The composite synchronization separation signal 3 and the horizontal oscillation pulse 7,
Each is processed by an integrator circuit 10 and a differentiator circuit 11, further waveform shaped by waveform shaping circuits 12 and 13, and the AND of both outputs is taken by a gate 14. Further, the output is integrated by an integrator circuit 15, and the integral Tuning is determined based on the voltage value. Schmitt circuit 1 is designed so that the judgment result is not affected by ripples in the vertical period.
6 as a tuning detection output signal 17. In this case, it is detected that the horizontal synchronization signal 3 is disturbed when it is not synchronized with the television signal. In order to compare only the horizontal sync signal part,
The horizontal synchronization signal 3 is extracted by the horizontal synchronization pulse 7.
However, the horizontal synchronization signal 3 and the horizontal synchronization pulse 7 are delayed in phase by the presence of the separation circuit 4 and the horizontal oscillation circuit 5. Therefore, in order to correct this, an integrating circuit 10 and a differentiating circuit 11 are required.
There is an inconvenience that correction is required. In particular, when making an integrated circuit IC, phase correction circuits 10, 11,
The integral simultaneous constant circuit 18 is a part outside the IC,
The number of parts increases, and the number of pins of the IC also increases. Purpose of the Invention An object of the present invention is to provide a signal tuning detection circuit that eliminates the above-mentioned drawbacks, has a small number of parts, is easy to integrate into an IC, and has characteristics similar to the response speed of tuning determination as the conventional example. do. Composition of the Invention The present invention includes an input circuit that compares a vertical synchronization separation signal with a threshold value that switches in response to the output of a signal presence/absence detection, and a circuit that counts vertical oscillation pulses and resets the input circuit when there is a signal from the input circuit. It is set by the counting circuit and the signal from the above input circuit,
This signal tuning detection circuit for a television receiver includes a signal presence/absence detection output circuit that is reset when the count value of the counting circuit exceeds a certain value. DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 2, the same parts as in FIG. 1 have the same numbers as in FIG. The synchronous separation signal 3 is transmitted to the differential amplifier 19 via the integrating circuit 18. It is compared with a predetermined threshold voltage 24 determined by the states of resistors 20 to 22 and transistor 23, and its output 25 is sent via transistor 36 to the set input of S-R flip-flop 26 with a clear terminal and to the T flip-flop. It is supplied to clear terminals 27 and 28. These T flip-flops 27 and 28 are
It constitutes a base counting circuit, and the vertical oscillation pulse 8 is input to the input of the first stage 27, and its output 2
9 is connected to the input of the next stage flip-flop 28. The outputs 29 and 30 of the flip-flops 27 and 28 are ANDed by an AND gate 31, and the AND output 32 is output from the flip-flop 2.
It is input to the clear terminal of 6. In addition, the flip
The reset terminal of flop 26 is grounded.
Output 17 of flip-flop 26 is the tuning detection output. The inverted output 33 of the flip-flop 26 is also supplied to the base of the transistor 23, the collector of which is connected between the resistors 21 and 22. The following table shows the input/output relationship of flip-flops.

【table】

[Table] Next, the operation of each block of the input circuit section 37, output circuit section 38, and counting circuit section 39 will be explained. First, the input circuit section 37 will be described. The synchronization separation signal 3 is integrated by the integrating circuit 18, and the vertical synchronization signal is input to the base of the transistor 34.
The waveforms of each part will be explained with reference to FIG. Waveform a is an example of a vertical synchronization signal input to the base of transistor 34. The synchronization signal has negative polarity. The period is a vertical period V. In the figure, V _A indicated by a broken line is the transistor 35.
is the base potential of Waveform b is the output 25 corresponding to waveform a. That is, during a period when the base potential of the transistor 34 is lower than the base potential of the transistor 35, the transistor 34 is on, the transistor 35 is off, the transistor 36 is off, and the output 25 of the input circuit section 37 becomes "H". V _A in the waveform a, that is, the threshold voltage 24 is determined by the division ratio of the resistors 20 to 22. However, it is switched depending on whether the transistor 23 is on or off. Next, the output circuit section 38 will be explained. This is the S-R FF2 that operates in the input/output relationship mentioned above.
It is 6. Waveform c in Fig. 3 is S-R FF2 in the initial state.
This is the output 17 waveform of the S-R FF 26 when the output 17 of the FF 26 is "L" and the clear input 32 is "L" and the waveform b is input to the set input terminal S. That is, due to the first pulse to the set input terminal S being "H", the output 17 of the S-R FF 26 changes from "L" to "H", and then the set input 25 becomes "L". Even if the output 17 becomes "H", the output 17 remains "H". This output 17 changes to “L” because the clear input 3
This is only when 2 becomes "H". Next, the counting circuit section 39 will be explained with reference to FIG. However, in the initial state, the clear input 25 of each T/FF 27, 28 is "L",
Outputs 29 and 30 were set to "L". First stage F.F27
Assume that the input 8 is a vertical oscillation pulse as shown in waveform d. With an input of period V, at its falling edge,
The output of T.FF 27 changes. The output 29 of the T.FF 27 is a waveform e. Furthermore, the output 30 of the T-FF 28 using the waveform e as input changes as the waveform f.The output 32 obtained by taking the logical product at the AND gate 31 is the waveform g, with a period of 4V and a duty of 1/4. It becomes a pulse waveform. Here, the overall operation will be explained. The more the vertical synchronization signal (base input of the transistor 34) receives TV radio waves with a stronger electric field, the higher the threshold potential 24 becomes.
(V _A in waveform a in FIG. 3) is assumed to have a characteristic that the potential is lower than that of V A in waveform a in FIG. First, the operation when shifting from a non-receiving state to tuning will be explained with reference to FIG. waveform h
is the vertical oscillation pulse 8, waveform i is the output 25 of the input circuit section 37, waveform j is the output 29 of the T.FF 27, waveform k is the output 30 of the T.FF 28, and waveform l is "L".
The C input 32 and the waveform m correspond to the tuning detection output 17, respectively. Before time _t0 , no signal is received, and the output 25 of the input circuit section 37 remains at "L". During this period, as explained in FIG. 4, a pulse with a period of 4V and a duty of 1/4 is inputted to the clear input 32 of the SR/FF 26 of the output circuit section 38 by the counting circuit section 39. During the "H" portion of this pulse, the output 17 becomes "L" and is maintained at this level. This is the reason why waveform m remains "L" until time _t0 . Now, assume that the reception state is reached after time _t0 , and pulses begin to be output from the output 25 of the input circuit section 37. When the clear terminals C of the T-FFs 27 and 28 of the counting circuit section 39 become "H", the outputs 29 and 30 both become "L", and the clear terminal C of the SR-FF 26 becomes "L". At this time, S-R・FF26
Since the set input 25 is "H", the tuning detection output 17 changes from "L" to "H". This is the reason why the waveform m changes from "L" to "H" at time _t0 . After this, unless the clear terminal 32 goes to "H" as explained in FIG. 3, the output 17 goes to "H".
It will remain as it is. Clear terminal 32 becomes “H” at T・FF2
This is the case when outputs 29 and 30 of outputs 7 and 28 are both “H”, but as can be seen from FIG.
When the outputs 29 and 30 of 27 and 28 both become "L", the clear terminal 32 of the S-R FF 26 becomes "H" unless the vertical oscillation pulse 8 falls three times.
do not become. However, during reception, the TFFs 27 and 28 are output from the output 25 of the input circuit section 37 in the V period.
Therefore, depending on the phase relationship between the output 25 of the input circuit section 37 and the waveform of _the vertical oscillation pulse ₈ , the T.
Although the output 29 of S
The clear terminal 32 of the -R.FF 26 does not become "H", and the tuning detection output 17 remains "H" after all. This means that the waveform m becomes “H” from time t ₀ onwards.
This is the reason why. Next, the transition from the tuned state to the untuned state will be explained with reference to FIG. 6. In FIG. 6, the waveform names are the same as in FIG. 5. As shown in waveform i at time t ₃ , it has not been synchronized since t ₃ . At this time, the counting circuit section 39 starts counting from the falling edge of the waveform h at time _t4 . Then, at time _t5 , waveform l becomes “H” and S-
The output 17 of the R.FF 26 changes to "L". That is, at time _t5 , the non-synchronization detection output state is reached. Note that there is a 3V period from time t ₃ to t ₅ , which is
This is necessary in the sense that the judgment output 17 does not react sensitively if the synchronization signal is disturbed for a while during reception. This period can be varied depending on the configuration of the counting circuit section 39. In the conventional example, the integral time constant circuit 18 shown in FIG. 1 was adjusted. In order to stabilize the above operation, the threshold potential 24 of the input circuit section 37, ie, the base potential of the transistor 35, is switched by the inverted output 33 of the SR/FF 26. This will be explained with reference to FIG. When transitioning from an unsynchronized state to a synchronized state, the vertical synchronization signal is waveform A, and the threshold potential is waveform B.
It is. The threshold potential B is the low potential V _C until time t ₅ . In FIG. 2, the tuning detection output 17 is "L", its inverted output 33 is "H", and the transistor 23 is on,
This corresponds to the case where the base potential of the transistor 24 is determined approximately by the ratio of the resistors 20 and 21. Since the threshold potential is low, the output 25 of the input circuit section 37 at times t ₃ and t ₄
remains at "L". It crosses the threshold potential for the first time at time _t5 , and as explained in FIG. 5, the tuning detection output 17 immediately becomes "H". At this time, inverted output 3
3 is "L" and the transistor 23 is off. Therefore, the threshold voltage 24 becomes the ratio of the resistor 20 and the sum of the resistors 21 and 22, and becomes a potential V _B higher than the previous threshold value V _C. That is, once the synchronization state is entered, even if the vertical synchronization signal is slightly disturbed, the output 25 of the input circuit section 37
Pulses are stably output from , and the tuning state detection output 17 is stable. This has an effect equivalent to the output stage Schmitt circuit (16 in FIG. 1) in the conventional example. How much electric field strength should be used to determine tuning?
It is basically determined by the resistors 20 to 22, and the integration circuit 18
Fine adjustment can be made using the time constant. Furthermore, the counting circuit section 39 sets how long the synchronization output is to be maintained in response to disturbances in the synchronization signal being received. The response speed of transition from the non-tuned state to the tuned state is determined by the time constant of the integrating circuit 18. As this time constant is made smaller, the response speed becomes faster. Differences in pulse width, phase, and period between the vertical synchronization pulse and the vertical synchronization signal are not a problem in this circuit, so the correction circuits 10 and 1 as in the conventional example are not used.
1 is unnecessary. Also, the integration circuit 18 is located at the signal input section, compared to the conventional case where the integration circuit 18 is located in the middle of processing.
When converted to an IC, the number of IC pins will be reduced. That is, in the conventional example, four inputs are required: 3 and 7, the integrating circuit 18, and the output 17, whereas in this example, the inputs are the base of the transistor 34, the input for 8 vertical oscillation pulses, and 3 of the output 17. This means that the number of pins can be reduced by one. Effects of the Invention As described above, the signal tuning detection circuit of the present invention has a large degree of freedom in input signals, and eliminates the need for phase and pulse width correction circuits, which were conventionally necessary.
Furthermore, the output holding period for synchronization disturbance during reception and the response speed for transition from the out-of-sync state to the in-sync state can be set separately, making the settings easy. Additionally, I.C.
It has the advantage of having a configuration that is easy to implement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal tuning detection circuit in a conventional example, FIG. 2 is a circuit diagram of a signal tuning detection circuit in an embodiment of the present invention, and FIG. 3 is for explaining the operation of the input circuit section in FIG. 2. FIG. 4 is a waveform diagram for explaining the operation of the counting circuit section in FIG. FIG. 7 is an explanatory diagram of operating waveforms during transition from to an out-of-tuned state, and FIG. 7 is an explanatory diagram of operating waveforms when switching the threshold of the input circuit section. 3...Synchronization separation signal, 8...Vertical oscillation pulse,
17... Tuning detection output, 19... Differential amplifier, 2
3...Threshold voltage switching transistor, 26...Set-reset flip-flop with clear terminal, 27, 28...T-flip-flop with clear terminal
Flop, 31...AND gate, 37...Input circuit section, 38...Output circuit section, 39...Counting circuit section.

Claims (1)

[Claims] 1. An input circuit that receives a vertical synchronizing signal as an input, compares the vertical synchronizing signal with a reference voltage, and outputs a pulse signal according to the comparison result, and receives a vertical oscillation pulse as an input, and A counting circuit configured by connecting a plurality of flip-flops in series, which receives the output signal of the input circuit as an input to a clear terminal; an output circuit composed of a set-reset flip-flop whose reset terminal is grounded; A signal tuning detection circuit configured to switch a comparison reference voltage of the input circuit based on an output signal of the circuit.