JPH03250784A - Printed circuit board for using sram's in common - Google Patents
Printed circuit board for using sram's in commonInfo
- Publication number
- JPH03250784A JPH03250784A JP4787990A JP4787990A JPH03250784A JP H03250784 A JPH03250784 A JP H03250784A JP 4787990 A JP4787990 A JP 4787990A JP 4787990 A JP4787990 A JP 4787990A JP H03250784 A JPH03250784 A JP H03250784A
- Authority
- JP
- Japan
- Prior art keywords
- sram
- terminal hole
- terminal
- printed circuit
- capacity sram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は小容量SRAMの代りに大容量SRAMを装
着可能とするSRAM共用化のためのプリント基板に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a printed circuit board for SRAM sharing that allows a large capacity SRAM to be installed instead of a small capacity SRAM.
[従来の技術]
一般の電子機器、システムにおいて多数のSRAMを装
着したプリント基板が多用されている。[Prior Art] Printed circuit boards equipped with a large number of SRAMs are often used in general electronic devices and systems.
第4図〜第6図はそれぞれプリント基板上に装着される
16にビット(2048語×8ビット構成)、64にビ
ット(8192語×8ビット構成)および256にビッ
ト(327688i!iX8ビット構成)のSRAM
(スタテックランダムアクセスメモリ)を上側面から見
た端子(ビン)の配置図であり、各端子には端子番号を
書き込み、その機能を添書きした。第4〜第6図におい
て、fl)は1、6 KビットSRAM (以下、16
KsRAMと記す)、(2)は64にビットSRAM
(以下、64KSRAMと記す)13)は256にビッ
トSRAM (以下、256KSRAMと記す) 、
(41は端子であり、16KSRAM+11の場合は2
4本の端子を、64KSRAMf21および256KS
RA M (3)の場合は28本の端子を有する。Figures 4 to 6 show 16 bits (2048 words x 8 bits configuration), 64 bits (8192 words x 8 bits configuration), and 256 bits (327688i!iX8 bits configuration) mounted on the printed circuit board, respectively. SRAM of
This is a layout diagram of the terminals (bins) of (Static Random Access Memory) viewed from the top side, with the terminal number written on each terminal and its function added. In FIGS. 4 to 6, fl) is 1.6 Kbit SRAM (hereinafter referred to as 16
KsRAM), (2) is 64-bit SRAM
(hereinafter referred to as 64KSRAM) 13) is a 256-bit SRAM (hereinafter referred to as 256KSRAM),
(41 is a terminal, and in the case of 16KSRAM+11, 2
Connect the four terminals to 64KSRAMf21 and 256KS
RAM (3) has 28 terminals.
(5)は電源(バッテリバックアップ電源) 、 16
1はGND (接地)、(7)はコンデンサを示す。(5) is the power supply (battery backup power supply), 16
1 indicates GND (ground), and (7) indicates a capacitor.
次に、各端子(]O0に端子番号と共に併記された役割
(機能)を示す記号について説明する。AO〜A15は
アドレスバス端子、l101〜r108はデータ入出力
用のデータバス端子OEは読出し指令信号端子、WEは
書込み指令信号端子、CSはチップセレクト端子であり
、第5図におけるCS、、CS2はそれぞれ第1および
第2のチップセレクト端子、VCCは電源端子、V s
sは接地端子を示す。16KSRAM(1+と64KS
RAM(2)および256 K S RA M [31
とは端子数が異なり、 64 K S RA M [
2) と256KSRΔM(3)とは端子の数は28本
で同じであるが、端子の役割が1例^ば端子番号1,2
0.26番について異なっている。ただし端子および端
子間寸法は各S’ RA M共同−に標準化されており
1例えば256KSRAM(31装着用のプリント基板
の端子穴には64 K S RA M (2)および1
(3KSRAMf1.lの装着を可能とする。Next, the symbols indicating the role (function) written together with the terminal number for each terminal (]O0 will be explained. AO to A15 are address bus terminals, l101 to r108 are data bus terminals for data input/output, and OE is a read command. A signal terminal, WE is a write command signal terminal, CS is a chip select terminal, CS, CS2 in FIG. 5 are the first and second chip select terminals, respectively, VCC is a power supply terminal, Vs
s indicates a ground terminal. 16KSRAM (1+ and 64KS
RAM (2) and 256 K S RAM [31
The number of terminals is different from 64K SRAM [
2) and 256KSRΔM(3) have the same number of terminals, 28, but if the role of the terminal is one example, terminal numbers 1 and 2 are used.
0.26 is different. However, the terminals and the dimensions between the terminals are standardized for each S' RAM (2) and 1 (for example, 256 KS RAM (31) in the terminal hole of the printed circuit board for mounting 64 K S RAM (2) and 1).
(3KSRAMf1.l can be installed.
L発明が解決しようとする課題J
SRAMの端子数および各端子の役割が一般にそのメモ
リ容量にて異なるので、プリント基板への上記SRΔM
の装着工程において、必要とするメモリ8徂のものが入
手できない場合には、よりメモリ容量の大きな人吉fi
sRAMで代用したくとも従来のプリント基板では装着
することができず、メモリ各社や端子数の異なる各SR
AMに合わせて複数種類のプリント基板を準備しなけれ
ばならないなどの問題点があった。L Problem to be solved by the invention J Since the number of terminals of an SRAM and the role of each terminal generally differ depending on the memory capacity, the above SRΔM on the printed circuit board is
During the installation process, if the required memory capacity of 8 degrees is not available, use the Hitoyoshi FI with a larger memory capacity.
Even if you want to use sRAM as a substitute, it cannot be installed on a conventional printed circuit board, and it is difficult to install it on a conventional printed circuit board.
There were problems such as the need to prepare multiple types of printed circuit boards for AM.
この発明は、上記のような問題点を解消するためになさ
れたもので、小容量SRAMの代りに大容量SRAMを
装着可能とするSRAM共用化のためのプリント基板を
得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a printed circuit board for SRAM sharing that allows a large-capacity SRAM to be installed instead of a small-capacity SRAM.
[課題を解決するための手段]
第1の発明に係わるSRAM共用化のためのプリント基
板は、小吉1tsRAMの代りに端子数の異なる大容量
SRAMを装着可能に上記大官iiSRAMの端子数の
端子穴を形成し、上記小容量SRAMと上記大容量sR
AMとの接地端子穴を共用すると共にそれぞれの電源端
子穴間を接続し、上記小吉llSRAMのWE端子穴は
第1の抵抗器を介して上記大官jlisRAMのWE端
子穴と接続すると共に上記小吉fISRAMを装着時に
誤装着を防止すべく不要となる端子穴間近傍に上記第1
の抵抗器を装着し2かっ、上記小吉1isRAMのWE
端子穴は第2の抵抗器を介して上記電源端子穴とを接続
すべ(プリント配線を形成したものである。[Means for Solving the Problems] The printed circuit board for SRAM sharing according to the first invention is capable of mounting a large-capacity SRAM with a different number of terminals in place of the Kokichi 1tsRAM. A hole is formed between the small capacity SRAM and the large capacity sR.
It shares the ground terminal hole with the AM and connects the respective power supply terminal holes, and the WE terminal hole of the Kokichi llSRAM is connected to the WE terminal hole of the Daikan jlisRAM through the first resistor, and the WE terminal hole of the Kokichi In order to prevent incorrect installation when installing fISRAM, the above-mentioned first
I installed the resistor of 2, and the above Kokichi 1 is RAM WE
The terminal hole should be connected to the power supply terminal hole via the second resistor (printed wiring is formed).
また、第2の発明に係わるSRAM共用化のためのプリ
ント基板は、小吉IsRAMの代りに端子数の等しい大
容量S RAMを装着可能に上記小容量SRAMと上記
大容量 S RA Mとの接地端子穴および電源端子穴
を共用すると共に上記小容量SRAMのNC端子穴は上
記接地端子穴と接続し、上記小吉fiSRAMが2本の
O3端子を有する場合には上記大官gksRAMと共通
する第1のC5端子穴を上記SRAMの共通するC5端
子穴とし、上記小吉JiSRAMの第2のC5端子穴を
上記電#端子穴と接続すべくプリント配線を形成したも
のである。Further, the printed circuit board for SRAM sharing according to the second invention has a ground terminal between the small capacity SRAM and the large capacity SRAM, so that a large capacity SRAM having the same number of terminals can be installed instead of the Kokichi IsRAM. hole and power supply terminal hole, and the NC terminal hole of the small capacity SRAM is connected to the ground terminal hole, and if the Kokichi fiSRAM has two O3 terminals, the first The C5 terminal hole is the common C5 terminal hole of the SRAM, and a printed wiring is formed to connect the second C5 terminal hole of the Kokichi JiSRAM to the terminal hole.
[作 用]
第1の発明におけるプリント基板の端子穴は大容量SR
AMの端子数に合わせて形成され、プリント配線は小吉
ffi: S RA Mと上記大容量S RAMとの接
地端子穴を共用すると共にそれぞれの電源端子穴間を接
続し、上記小吉1isRAMのWE端子が第1の抵抗器
を介して上記大容量SRAMのWE端子と接続されると
共に上記小吉ffi S RA Mを装着時に誤装着を
防止すべく不要となる端子穴間近傍に上記第1の抵抗器
を装着し、かつ、上記墨客jlsRAMのWE端子は第
2の抵抗器を介して上記電源端子穴とを接続すべく形成
される。[Function] The terminal hole of the printed circuit board in the first invention has a large capacity SR.
The printed wiring is formed to match the number of AM terminals, and the printed wiring shares the ground terminal hole of the Kokichi ffi: S RAM and the above-mentioned large-capacity S RAM, connects the respective power terminal holes, and connects the WE terminal of the above-mentioned Kokichi 1isRAM. is connected to the WE terminal of the large-capacity SRAM through the first resistor, and the first resistor is located near the terminal hole which becomes unnecessary in order to prevent incorrect installation when the Kokichi ffi SRAM is installed. is installed, and the WE terminal of the writer jlsRAM is formed to be connected to the power supply terminal hole via a second resistor.
また、第2の発明におけるプリント基板のプリント配線
は、墨客jltsRAMと大吉jlSRAMとの接地端
子穴および電源端子穴を共用すると共に上記墨客tsR
AMのNC端子穴は上記接地端子穴と接続し、上記墨客
1tSRAMが2本のC8端子を有する場合には上記大
容量SRAMと共通する第1のCS端子の端子穴を上記
SRAMの共通するO5端子穴とし、上記墨客fiSR
AMの第2のC8端子穴を上記電源端子穴と接続すべく
形成される。Further, the printed wiring of the printed circuit board in the second invention shares the ground terminal hole and the power supply terminal hole of the Bokukyu jltsRAM and the Daikichi jlSRAM, and also shares the ground terminal hole and the power terminal hole of the Bokukyu tsR.
The NC terminal hole of the AM is connected to the grounding terminal hole, and when the above-mentioned customer 1tSRAM has two C8 terminals, the terminal hole of the first CS terminal common to the above-mentioned large capacity SRAM is connected to the common O5 of the above-mentioned SRAM. With the terminal hole, the above writer fiSR
A second C8 terminal hole of the AM is formed to connect with the power supply terminal hole.
[発明の実施例] この発明の一実施例を第1図〜第3図により説明する。[Embodiments of the invention] An embodiment of the present invention will be described with reference to FIGS. 1 to 3.
図中、従来例と同じ符号で示されたものは従来例のそれ
ど同一もしくは同等なものを示す。In the figure, the same reference numerals as in the conventional example indicate the same or equivalent elements in the conventional example.
第1図は16KSRAM[1,lの代りに256KS
RA M CS1を装着するS RAM共用化のための
プリント基板(11)の回路図、第2図は16KSRA
M mの実装状態を示す外観の一部を示す図である。Figure 1 shows 16KSRAM [256KS instead of 1,l]
The circuit diagram of the printed circuit board (11) for SRAM sharing on which RAM CS1 is installed, Figure 2 is 16KSRA.
FIG. 3 is a diagram showing a part of the external appearance showing the mounting state of M m.
第1図において(8)は後述のプリント基板(11)に
形成されたSRAM装着のための端子穴であり、各端子
穴に付した記号T1〜728は256KSRΔM(3)
装着時の端子番号を示し1例えばT 3 (11のごと
<()内に付された数字は16 K S RA M (
11装着時の端子番号を示す、(9)は16にと256
KSRAM(11,(31の書込指令信号を切替えるた
めの抵抗器、(lO)は256KSRAM装着時All
端子を“H”レベルに確定させるためのプルアップ抵抗
器である。In FIG. 1, (8) is a terminal hole for mounting an SRAM formed on a printed circuit board (11), which will be described later, and the symbols T1 to 728 attached to each terminal hole are 256KSRΔM (3).
Indicates the terminal number when installed. 1 For example, T 3 (11 < The number in parentheses is 16 K S RAM (
Indicates the terminal number when 11 is installed, (9) is 16 and 256
Resistor for switching the write command signal of KSRAM (11, (31), (lO) is All when 256KSRAM is installed.
This is a pull-up resistor to establish the terminal at "H" level.
次に1.6 Kと256 K S RA、M(11,(
3)の共用回路と実装方式について説明する。16Ks
RAM f1+はその1,12.13.24番ビンが2
56 K S RA M (3)の3.14.15.2
6番ビンに対応するように実装させる。この場合、ピン
アサインが一致しない256 K S RA M T3
)のAl1、、A1.2についてはG N D (61
へ接続することによりアドレスを確定させる。書込指令
信号端子であるWE端子については16KsRAM[1
1の装着時に抵抗器(9)を実装し、256KSRAM
(3)実装時には抵抗器(9)を実装しないことにより
書込指令信号の入力元を切替えることにする。Next, 1.6 K and 256 K S RA, M (11, (
3) The shared circuit and mounting method will be explained. 16Ks
RAM f1+ has bins 1, 12, 13, and 24 as 2
56 K S RAM (3) 3.14.15.2
Implement it to correspond to the 6th bin. In this case, the pin assignments do not match 256 K S RAM T3
) for Al1, , A1.2 of G N D (61
Confirm the address by connecting to. Regarding the WE terminal which is the write command signal terminal, 16KsRAM [1
When installing 1, a resistor (9) is mounted, and 256KSRAM
(3) At the time of mounting, the input source of the write command signal is switched by not mounting the resistor (9).
抵抗(10)は256KSRAM装着時、抵抗器(9)
が実装されないため端子Allが不安定となるのを避け
るために挿入したものである。また、抵抗器(9)の実
装位置を第2図に示すように256KSRAMの1.2
番ビンと27.28番ビンの間にすることにより、16
にと256KSRAMとの誤実装の防止、例えば16K
SRAM+ljの装着端子穴の間道防止、又は16Ks
RAM(1)の代りに256 K S RA M (3
)の誤装着の防止、および抵抗器(9)を実装する、し
ないによる書込指令信号の切替え間違いを防止する。例
えば、16KSRAM実装時に抵抗器(9)が無いと動
作せず、出荷時に確認可となる。また、抵抗器(9)が
あると256KSRAMは実装することができず組立時
に誤実装を防止することができる。Resistor (10) is resistor (9) when 256KSRAM is installed.
This was inserted to prevent terminal All from becoming unstable because it is not mounted. Also, the mounting position of the resistor (9) is set at 1.2 of the 256KSRAM as shown in Figure 2.
By placing it between the No. 27 and 28th bins, 16
Preventing incorrect mounting with 256KSRAM, e.g. 16K
Preventing gaps in SRAM+lj mounting terminal holes or 16Ks
256 K S RAM (3) instead of RAM (1)
) and erroneous switching of the write command signal due to whether or not the resistor (9) is mounted. For example, when a 16KSRAM is mounted, it will not operate without the resistor (9), which can be confirmed at the time of shipment. Furthermore, the presence of the resistor (9) makes it impossible to mount the 256KSRAM, making it possible to prevent incorrect mounting during assembly.
第3図は64 K S RA M (2)の代りに25
6KS RA M [3)を装着するSRAM共用化の
ためのプリント基板の回路図である。図において、 (
121は64 K S RA M +21を装着の場合
に第1および第2のチップセレクト信号のいずれかを選
択するようにデツプセレクト信号を制御するためのNA
NDゲート、(13)は入力信号を反転するインペラで
ある。Figure 3 shows 25 instead of 64 K S RAM (2).
FIG. 2 is a circuit diagram of a printed circuit board for SRAM sharing on which a 6KS RAM [3] is installed. In the figure, (
121 is an NA for controlling the depth select signal to select either the first or second chip select signal when the 64 K S RAM +21 is installed.
The ND gate (13) is an impeller that inverts the input signal.
次に、64にと256KSRAM共用回路について説明
する。64KSRAMf2)と256KSRA M +
31の相違点である1番ビンと26番ビン+j、第3図
に示すように、それぞれG N D (6)と電源(5
)に接続することによりアドレスを確定させる。64K
SRAMの選択をチップセレクト信号lと2の両方で行
っている場合、20番ビンにはチップセレクト信号lを
インバータ(13)により反転させチップセレクト信号
2とのNANDをとって入力させることによりS RA
Mが選択されるようにする。Next, the 64 and 256 KSRAM shared circuit will be explained. 64KSRAMf2) and 256KSRAMM+
As shown in Figure 3, the differences between the 1st bin and the 26th bin +j of 31 are GND (6) and power supply (5
) to confirm the address. 64K
When SRAM selection is performed using both chip select signals 1 and 2, the chip select signal 1 is inverted by an inverter (13), NANDed with chip select signal 2, and input to the 20th bin. R.A.
Let M be selected.
上記実施例において、アドレスを確定させるために、第
1図に示した1 6に/256KSRAM共用回路では
A14 (256KSRAMの1番ビン)、Al1 (
256KSRAMの2番ビン)をそれぞれGNDに接続
し、第3図に示した64に/256KSRAM共用回路
ではA14 (256KSRAMの1番ビン)をGND
に接続したが、上記A12、A14アドレス端子は2.
2 [V]以上の電位にプルアップしてアドレスを確定
することも可能である。In the above embodiment, in order to determine the address, in the 16/256KSRAM shared circuit shown in FIG.
Connect A14 (bin 1 of 256KSRAM) to GND in the 64/256KSRAM shared circuit shown in Figure 3.
However, the A12 and A14 address terminals are connected to 2.
It is also possible to determine the address by pulling up to a potential of 2 [V] or higher.
また、16に/256KSRAM共用回路では書込み指
令信号の入力光を変え、なおかつ、16KSRAMの誤
実装を防止するために抵抗(9)を使用しているが、こ
れを短絡片等の部品に変えることも可能である。さらに
、64に/256KSRAM共用回路では、SRAMの
選択をチップセレクト信号lまたは2のどちらか一方の
みで行っている場合には、26番ビンを電源に接続し、
制御を行っているチップセレクト信号を20番ビンに接
続することも可能である。In addition, in the 16/256KSRAM shared circuit, the input light of the write command signal is changed and a resistor (9) is used to prevent incorrect mounting of the 16KSRAM, but it is possible to replace this with a component such as a shorting piece. is also possible. Furthermore, in the 64/256KSRAM shared circuit, if SRAM selection is performed using only either chip select signal 1 or 2, the 26th bin is connected to the power supply,
It is also possible to connect the controlling chip select signal to the 20th bin.
[発明の効果]
以上のように、第1の発明によれば、プリン]・基板に
大官llSRAMの端子数の端子穴を形成し。[Effects of the Invention] As described above, according to the first invention, terminal holes as many as the number of terminals of a large SRAM are formed on a printed circuit board.
弔客JilSRAMと上記大容量sRAMとの接地端子
穴を共用すると共に上記弔客isRAMのWE端子穴は
第1の抵抗器を介して上記大官ftsRAMのWE端子
穴は接続すると共に上記弔客fllsRAMを装着時に
不要となる端子穴間の近傍に上記第1の抵抗器を装着す
べ(プリント配線を形成したので、また、第2の発明に
よれば、プリント基板における弔客ffisRAMと大
容量SRAMとの接地端子穴および電源端子穴を共用し
、上記小容量SRAMが2本のO3端子を有する場合に
は、上記小容量SRAMの第2のCS端子穴を上記電源
端子穴と接続すべくプリント配線を形成したので、メモ
リ容量や端子数の異なる各SRAMに合わせて複数種類
のプリント基板を準備する必要のないものが得られる効
果がある。The ground terminal hole of the JilSRAM and the above-mentioned large capacity sRAM is shared, and the WE terminal hole of the isRAM is connected to the WE terminal hole of the large-capacity ftsRAM through the first resistor, and the According to the second invention, the first resistor is installed in the vicinity of the terminal holes that are unnecessary when installing the resistor. If the small-capacity SRAM has two O3 terminals, a printed wiring is used to connect the second CS terminal hole of the small-capacity SRAM to the power terminal hole. Since this structure is formed, there is an effect that there is no need to prepare a plurality of types of printed circuit boards for each SRAM having a different memory capacity and number of terminals.
第1図はこの発明の一実施例による1 6KSRAMの
代りに256KSRAMを装着するSRAM共用化のた
めのプリント基板の回路図、第2図は第1図に示した回
路図の実体配線図、第3図は64KSRAMの代りに2
56KSRAMを装着するSRAM共用化のためのプリ
ント基板の回路図、第4図〜第6図は従来のプリント基
板におけるSRAMの回路図であり、それぞれ16に、
64に、256KSRAMの回路図である。
図において、[1)〜(3)はそれぞれ16K、64に
、256KSRAM、(4)は各SRAMの端子、(8
)はプリント基板(10)の端子穴、(91,(101
は抵抗器、(12)はNANDゲート素子、(13)は
インバータ素子を示す。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a circuit diagram of a printed circuit board for SRAM sharing in which a 256KSRAM is installed instead of a 16KSRAM according to an embodiment of the present invention, FIG. 2 is an actual wiring diagram of the circuit diagram shown in FIG. Figure 3 shows 2 instead of 64KSRAM.
Circuit diagrams of printed circuit boards for SRAM sharing on which 56KSRAMs are mounted, Figures 4 to 6 are circuit diagrams of SRAMs on conventional printed circuit boards.
64 is a circuit diagram of a 256KSRAM. In the figure, [1] to (3) are 16K, 64, and 256KSRAM, respectively, (4) is the terminal of each SRAM, and (8
) are the terminal holes of the printed circuit board (10), (91, (101)
is a resistor, (12) is a NAND gate element, and (13) is an inverter element. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (2)
RAMを装着可能に上記大容量SRAMの端子数の端子
穴を形成し、上記小容量SRAMと上記大容量SRAM
との接地端子穴を共用すると共にそれぞれの電源端子穴
間を接続し、上記小容量SRAMのWE端子穴は第1の
抵抗器を介して上記大容量SRAMのWE端子穴と接続
すると共に上記小容量SRAMを装着時に誤装着を防止
すべく不要となる端子穴間近傍に上記第1の抵抗器を装
着し、かつ、上記小容量SRAMのWE端子穴は第2の
抵抗器を介して上記電源端子穴とを接続すべくプリント
配線を形成したことを特徴とするSRAM共用化のため
のプリント基板。(1) Large capacity S with different number of terminals instead of small capacity SRAM
The terminal holes are formed to have the same number of terminals as the large-capacity SRAM, so that the RAM can be attached to the small-capacity SRAM and the large-capacity SRAM.
The WE terminal hole of the small capacity SRAM is connected to the WE terminal hole of the large capacity SRAM via the first resistor, and the WE terminal hole of the small capacity SRAM is connected to the WE terminal hole of the large capacity SRAM through the first resistor. In order to prevent incorrect installation when installing the capacity SRAM, the first resistor is installed near unnecessary terminal holes, and the WE terminal hole of the small capacity SRAM is connected to the power supply through the second resistor. A printed circuit board for common use with an SRAM, characterized in that printed wiring is formed to connect terminal holes.
RAMを装着可能に上記小容量SRAMと上記大容量S
RAMとの接地端子穴および電源端子穴を共用すると共
に、上記小容量SRAMのNC端子穴は上記接地端子穴
と接続し、上記小容量SRAMが2本のCS端子を有す
る場合には上記大容量SRAMと共通する第1のCS端
子穴を上記SRAMの共通するCS端子穴とし、上記小
容量SRAMの第2のCS端子穴を上記電源端子穴と接
続すべくプリント配線を形成したことを特徴とするSR
AM共用化のためのプリント基板。(2) Large capacity S with the same number of terminals instead of small capacity SRAM
RAM can be attached to the above small capacity SRAM and above large capacity S
In addition to sharing the ground terminal hole and power supply terminal hole with the RAM, the NC terminal hole of the small capacity SRAM is connected to the ground terminal hole, and if the small capacity SRAM has two CS terminals, the NC terminal hole of the small capacity SRAM is connected to the ground terminal hole of the small capacity SRAM. A first CS terminal hole common to the SRAM is a CS terminal hole common to the SRAM, and a printed wiring is formed to connect the second CS terminal hole of the small capacity SRAM to the power supply terminal hole. SR to do
Printed circuit board for AM sharing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2047879A JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2047879A JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03250784A true JPH03250784A (en) | 1991-11-08 |
| JP2536652B2 JP2536652B2 (en) | 1996-09-18 |
Family
ID=12787672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2047879A Expired - Lifetime JP2536652B2 (en) | 1990-02-28 | 1990-02-28 | Printed circuit board for SRAM |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536652B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04109568U (en) * | 1991-03-11 | 1992-09-22 | 株式会社ケンウツド | Structure to prevent incorrect insertion of printed circuit boards |
| JPWO2021153476A1 (en) * | 2020-01-31 | 2021-08-05 |
-
1990
- 1990-02-28 JP JP2047879A patent/JP2536652B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04109568U (en) * | 1991-03-11 | 1992-09-22 | 株式会社ケンウツド | Structure to prevent incorrect insertion of printed circuit boards |
| JPWO2021153476A1 (en) * | 2020-01-31 | 2021-08-05 | ||
| US12374967B2 (en) | 2020-01-31 | 2025-07-29 | Fanuc Corporation | Motor drive device and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2536652B2 (en) | 1996-09-18 |
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