JPH0325089B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The processing time of a frequency analysis program used in a digital signal processor constituting a digital filter and a program that outputs filter data while performing frequency analysis are made the same, and the processing time is - The feature of the present invention is to generate a sampling clock for the analog-to-digital converter that supplies digital data to the digital signal processor by combining the number of steps of both programs so as to match the sampling period of the digital converter. .

[Industrial application field]

The present invention relates to an analog-to-digital converter sampling clock generation method for a digital filter, and more specifically, the present invention relates to a digital filter analog-to-digital converter sampling clock generation method, and more specifically, to a digital filter in which the generation of the sampling clock by conventional hardware means is improved by generation of the sampling clock by software means. Concerning analog-to-digital converter sampling clock generation method.

Digital filters are used to process analog signals such as audio signals. This digital filter must also be able to be successfully accommodated within the equipment in which it is used. Of course, it is necessary that other components be installed in the device and that these components can also be accommodated in the same manner as the digital filter. Therefore, if the device has a certain size, the space these components can occupy is limited in order for these components to be accommodated within that size.

In such cases, each component must meet its requirements while maintaining its functionality. Such requirements are also placed on digital filters used in audio processing devices and the like, and it is desired to develop technical means that can meet these requirements.

[Conventional technology]

FIG. 3 shows an example of the configuration of a digital filter used in a conventional audio processing device. As is clear from this figure, a digital signal supplied to a digital signal processor (DSP) 1 is sampled by an analog-to-digital converter (ADC) 2 and output. The clock for this sampling is a high-speed clock of a clock generation circuit 3 for operating the digital signal processor 1, which is reduced by a counter 5 of a timing control section 4 to a low-speed clock required for the above-mentioned sampling. In addition, in Figure 3, 6 is a microphone, 7
is a preamplifier, 8 is a pre-emphasis circuit, 9 is a low-pass filter (LPF), 10 is a sampling/hold circuit (S/H), 11 is a buffer control section, 12 is a bus, 13 is a microprocessor unit (MPU), 14 1 is a timing control section, and 15 is a counter.

[Problem that the invention seeks to solve]

As described above, when the counter 5 tries to down-level a high-speed clock to a low-speed clock, the difference in speed is large, and therefore the amount of hardware (number of parts) required increases. Therefore, the mounting space for this type of digital filter increases, the failure rate increases, and there is a cost disadvantage.

The present invention was created in view of the above problems, and is an analog-to-digital digital filter that can solve the above problems by improving the conventional hardware clock generation means into a software clock generation means. The purpose is to provide a converter sampling clock generation method.

[Means for solving problems]

The main structure of the present invention is as follows.

That is, in a digital filter having a digital signal processor, partial data for generating filter data of each channel is generated by frequency analysis of a required number of channels for each analog-to-digital converter sampling period within the preceding period of the filter data sampling period. A first program that generates the partial data and Generate filter data for each channel using the partial data for filter data generation obtained by frequency analysis in the latter period, and output the filter data of the generated channel to an analog-to-digital converter corresponding to the channel. A second program to be executed in a sampling period, and a processing time of the two programs of the digital signal processor, which are activated alternately, are approximated for each sampling period of the analog-to-digital converter, and each time each program is executed. The present invention is constructed by providing a circuit for generating a sampling clock for the analog-to-digital converter.

[Effect]

As mentioned above, the processing times of the two programs for generating filter data of the digital signal processor are approximated. Therefore,
The signals for generating the sampling clock from these programs are output each time the execution of each program is started, that is, at a period according to the approximation described above, and are used for sampling the analog-to-digital converter. It becomes a suitable clock. In this way, digital data provided to any program that generates filter data can be output from the analog-to-digital converter at a sampling period commensurate with the filter band.

[Embodiment] FIG. 1 shows an embodiment of the present invention. This embodiment takes as an example a case in which digital filtering of an audio signal is performed, and the same components as those of the conventional digital filter shown in FIG. 3 are given the same reference numerals and their explanations will be omitted. The main configuration of this embodiment is a digital signal processor (hereinafter referred to as
There are two programs (see Figure 2) used to generate filter data in the DSP (abbreviated as DSP): program A that performs frequency analysis of the required number (M) of channels and generates filter data, and program A that generates filter data. Filter data output signal (DSP1,
given via status register 15
Program B is applied to the DSP 1 via the line 18 from the control unit 17 in response to the filter data read request signal applied from the MPU 13 via the bus 12 and line 16 in response to the status of the ADC sampling period T and the filter data ready signal. The processing time is made the same as that of program B which is started in response to a start signal and outputs filter data while performing frequency analysis of the same number of channels as the required number, and the time is set to be the sampling period of the analog-to-digital converter. In addition, each time the execution of both programs is started, a signal having the timing of the ADC sampling period T is output from DSP1 on line 19 at the same period. A control section 17 is provided as a means for changing the signal to a signal suitable for sampling, that is, a signal satisfying a required pulse width, etc.

With this configuration, the drawbacks of conventional hardware clock generation means can be significantly alleviated.

That is, in both program A and program B described above, a signal having the timing of the ADC sampling period T can be sent from the DSP 1 on the line 19 (see FIG. 2). This is because the signal is converted by the control unit 17 into a sampling clock given signal conditions suitable for sampling by the ADC 2 and is supplied to the ADC 2. In other words, the ADC sampling period T can be set by software.

In the above embodiment, digital filtering of audio signals was described, but the present invention is also effective for other analog input signals as long as the ADC sampling period can be set in accordance with the filter band of the analog input signal. It is.

Furthermore, in the above embodiment, a case was explained in which the processing times of two programs are made the same, but analog signals such as audio signals do not necessarily need to be made the same all the time, and there may be a slight difference in the ADC sampling period. is allowed. In short, it is sufficient to generate a clock that can set the ADC sampling period.

〔Effect of the invention〕

As described above, according to the present invention, the sampling clock of the analog-to-digital converter of the digital filter can be set by software, so that the problems caused by conventional hardware settings can be greatly alleviated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a flowchart for explaining the embodiment of FIG. 1, and FIG. 3 is a diagram showing the configuration of a conventional digital filter. In Figure 1, 1 is DSP, 2 is ADC, 17
is the control section.

Claims (1)

[Claims] 1. In a digital filter having a digital signal processor, filter data generation for each channel is performed by frequency analysis of a required number of channels for each analog-to-digital converter sampling period within the preceding period of the filter data sampling period. a first program for generating partial data for the filter data sampling period; and performing frequency analysis of the same number of channels as the required number for each analog-to-digital converter sampling period in the period after the period after the period of the filter data sampling period; The partial data and the partial data for filter data generation obtained by frequency analysis in the latter period are used to generate filter data for each channel, and the output of the filter data of the generated channel is converted into an analog corresponding to the channel. - a second program executed in the digital converter sampling period; and - approximating the processing times of the two programs of the digital signal processor which are activated alternately for each of the analog-to-digital converter sampling periods; An analog-to-digital converter sampling clock generation method for a digital filter, characterized in that a circuit for generating a sampling clock for the analog-to-digital converter is provided each time a program is executed.