JPH03250924A - A/d converter - Google Patents

Abstract

PURPOSE:To revise the timing of sampling in a short time into a prescribed timing by supplying a 1st clock to a sampling circuit and supplying a 2nd clock having a period being the multiple of (m) of the period of the 1st clock to a digital filter. CONSTITUTION:When the timing sampling clocks SCK0, SCK1 is changed and the preset data PD of a register 10 is set smaller by the K period of the sampling clock SCK1, the period of the sampling clock SCK0 is shortened by a period Kt. Since the sampling clock SCK0 is obtained by frequency-dividing the sampling clock SCK1 through 1/m frequency division by a frequency divider 12, m-set of the sampling clocks SCK1 are present thereon without fail for one period of the sampling clock SCK0 and the digital filter operation averaging the digital data outputted according to the sampling clock SCK1 based on the sampling clock SCK0 is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an oversampling type A/D converter, and particularly relates to the creation of a sampling clock.

(b) Conventional technology In communication equipment etc. that handle digital data,
An oversampling type A/D converter is used, which reduces the number of analog circuits and uses a digital circuit that can relatively easily obtain high accuracy. This oversampling type A/D converter samples input analog data at a frequency that is appropriate for the original quantization frequency, converts the sampling output, and converts the resulting digital data using a digital filter. It is configured to obtain digital data according to the quantization frequency by averaging over a predetermined period, and it reduces the number of analog circuits, is less susceptible to noise, and has high accuracy. It has the characteristic that it can be obtained.

FIG. 3 is a block diagram showing the configuration of an oversampling type A/D converter.

The sampling circuit 1) determines the frequency f, (7) of the sampling clock SCK, which determines the frequency of the digital output.
) a sampling clock SCK having m times the frequency;
The analog data is sampled according to the data and is provided to the A/D conversion circuit 2>. The A/D conversion circuit (2) converts each piece of sampling data into digital data in synchronization with the operation of the sampling circuit (1). This digital data follows the sampling clock SCK and changes at a cycle of 1/m f'. and,
The digital filter (3) averages the digital data from the A/D conversion circuit (2) over a predetermined period and outputs it in accordance with the sampling clock SCK. That is, A
/D conversion circuit (2) averages m pieces of data over a period m times the period of the digital data output, and performs processing such as removing sampling noise and correcting distortion,
Sampling clock SCK.

Accordingly, digital data that changes at a period of 1/f is output.

The sampling clock SCK used here and S
CK is obtained by dividing the common basic clock BCK, and as shown in FIG. 4, the rising and falling timings are the same.

FIG. 5 shows the sampling clock SCK, and SCK,
FIG. 2 is a block diagram of a clock generation circuit that generates a clock.

The frequency divider (4) is a counter with an appropriate number of bits that counts the basic clock BCK, and the frequency division ratio is determined by selectively taking out one bit of its output. Therefore,
If the n-th bit from the least significant bit of the output is selected, the frequency division ratio becomes 1/2", so the output of the bit that obtains the desired frequency division ratio is the sampling clock SCK, and SCK,
The output will be closed. Further, the output of the frequency divider (4) is input to the decoder (5), and when the output reaches a predetermined value, the decoder (5) outputs the preset signal PR3, and the frequency divider (
4) Initialize. That is, a frequency divider (4
) takes in the preset data PD at the timing based on the preset signal PR3, and the preset data P
Set D as the initial value. The preset data FD is
It is supplied from the register (6>), and the period of the sampling clock SCK and SCK is determined depending on the setting of this value and the setting of the defood value of the decoder (5).

(8) Problems to be Solved by the Invention The A/D converter as described above is configured to take in analog data at the rising timing of the sampling clock SCK and SCK. Therefore,
If it is desired to change the sampling timing, this can be done within a limited range by changing the data in the register (6). For example, preset data PD
By increasing , the period from the initial state of the frequency divider (4) to the predetermined state specified by the decoder (5) becomes shorter, and the timing of sampling becomes earlier by the shorter period.

However, the period t during which the sampling timing is advanced is the period 1/m of the sampling clock SCK.
If the period is longer than 1/2 of f's (1/2mf's), the number of sampling clocks SCK within one period of sampling clock SCK will change, which the digital filter (3) cannot handle. This will lead to malfunction. That is, the sampling clock SCK as shown in FIG.

When the period of SCK I and SCK I is shortened by a period t, only the m-th clock among the m clocks of the sampling clock SCK within one period (1/f,) of the sampling clock SCK is shortened, Period t is 1/2
If it becomes larger than mfs, the m-th clock disappears.

Therefore, the digital filter (3), which is set to receive m digital data during one cycle of the sampling clock SCK, receives only m-1 digital data and cannot operate normally. It will no longer be done.

Therefore, the sampling timing can be changed by at most one cycle <1. /f,) per 1/2 rs f'
s, and there is a problem that it takes time to match the predetermined timing.

Furthermore, if each circuit is reset at a predetermined timing, the sampling timing can be made to match the predetermined timing in an extremely short time. Since data cannot be output until data is input, the start-up of the circuit is delayed.

Therefore, an object of the present invention is to change the sampling timing to a predetermined timing in a short time without causing malfunction of the circuit.

(2) Means for solving the problems The present invention has been made to solve the above problems,
Its features include a sampling circuit that samples analog signals that can be input at a constant cycle, an A/D conversion circuit that converts each sampled data into digital data, and a period that is m times the sampling cycle. An m-times oversampling type A/D converter that obtains one digital data from m continuous sampling data, which is equipped with a digital filter that averages the digital data, and which obtains one digital data from m consecutive sampling data. a first frequency dividing means for obtaining a first clock by dividing the frequency;
a second frequency dividing means for dividing the frequency of the first clock by m to obtain a second clock having a period m times that of the first clock, and transmitting the first clock to the sampling circuit. and a clock generation circuit that also supplies the second clock to the digital filter.

(*) Effect According to the present invention, since the second clock supplied to the digital filter is obtained by dividing the first clock, even if the period of the first clock is shortened, the second clock is The number of clocks of the first clock existing within one period of the clock of You can change the sampling timing by changing the time.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock generation circuit of an A/D converter according to the present invention.

The first and second frequency dividers (11) and (12) each consist of a counter with an appropriate number of bits, and the first frequency divider (11) and (12) operate at high speed.
The frequency divider (11) divides the basic clock BCK by a predetermined frequency division ratio to obtain the sampling clock SCK.

Output. The 20th frequency divider (12), which operates at a lower speed than the first frequency divider (11), uses the sampling clock SCK.
, is divided by m to obtain the sampling clock SCK.

occurs. Then, the output of the 20th frequency divider (12>) is input to the decoder (13), and the decoder (13) receives the preset signal PR5l according to the output of the second frequency divider <12).
and PR5! Output. This preset signal PR8,
and PH1, initialize the first and second frequency dividers <11) and (12) having a counter configuration, and determine the periods of the sampling clocks SCK and SCK. Here, the preset signal PR52 is passed through the second frequency divider (
12) is output when the output reaches a predetermined value, whereas the preset signal PR51 is output from the second frequency divider (12).
The first frequency divider (11) is set to be output every time the output of the sampling clock SCK changes.
, is preset every cycle. The first frequency divider (11
) takes in preset data PD from the register (10) in accordance with the preset signal PR3, and initializes it. This preset data PD determines the period of the sampling clock SCK, and the timing of sampling is changed depending on the setting of this preset data FD. In addition, the preset data set in the second frequency divider (12>) is data such that m clocks of the sampling clock SCK exist within one period of the sampling clock SCK, that is, from the preset timing to the next The data is fixed to count m sampling clocks SCK by the preset timing, and is kept constant even when the sampling timing is changed.Here, the second frequency divider (12
) is reset and initialized.

In the above-described lock generation circuit, changing the sampling clock SCK and the timing of SCK can be easily done by changing the preset data FD of the register (1o). At this time, as shown in Figure 2, if the period of the sampling clock SCK is shortened by the period t to 1/mf''s, the period of the sampling clock SCK t is within the period in which the preset data PD is changed. Therefore, the preset data PD is shortened uniformly by the period of the sampling clock SCK.
If is set small, the period of the sampling clock 5cK0 becomes shorter by the period Kt. Also, since the sampling clock SCK is obtained by dividing the sampling clock scK+ by m, the sampling clock SCK,
There are only m clocks, and the operation of the digital filter (3) that averages the digital data output according to the sampling clock 5CK1 based on the sampling clock SCK is performed reliably.

(g) Effects of the Invention According to the present invention, the timing of sampling analog data can be shifted significantly without causing malfunction of the digital filter, so the timing of sampling can be quickly matched to a predetermined timing.
The operating speed of the circuit can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the clock generation circuit of the A/D converter of the present invention, FIG. 2 is a waveform diagram of the sampling clock, and FIG.
FIG. 4 is a block diagram of an oversampling type A/D converter, FIG. 4 is a waveform diagram of a sampling clock, and FIG. 5 is a block diagram of a conventional clock generation circuit. (1)...Sampling circuit, (2)...A/D
Conversion circuit, (3)...Digital filter, (4)
... Frequency divider, (5) (13) ... Decoder, (6
)(10)...Lujistar, ku11)...First frequency divider, (12)...Second frequency divider.

Claims (2)

[Claims] (1) A sampling circuit that samples the input analog signal at a constant cycle, an A/D conversion circuit that converts this sampling data into digital data for each data, and a period of m times the sampling cycle (m is an integer). A digital filter that averages the above-mentioned digital data over a period of a first frequency dividing means for dividing a clock to obtain a first clock; and a first frequency dividing means for dividing the first clock by m to obtain a second clock having a period m times that of the first clock. 2, and a clock generation circuit that supplies the first clock to the sampling circuit and the second clock to the digital filter. vessel. (2) The first frequency dividing means of the clock generation circuit has a counter that counts the basic clock, and by changing the initial setting of this counter, the period of the first clock is shortened, and the sampling Claim 1, characterized in that the sampling timing of the circuit is changed.
A/D converter described in Section 1.