JPH0325232Y2 - - Google Patents

Description

[Detailed explanation of the idea]

Technical Field of the Invention This invention relates to a microprocessor operating mode designation circuit for processing the output of an AD converter using a microprocessor that can externally designate the operating mode. Prior Art and Problems As a microprocessor in which the operating mode can be specified from the outside, for example, one having the configuration shown in FIG. 1 is known. In the figure, PU is an arithmetic processing unit, RAM is random access memory, ROM is read-only memory, PT1 to PT4 are ports, and E
is the output terminal of the system clock, V _CC is the power supply terminal, X ₁ and X ₂ are the connection terminals of the oscillation crystal XTL,
NMI, IRQ, RST are external interrupt pins, V _CC (SB) is a power supply pin for memory RAM standby mode,
V _SS is a ground terminal, and SC ₁ and SC ₂ are terminals for inputting and outputting signals with different functions depending on the operation mode, such as read/write signals, input/output device selection signals, and strobe signals. Port PT1 consists of pins P ₁₀ to _{P 17} , port PT2 consists of pins P ₂₀ to P ₂₄ , port PT3 consists of pins P ₃₀ to P ₃₇ , port PT4 consists of pins P ₄₀ to _{P 47} , and pins P ₂₀ to P of port PT2 ₂₂ is used to specify the operating mode. This specification of the operation mode is performed, for example, with the configuration shown in FIG. In the same figure, R1 to R3
are resistors, S1 to S3 are switches, and D1 to D3 are diodes. A reset signal rst is applied to the terminal RST, and a low voltage is applied to the pins P ₂₀ to _{P 22} of the port PT2 in response to turning on and off of the switches S1 to S3. (low) level or H (high) level is added. As shown in FIG. 3a, when the power is turned on at time t1 and a voltage of +V is applied to the power supply terminal Vcc,
The reset signal rst is at the L level as shown in FIG. 2B, and is set to the H level at time t2 after a certain period of time from the external circuit such as a power supply stabilizing device. Between times t1 and t2, the registers and the like within the microprocessor are reset to their initial states. Also, at the rising edge of the reset signal rst, the pin
The microprocessor reads the input levels of _P20 to _P22 , sets the operating mode, and starts the program. The relationship between the input levels of pins P ₂₀ to _{P 22} and the operation mode is shown in the table below.

[Table] Therefore, when switches S1 to S3 are turned off,
The operating mode is single-chip, and with internal memory RAM and ROM, it operates as a single-chip processor without external memory. If only switch S3 is turned on, the operating mode becomes 64K address I/O, and the processor operates as a processor that has no internal memory and can be equipped with 64K memory. In addition, input to pin _P20 other than specifying the operation mode is
Processing is performed by the configuration shown in FIG. In the figure, G1 and G2 are gates, EDET is an edge detection circuit, TIM is a timer, and REG is a register. After being reset to the initial state by a reset signal, timer TIM counts system clock clk, and its contents are latched into register REG when gate G2 is opened. In addition, the edge detection circuit EDET is configured to specify whether to detect a rising edge or a falling edge by the program specification signal rf, and when the signal DDR ₂₀ becomes L level, the input signal of the pin P ₂₀ is passed through the gate G1. In the case of rising edge detection, the rising edge of the input signal is detected and the gate G2 is added to the edge detection circuit EDET.
It opens the door. Therefore, the time from the rise to the fall of the input signal can be measured. Further, a system combining the aforementioned microprocessor and an AD converter that converts an analog signal level into a pulse width has a configuration shown in FIG. 5, for example. The AD converter ADC has analog signal input terminals CH1 to CH6 for each channel, terminals A0 to A2 for channel specification, connection terminal _RF for resistor R, connection terminal CAP for capacitor C, power supply terminal _VDD , and ground terminal V. _SS , a start signal input terminal ST, and a comparator output terminal STOP.This output terminal STOP is connected to pin _P20 of port PT2 of the microprocessor μCPU, and terminals ST, A0 to A2 are connected to any port.
Connected to PT. Also, R10 to R12 are resistors, and in this case, resistors R10 to R12 are connected to pins _P20 to _P22 .
Since the H level is input through the pin 12, the single-chip operation mode is designated at the rise of the reset signal rst. In addition, in the AD converter ADC, the channel is specified according to the input signals at the terminals A0 to A2, and when the start signal to the terminal ST is at L level, the analog signal of the specified channel is charged to the capacitor C, and the start signal is started. When the signal becomes H level, the capacitor C is discharged by a constant discharge current determined by the resistor R, the capacitor C, and the like. Since a comparator is built in to compare the terminal voltage of capacitor C with the reference voltage, an H level output appears at the terminal STOP when the terminal voltage of capacitor C is higher than the reference voltage. FIG. 6 is an explanatory diagram of the operation of the apparatus shown in FIG. 5, in which a shows a start signal, b shows a terminal voltage of a capacitor, and c shows an output signal from an output terminal STOP. When the start signal goes to L level after the microprocessor μCPU specifies the channel, the capacitor C is activated by the analog signal of the specified channel.
Charging is performed, and the terminal voltage of the capacitor C corresponds to the level of the analog signal during the period T _C. Further, when the reference voltage is set to 0V, the output signal becomes H level as shown in c in FIG. 6. time
At _T1 , the start signal is set to H level, and the microprocessor μCPU reads the contents of timer TIM and sets it in a data register (not shown). When the start signal becomes H level, the capacitor C is discharged with a constant current, and the terminal voltage of the capacitor C becomes 0V during the discharge period _Td , and the output signal becomes L level, and at this time _T2 ,
Detection of the falling edge of the signal from terminal STOP applied to pin P ₂₀ causes the contents of timer TIM to be latched into register REG, as described with respect to FIG. Upon completion of this latch, an internal interrupt is generated, and the calculation T=T ₂ -T ₁ is performed within the processing routine. Since this time T corresponds to the level of the analog signal, the microprocessor μCPU performs predetermined processing. However, the reset signal immediately after power-on
During the period when rst is at L level, the port PT is in a high impedance state (input mode) and the start terminal ST of the AD converter ADC is in an uncertain state, so the AD converter ADC is in the discharge mode and does not discharge. May start. When the discharge starts, the output of the terminal STOP, and therefore the input of the pin _P20 , becomes L level after a predetermined time (several tens of microseconds to several milliseconds). Therefore, when the reset signal rst becomes H level,
P ₂₀ =L, P ₂₁ =H, P ₂₂ =H, and the operating mode is not single chip but extended multiplex. That is, the desired operation mode is not specified. Purpose of the invention The purpose of this invention is to reliably prevent such errors in operation mode designation with an extremely simple configuration. Therefore, the configuration of the present invention is as shown below. That is, the present invention includes a microprocessor that reads an operating mode designation signal to determine the operating mode at the rising edge of the reset signal immediately after power is turned on, and a charging mode when the start signal is low level and a constant current discharging mode when the start signal is high level. In a system combining an AD converter that outputs a pulse with a time width corresponding to the level of an input analog signal, the microprocessor is connected to a terminal to which one of the operating mode designation signals is applied.
Connect the output terminal of the AD converter and apply the start signal from the microprocessor to the AD converter.
By grounding the converter terminal via a resistor and determining the level state of the start signal, the charge mode operation of the AD converter is used to set the output terminal of the AD converter when resetting the microprocessor. It has a configuration as a microprocessor operation mode designation circuit characterized by determining the level and determining the operation mode designation signal at the time of reset, thereby reliably preventing errors in designation of the operation mode with an extremely simple configuration. be. Embodiment of the invention FIG. 7 is a block diagram of main parts showing an embodiment of this invention, and the same reference numerals as in FIG. 5 indicate the same parts.
R13 is a resistor. This example is an AD converter
The ADC terminal ST is grounded via a pull-down resistor R13. As mentioned above, while the reset signal rst is at L level immediately after the power is turned on, the port PT is in a high impedance state (input mode).
However, if the terminal ST is grounded through the resistor R13, then the terminal ST will be at L level, so
The AD converter ADC is in charging mode and the terminal STOP
The output becomes H level. Therefore, the reset signal
When rst reaches H level, P ₂₀ = H, P ₂₁ = H,
Since P ₂₂ =H, the single-chip operation mode is reliably specified. Effects of the invention As described above, this invention resets the internals to the initial state at the L level of the reset signal rst immediately after power is turned on, and changes the operation mode designation signal applied to pins _P20 to _P22 to the H level of the reset signal rst. The microprocessor μCPU specifies the operating mode by reading at the rising timing of the start signal, and the time width T corresponding to the input analog level is set to charge mode when the start signal is L level, and constant current discharge mode when it is H level.
In a system that combines an AD converter ADC that outputs _pulses of
Measure the time width of the ADC output signal using the microprocessor μCPU's timer TIM, etc., and add a start signal from the microprocessor μCPU.
The terminal ST of the AD converter ADC is grounded via a resistor so that the terminal becomes low level when the reset signal is low level, and the output signal of the AD converter ADC when specifying the operation mode is high.
level, so it is possible to reliably specify the desired operation mode. In addition, the only hardware added for this purpose is a small resistor, and by determining the level state of the start signal, when resetting the microprocessor, the charge mode operation of the AD converter is used to perform the AD converter.
By determining the level of the output terminal of the converter and determining the operation mode designation signal at reset, errors in operation mode designation can be reliably prevented with an extremely simple configuration, and the operation mode of the microprocessor μCDU can be determined with an extremely simple configuration. It is possible to ensure that the designation of

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the microprocessor, Fig. 2 is an explanatory diagram of how to specify the operating mode of the microprocessor, Fig. 3 is an explanatory diagram of power-on and reset signals, and Fig. 4 is an explanatory diagram of the microprocessor time. Figure 5 is a block diagram of the main part of the measuring means. Figure 5 is a block diagram of a system that combines a conventional microprocessor and AD converter. Figure 6 is an explanatory diagram of the operation of the AD converter.
The figure is a block diagram of essential parts of an embodiment of this invention. μCPU is a microprocessor, ADC is an AD converter, PT1 to PT4, PT are ports, _P20 to _P22 are input terminals for operation mode designation signals, RST is input terminal for reset signal rst, R, R10 to R13 are resistors. ,
C is a capacitor, STOP is an output terminal, ST is a start signal input terminal, A0 to A2 are channel designation terminals, and CH1 to CH6 are analog signal input terminals.

Claims (1)

[Scope of utility model registration request] The microprocessor reads the operating mode designation signal at the rising edge of the reset signal immediately after power-on and determines the operating mode, and when the start signal is low level, it is in charging mode, and when it is high level, it is in constant current discharging mode, and the input analog signal is AD that outputs a pulse with a time width corresponding to the level
In a system in which the output terminal of the AD converter is connected to a terminal to which one of the operation mode designation signals of the microprocessor is applied, and the AD converter is applied with the start signal from the microprocessor, By grounding the converter terminal via a resistor and determining the level state of the start signal, the charge mode operation of the AD converter is used to set the output terminal of the AD converter when resetting the microprocessor. A microprocessor operation mode designation circuit characterized in that an operation mode designation signal at the time of reset is determined by determining a level, thereby preventing errors in designation of the operation mode.