JPH0325255U - - Google Patents

Info

Publication number
JPH0325255U
JPH0325255U JP1989085985U JP8598589U JPH0325255U JP H0325255 U JPH0325255 U JP H0325255U JP 1989085985 U JP1989085985 U JP 1989085985U JP 8598589 U JP8598589 U JP 8598589U JP H0325255 U JPH0325255 U JP H0325255U
Authority
JP
Japan
Prior art keywords
integrated circuit
negative power
power source
circuit mounting
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1989085985U
Other languages
English (en)
Japanese (ja)
Other versions
JP2501869Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989085985U priority Critical patent/JP2501869Y2/ja
Publication of JPH0325255U publication Critical patent/JPH0325255U/ja
Application granted granted Critical
Publication of JP2501869Y2 publication Critical patent/JP2501869Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP1989085985U 1989-07-21 1989-07-21 負電源高周波集積回路実装構造 Expired - Lifetime JP2501869Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989085985U JP2501869Y2 (ja) 1989-07-21 1989-07-21 負電源高周波集積回路実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989085985U JP2501869Y2 (ja) 1989-07-21 1989-07-21 負電源高周波集積回路実装構造

Publications (2)

Publication Number Publication Date
JPH0325255U true JPH0325255U (ko) 1991-03-15
JP2501869Y2 JP2501869Y2 (ja) 1996-06-19

Family

ID=31635389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989085985U Expired - Lifetime JP2501869Y2 (ja) 1989-07-21 1989-07-21 負電源高周波集積回路実装構造

Country Status (1)

Country Link
JP (1) JP2501869Y2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001015231A1 (fr) * 1999-08-19 2001-03-01 Seiko Epson Corporation Panneau de cablage, dispositif semiconducteur, procede de fabrication d'un dispositif semiconducteur, carte a circuit imprime et dispositif electronique

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110052U (ko) * 1987-01-08 1988-07-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110052U (ko) * 1987-01-08 1988-07-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001015231A1 (fr) * 1999-08-19 2001-03-01 Seiko Epson Corporation Panneau de cablage, dispositif semiconducteur, procede de fabrication d'un dispositif semiconducteur, carte a circuit imprime et dispositif electronique
US6670700B1 (en) 1999-08-19 2003-12-30 Seiko Epson Corporation Interconnect substrate and semiconductor device electronic instrument

Also Published As

Publication number Publication date
JP2501869Y2 (ja) 1996-06-19

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