JPH03252877A - Memory device - Google Patents

Abstract

PURPOSE:To realize the simplification and the speedup of processing by changing the number of memory small groups to constitute a memory group, and changing data width so that one unit data is read or written per one picture element for every number of bits corresponding to bus size. CONSTITUTION:A memory part 2 is constituted by using 32-pieces (n-pieces) of the memory small groups 8 of readably/writable 8-bits X 1M (mega) words in 8-bits (k-bits) parallel, and has the memory capacity of 32 Mbytes. Each memory small group 8 is constitued by using 8-pieces of the memory chips 9 of 1-bitX1M words. A memory group switching part 3 divides 32-pieces of the memory small groups 8 of the memory part 2 by every adjoining s-pieces into n/s-pieces of the memory groups 10 according to the value of (s) determined from the number of bits 8Xs of the data to be handled. A memory read/write part 5 reads/writes the memory of 8Xs-bits (kXs-bits) in parallel in the order of their addresses. Thus, the simplification and the speedup of the processing can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data width conversion technology in digital data processing, and particularly to a memory device that can accommodate changes in data width.

[Prior Art] Digital images include gradation images in which the data for each pixel is a gradation value representing the shade of color of each pixel, and spot color images in which the data for each pixel is a color identification number called a color number. There is.

Gradation images include single-color binary images, single-color multi-value images, and full-color images that combine primary color multi-value images for the number of primary colors (4 or 3), and the pixel data handled in these images. The width is 1 bit, 8 bits (1 byte), and
32 bits or 24 bits (4 bytes or 3 bytes) are well known.

Spot color images are mainly used as masked images or colored (tinted) images, and the pixel data width used is well known to be 1 bit or 8 bits.

In this way, in digital image processing, the data width changes depending on the type of image being handled.

On the other hand, digital processing devices including computers have a bus size specific to the device, that is, a number of bits that can be accessed in parallel, and it is efficient to process data in units of that number of bits. In particular, in image processing including prepress for stamps, each of the four primary colors of stamps, Y (yellow), M (magenta), C (cyan), and K (black), is converted into 8-bit 2
A bus-sized device capable of parallel processing of 32 bits, which is the data width of one pixel of a full-color image when expressed in 56 gradations, is desirable, and is often used in practice.

[Problems to be Solved by the Invention] However, as mentioned above, some image data have various data widths (number of bits). For example, if the data to be processed has a data width of 1 pixel and 1 byte (8 bits), If they are arranged contiguously on a memory device, if you try to handle them with an image processing device with a 32-bit bus size, you will end up reading and writing every 4 pixels, so this will be modified to read and write every 1 pixel. This requires software processing by the CPU, which poses a problem of increased processing time.

It is conceivable to write data to 8 bits out of every 32 bits on the memory device in accordance with the reading and writing of every 32 bits by the image processing device, but in this case, there is a problem that 3/4 of the memory device is wasted.

This invention was made in view of the above-mentioned circumstances, and even when the data width of pixel data to be processed does not match the bus size of the memory device used for the processing, The data width is changed so that one unit of data per pixel is read and written for each corresponding number of bits, and this is achieved by changing the number of memory chips that make up the memory group, which increases processing time. It is an object of the present invention to provide a memory device that can simplify and speed up processing by performing reading and writing on a pixel-by-pixel basis in a fixed amount of time without incurring problems, and that eliminates waste in the memory device.

[Means for Solving Problem 81] Corresponding to this object, the memory device of the present invention has a memory device of the present invention that can be accessed in parallel by using a memory of several bits as one word.
l word number 0.1.2. . . . A memory section consisting of nlJ of memory small groups of 10 m words each having a memory capacity corresponding to m-1, and a memory section s( that can read/write the n memory small groups in parallel s≦n)
n, which can correspond to memory group number 0.1゜2,... (n/S) -1.
a memory group switching unit that divides the memory into memory groups; and a memory read/write unit that reads/writes k×s bits of memory specified by an address formed by the memory group number and the word number in parallel. It is characterized by having the following.

[Operation] In the memory device configured in this way, for example, 1
When 32 memory small groups are used (k=8.m-1M, n=32>
If the data width is 32 bits, the number of memory subgroups S in the memory group is determined according to the data width of the pixel data etc.
is set to 4 (therefore, the number of memory groups is 8), and in the case of 8 bits, S is switched to 1 (therefore, the number of memory groups is 32), and data can be read and written one word at a time in one memory group. be exposed.

In the former case, data with a data width of 32 bits is handled as 32-bit data, so it can be handled as is by a device with a bus size of 32 bits, and in the latter case, 8-bit or 1-bit data is handled as 32-bit data. However, in this case, the remaining bits among the 32 bits are read and written as undefined data, and in any case, each data is read and written in a fixed time and processed efficiently.

[Embodiment] In FIG. 1, 1 is a memory device. Memory device 1
includes a memory section 2, a memory group switching section 3, and a memory reading/writing section 5.

As shown in FIG. 2, the memory section 2 is constructed using 32 (nl) memory subgroups 8 of 8 bits x IM (mega) words that can be written in 8 bits (k bits) in parallel. It has a memory capacity of 32 Mbytes.Each memory subgroup 8 is constructed using eight 1-bit x 1M word memory chips 9, as shown in FIG.

The memory group switching unit 3 divides the 32 memory subgroups 8 of the memory unit 2 into adjacent S@ groups according to the value of S determined from the number of bits of handled data B×s, and divides them into n/sl memory groups. 10 (see Figures 4 and 5).

The memory section 2 is provided with 25-bit address signal lines 30 (MAO to MA24) as shown in FIG.
The word number designation line 30a is for designating one of the word numbers in a word, and the remaining 5 bits M20 to M24 are the memory group number designation line 30a for designating the memory group number to be read/written.
It is b. However, as explained below, not all of these five bits are always used.

In other words, when the number of bits of data to be handled is 8 x 5 = 32, S = 4, so Confucianism in memory group 10 is n
,'s=6, and the memory group switching unit 3 forms eight memory groups consisting of four adjacent memory subgroups, and one of the eight memory group numbers arranged in order is selected. Since three signal lines are required to specify, MA20~ of the 5 bits is required.
Only MA22 is used, and the remaining MA23°MΔ24 are not used.

Also, if the number of bits of data to be handled is 8XS=16, then s=2, so the memory group number is 16@
Yes, 4 signal lines MA20 to MA23 are used, and if the number of data bits is 8 x S = 8, S = 1 and the number of memory groups is 32, so 511 signal lines MA20-
Use all of MA24. In this way, depending on S, from MA20 to the required number of bits are used.

Since the number S of memory subgroups 8 constituting the memory group 10 as described above can be given by CPtJ etc., S
is variable.

The memory read/write unit 5 reads 8×S bits (k×s bits) of memory in parallel in the order of the addresses, which are specified by the addresses made up of the above-mentioned memory group number and word number in each memory group. /Writable. That is, the memory read/write unit 5 reads/writes the memory unit 2 through the address signal line 30, and reads/writes six memory groups of the memory group numbers specified by the use bit determined by the above-mentioned S from MA20 to MA24. of the memory small group of,
8XS bits corresponding to word numbers specified by MAO to MA19 are read/written in parallel.

However, at this time, if k x s bits is smaller than the data bus size of the external processing device, for example 32 bits,
It is assumed that the remaining bits of the kXS bits are read/written as undefined data. As a result, one unit of data per pixel is read and written for each bit number corresponding to the bus size, and this is achieved by changing the number of memory subgroups 8 that make up the memory group, so reading and writing in units of one pixel is possible. The processing can be carried out within a fixed amount of time, so that the processing time does not increase and the memory device is not wasted.

FIG. 7 shows a method of cutting out an image using three memory devices of the present invention, that is, a full-color image 1111a.
A method of synthesizing the image and mask image 11b to obtain a full-color image 12 will be described.

First, the full-color image 11a is stored in the memory device 111a1, and the mask image 11b is stored in the memory device [1b].

Here, the mask image 11b is binary data in which 1 pixel is 1 bit, and whether the pixel is in the cutout area 14 painted with a predetermined one of the color numbers, or if it is painted with another predetermined color number. It takes two values, A or B, depending on whether it is in the non-cutting area 13 painted by one of the colors.

The full-color image 11a is Y, M, and C as described above.

It has a data width of 32 bits, 8 bits per color, for the four colors of K.

Data for one pixel is read from the memory device 1a1 and the memory device 1b in each cycle, and when the data from the memory device 1b is A (that is, when the pixel is in the cutout area 14), the data from the memory device 1a1 is read. is written as is to the corresponding address of the memory device 1a2 that stores the full-color image 12, and when the data from the memory device 1b is 8 (that is, when the pixel is in the non-cutting area 13)
Instead of the data from the memory device 11al, data with all 32 bits set to O may be written to the corresponding address of the memory device 1a2.

[Effect of the Invention 1] As is clear from the above description, according to the present invention, even when the data width of pixel data to be processed does not match the bus size of the memory device used for the processing, the bus size is The data width is changed so that one unit of data per pixel is read and written for each bit number corresponding to It is possible to perform reading and writing in units of one pixel in a fixed time without causing an increase in the number of pixels, simplifying and speeding up processing, and obtaining a memory device that eliminates waste in the memory device.

[Brief explanation of drawings]

FIG. 1 is a block explanatory diagram showing a memory device of the present invention;
Figure 2 shows one example of the configuration of the memory section of the memory device shown in Figure 1.
3 is a diagram showing the configuration of address signal lines in the memory section of the memory device shown in FIG. 1, FIG. 4 is a plan view showing an example of the configuration of memory groups in the memory section, and FIG. 6 is an explanatory plan view showing another example of the configuration of a memory group in the memory section, FIG. 6 is an explanatory plan view showing the configuration of a small memory group, and FIG. It is an explanatory diagram showing a method of processing. 30a...Word number designation line, 30b...Group number designation line

Claims (2)

[Claims] (1) m word numbers 0, 1, 2, ..., m with k-bit memory that can be accessed in parallel as one word
-1 memory unit consisting of n small memory groups of k bits x m words with a memory capacity that can correspond to
Memory group switching consisting of (s≦n) memory small groups and dividing into n/s memory groups that can correspond to memory group numbers 0, 1, 2, ..., (n/s)-1. and a memory read/write unit that reads/writes k×s bits of memory in parallel specified by an address constituted by the memory group number and the word number. (2) Claim (1) characterized in that said memory small group of k bits x m words is constituted by a combination of memory small groups of t bits x u words (t≦k, u≦m). Memory device (3) The memory group switching section is configured to make the s variable, thereby changing the data width k×s and the address width n/
The memory device according to claim (1), characterized in that s is configured to be variable.