JPH02166547A - Information processor - Google Patents

Abstract

PURPOSE:To improve the DMA (direct memory access) data transfer ability by preparing a data bus of a data transfer unit of N times as much as the transfer unit M of a CPU and a function which changes the address of an address space secured in a main storage. CONSTITUTION:At DMA transfer of data performed by a buffer memory 3, 4 or 5, an address space changing function is used to perform the transfer of data to two banks every 4 bytes. In other words, a data bus 12 has the data transfer width of 4 bytes double as much as 2 bytes, i.e., the data trasnfer unit of a CPU 1. Furthermore a function is added to apparently change a certain address space into another one. Thus the bus occupying time required for the DMA data transfer can be reduced down to 1/2 (=2 bytes/4 bytes) compared with the conventional value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to a DMA (formerly rec
The present invention relates to an information processing apparatus having a channel capable of performing tHenory Access) transfer.

Conventionally, in this type of information processing device, the data transfer unit of the central processing unit and the data transfer unit of DMA are the same.
Alternatively, the data transfer unit in DMA was smaller than the data transfer unit in the central processing unit.

Therefore, the largest data transfer unit is that of the central processing unit, so when a configuration includes multiple input/output devices and channels, data transfer is required when continuously transferring a large amount of data. I couldn't improve my abilities. As a result, not only the data transfer capability of the input/output device cannot be fully utilized, but also the bus occupancy time of the input/output device increases, resulting in a decrease in the processing capability of the central processing unit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that can improve data transfer capability using DMA when continuously transferring a large amount of data.

111 Ports 1 An information processing device according to the present invention includes a main memory and M (M>
0) a central processing unit that transfers data to the main storage device in byte units; a channel that transfers data to the main storage device; and when transferring data from the central processing unit to the main storage device; A predetermined address space of M bytes of the main memory is accessed, and when data is transferred from the channel to the main memory, an address of N (N>1> times the predetermined address space of the main memory) is accessed. The present invention is characterized by comprising an access control means for accessing the space.

Supervisor 1 Tooru Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention. In FIG. Ilo) 6.7 and 8, buffer memories (channels) 3.4 and 5, and a main memory 2, which are connected to each other via a data bus 12.

In this embodiment, the data transfer unit of the central processing unit 1 is 2 Bytel, and the data transfer unit of the input/output devices 6, 7, and 8 is 1 Bytel. In addition, the input/output device 6.
The data from 7 and 8 is converted into a data transfer unit of 4 bytes by buffer memories 3, 4 and 5, and sent to the data bus 12. Note that the data transfer unit of the data bus 12 is 4 [Bytel].

The main memory bag rI12 includes storage areas 9 and 10 and an address control section 11. Address control section 1
1 has a function of changing the address space of the storage area 10 during DMA transfer to make it the same address space as the storage area 9. Furthermore, the data bus 13 has 2 [Byte
The data bus 12 has a width of 4 [Bytel, which is not used by the central processing unit 1 (that is, the remainder) 2
[Connected to Bytel.] In other words, data buses 14 and 15 are connected.

The address space of the storage areas 9 and 10 of the main storage device 2 is 00000 [H] as shown in FIG.
It is assumed that the data from FFFFF [H] is divided into banks 0 to F. It is assumed that banks 0 to F are alternately allocated to storage areas 9 and 10. Therefore, storage area 9 has 0.2
．． 4. Each bank and storage area 10 has 1.
This means that each bank of 3.5... is allocated.

Further, each bank of the storage area 10 is provided with a function to change the address space. Regarding its function,
This will be explained using FIG. FIG. 3 is a block diagram showing the configuration of the function for changing the address space. In FIG. 6,
31 is an addressing register, 32 is a decoder, and 33 is one bank. Other banks within the storage area 10 also have the same configuration.

The address designation register 31 stores in advance data serving as an address signal for designating an address space to be transferred. Then, the output signal B from this address designation register 31 is compared with the original address signal A in the decoder 32, and only when the result shows a match, the enable signal 320 for the corresponding bank becomes active, and the enable signal 320 for the corresponding bank becomes active. Data transfer for all 33 address spaces is performed.

In other words, this address designation register 31 stores data that becomes the original address signal for that bank during transfer from the central processing unit 1, and buffer memories 3.4 and 5
At the time of DMA transfer from , data that becomes the changed bank address signal is stored.

Returning to FIG. 1, the operation of the information processing apparatus of this embodiment having such a configuration will be described.

First, central processing bags? I! At the time of normal transfer from 1, data that becomes the original address signal is stored in the address designation register 31. Therefore, central processing unit 1
Data transfer in units of 2 [Byte] is performed to the bank to be transferred in accordance with the address signal from.

On the other hand, at the time of DMA transfer from buffer storage 3.4 or 5, the above-mentioned address space changing function is used to transfer data in units of 4 [Byte] to two banks. In this case, for example, when changing the address space of bank 8 in FIG. As a result, bank 8 is apparently assigned the same address as bank 7. Therefore, access to bank 7 is also performed simultaneously to successive adjacent bank 8.

In other words, in this embodiment, a data bus 12 is provided with a data transfer width of 2 Bytes, which is the data transfer unit of the central processing unit 1, and 4 Bytes, which is twice the data transfer width of the central processing unit 1. By providing a function to change the bus occupancy time during DMA transfer, the bus occupancy time during DMA transfer is reduced to 1/2 (=2 [Bytel/4 [Bytel
) can be done.

In this embodiment, a case has been described in which the function of changing the address space is provided only for each bank in the storage area 9, but all banks in the main storage device 2 (i.e.,
It is clear that the storage areas 9 and 10) may be provided with this function.

In that case, the address space can be changed more freely by rewriting the address designation register.

Furthermore, in this embodiment, the case where two consecutive banks (for example, banks 7 and 8) are accessed simultaneously is explained, but the addressing registers can also be used for non-consecutive banks (for example, banks 7 and A). It is also clear that simultaneous access is possible by rewriting .

Furthermore, in this embodiment, the data transfer unit handled by the central processing unit is 2 Bytes, and the data transfer unit by DMA transfer is 4 Bytes. It is clear that it can be 0, for example, a central processing unit! The data transfer unit handled by 4 [Bytel, D
If the data transfer unit by MA transfer is 5 bytes, it becomes 5/4=1.25 (=N) times, and the bus occupation time can also be shortened. However, if N>1, the bus occupation time cannot be shortened.

As explained above, the present invention provides a function to change the address of the data bus and the address space in the main memory in a data transfer unit that is N times the data transfer unit M of the central processing unit. During DMA transfer, N times the normal transfer is possible, which has the effect of shortening the data bus occupation time and improving the data transfer capability by DMA transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing the address space of the main storage device, and FIG. 3 is an address space provided in the address control unit 11. FIG. Explanation of symbols of main parts 1...Central processing unit 2...Main memory 3.4.5...Buffer storage 6.7.8... Input/output device 12...Data bus

Claims (1)

[Claims] (1) A main storage device, a central processing unit that transfers data to the main storage device in units of M (M>0) bytes, a channel that transfers data to the main storage device, and the central processing unit. When transferring data from the device to the main storage device,
When accessing a predetermined M-byte address space of the main memory, and transferring data from the channel to the main memory, an address that is N (N>1) times the predetermined address space of the main memory. An information processing device comprising: access control means for accessing a space.