JPH03253295A - Signal generation circuit - Google Patents

Abstract

PURPOSE:To reduce a burden of preparation of a program by providing a central processing circuit processing a signal, a register storing data on an initial value, a memory storing data on a waveform, a means of specifying an address of the waveform data, a signal processing means of outputting the signal, and a means of switching a data bus. CONSTITUTION:An address of ROM 28 is specified based on data on an initial value. Then, data Da, Db and Dc on a waveform of the aforesaid address are read out. A signal processing means 36 applies a signal processing to the waveform data Da, Db and Dc and outputs the results. Next, a count operation is executed when a signal led out to a multiplexer 27 coincides with the address data and when a theoretical value of a fourth bit of a register CONT is zero. When a count value of a register CNT 12 is a prescribed value, thereafter, an interrupt is generated and a desired value can be set in the register CNT 12. When a count value of a register CNTFF is a prescribed value or above, an interrupt signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application The present invention is useful for controlling the rotation of motors controlled by pulse width modulated (PWM) signals, such as compressors or stepping motors used, for example, in air conditioners with inverter circuits. The present invention relates to a signal generation circuit suitably implemented for control purposes.

Conventional technology For example, variable voltage systems such as transformer tap switching and phase control have been used to control the rotation of stepping motors and three-phase AC motors used in near conditioners. Due to problems such as noise generation, inverter systems have come to be used instead. In the above method, a signal generation circuit is configured with a so-called one-chip microcomputer, etc., and a control signal is output from the signal generation circuit to control a DC/AC inverter, thereby driving the motor with power at a frequency corresponding to the desired rotation speed. By driving, rotation control is performed smoothly.

FIG. 13 is a block diagram showing a configuration for controlling the compressor 12 using the signal generation circuit 1 of the prior art. The signal generation circuit 1 includes a register 4 connected via a data bus 2, a read-only memory (ROM) 5, a central processing circuit (CPU) 3, an internal timer 6, and an input/output register 7.

The ROM 5 stores an operation program and waveform data for the signal generating circuit 1. The CPU 3 selectively reads waveform data from the ROM 5 with reference to the data stored in the register 4 in accordance with this operating program.

Furthermore, signal processing such as data conversion is performed based on the data stored in the register 4, and the signal is outputted to the outside via the input/output register 7. At this time, an interrupt signal generated by internal timer 6 is applied to CPU 3 via line 8, thereby controlling the timing of the output signal.

The signal output from the signal generation circuit 1 is applied to the transistors T1 to T6 of the inverter 13 via the delay circuit 9 and the photocoupler 10. The delay circuit 9 is provided in consideration of the turn-off time of the transistors T1 to T6, and the photocoupler 10 is provided to prevent external noise from occurring in the signal generation circuit l.
is prevented from being input. Transistor Tl,
T2, transistor T3. T4 and transistor T5
゜T6 are connected in series, and the transistors Tl, T3 . A power supply voltage from the power supply circuit 11 is applied in parallel to the collector of T5. Output signals SL and Sl of the photocoupler 10 are applied to the bases of transistors TI and T2, respectively, and output signals S2. S2 is a transistor T
3. T4, respectively, and output signals S3.
S3 is a transistor T5. Each is given to the base of T6. Connection of transistors TI and T2, transistor T3. The signals at the connection of T4 and the connection of transistors T5 and T6 are connected to lines 1a, 1b.

Each signal is applied to the compressor 12 via the IC.

The compressor 12 is operated, for example, by a three-phase AC motor, equivalently having coils 12a, 12b.

12c. Coils 12a-12
One end of c is connected to the line 1 mentioned above.
a-lc are connected to the other ends of the coils 12a-12c, respectively.

In this way, the inverter 13 converts the DC output from the power supply circuit 11 into a rectangular wave equivalent to three-phase AC, and applies it to the coils 12a to 12c, thereby changing the operating state of the compressor 12, that is, the rotational speed of the motor. controlled.

Problems to be Solved by the Invention When controlling the operating state of the compressor 12 using the signal generating circuit 1 described above, it is necessary to create a program stored in the ROM 5 in order to operate the signal generating circuit 1. Since all operations such as reading waveform data from ROM 5 and converting this waveform data are performed according to the program, the program itself becomes large and the burden of creating software increases. be. Moreover, the waveform of the output signal changes slightly depending on the time required to execute each subroutine of the program and the time required to execute each instruction included in the program (cycle time). Therefore, this signal generating circuit 1 has a problem in that it cannot generate a signal having a highly accurate pulse waveform.

In order to solve the above-mentioned problems, the configuration of the signal generating port II@15 shown in FIG. 14 can be considered. In addition, the 13th
Parts that are the same as or correspond to those in the figures are designated by the same reference numerals.

The signal generation circuit 15 includes a central processing circuit (CPU) 3 realized by a microcomputer or the like, a random access memory (RAM>16), and a plurality of one-way only memories (RO).
M) 17.18. It is composed of each block of the waveform generation circuit 19. In the plurality of ROMs 17 and 18, the program-dedicated ROM 17 stores in advance the operating programs necessary for the operation of the CPU 3, and the waveform data-dedicated ROM
M18 has a 3-phase AC waveform applied to the compressor 12 (
For example, waveform data regarding 60I(Z) is stored in advance. Further, data such as the motor rotation speed set by an external controller (not shown) and temperature information from a temperature sensor are written in the RAM 16.

Each block has a data bus fl, a control bus 12
．． They are interconnected via 13. The CPU 3 instructs the read/write mode of each block via the control buses 12 and 13, and specifies the address necessary for reading via the address bus 14. The operating program read from the program-only ROM 17 and the corresponding data in the setting data read from the RAM 16 are transferred to the C'P U 3 and the waveform generation circuit 1 via the data bus 11.
9 respectively.

A waveform data bus 15 and an address bus 16 are connected between the waveform generation circuit 19 and the waveform data-dedicated ROM 18.
The waveform data is selectively read from the waveform data-dedicated ROM 18. Addressing necessary for this reading is performed via the address bus 16.

In the waveform generation circuit 19, signal processing such as data conversion is performed based on the waveform data read from the waveform data-dedicated ROM 18 and according to initial value data set in advance by the CPU 3. Further, the timing is controlled by an interrupt signal from an internal timer (not shown), and control signals Sl, Sl, S2 . S2
・, S3°S3 is created.

The control signals 81 to S3 control the conduction/cutoff timing of the transistors T1 to T6 in a predetermined phase order as described above, and the inverter 13 converts the supplied DC output into a rectangular wave equivalent to three-phase AC. , is applied to each coil 12a to 12c of the compressor 12. In this way, the rotational speed of the motor is controlled.

With the above-described configuration, after predetermined initial value data is set from the CPU 3 to the waveform generation circuit 19, the waveform generation circuit 19 consisting of hardware automatically converts the address designation data, and the waveform data dedicated ROM 18 After reading the waveform data from and converting the data, control signals 81 to S
3 and output to the inverter 13. That is, after setting the initial value data, the conversion process of the waveform data includes C
There is no need for the PU3 to be involved, so there is no need to create a program for such addressing and waveform data conversion, and the burden of program creation is greatly reduced. Since the instruction cycle time of the CPU 3 does not tend to change in waveform depending on the length of the subroutine of the program, it is considered that a highly accurate signal can be output.

However, in the configuration of the signal generation circuit 15, C
A ROM 17 dedicated to operation programs is associated with PU'3, and a ROM 1 dedicated to waveform data is associated with the waveform generation circuit 7.
At least two memories of 8 are required separately.

On the other hand, at the development stage of a system using a microcomputer, the ROM constituting the system is an E F ROM (Erasable Programmer) that can be written and erased.
A common method is to replace the program with a logical ROM (ROM) and create a program by trial and error, and a piggyback 51 shown in FIG. 15 is used for this purpose. The piggyback 51 has an EPROM socket 51b mounted on a package 51a containing a microcomputer, and inserts the EPROM into the socket 51b to freely rewrite the application program as many times as needed to complete the final program. It is a tool for Also piggyback 51
It is also possible to perform a product mounting check using .

Therefore, in order to create a program necessary for the signal generation circuit 15 described above using such a piggyback 51, the package 51a must be equipped with at least two sockets 51b;
This is difficult due to the space of 1a. Therefore, it takes time and effort to write an operating program into one EPROM and examine it, and then write waveform data into the other EPROM and examine it, resulting in high costs in terms of time and labor for creating the program.

Therefore, an object of the present invention is to provide a signal generation circuit that can significantly reduce the burden of creating a program and generate a signal having a highly accurate pulse waveform.

Means for Solving the Problems The present invention includes a central processing circuit that processes signals based on an operation program, and a system that is connected to the central processing circuit via a data bus and has initial value data that serves as a reference for output signals. remembered1
one or more registers, a memory in which waveform data regarding the operating program and the signal to be output are stored, and an address of the waveform data to be stored in the memory based on initial value data stored in the register; addressing means; signal processing means for responding to the waveform data from the memory, performing signal processing on the waveform data based on initial value data stored in the register, and outputting the signal to the outside; Corresponding to the reading of the operating program from the memory to the central processing circuit and the reading of waveform data from the memory to the signal processing means, a data bus between the central processing circuit and the memory and a connection between the signal processing means and the memory are provided. and switching means for switching data buses between the two.

Operation According to the signal generation circuit of the present invention, the memory stores an operation program to be processed by the central processing circuit and waveform data for output signals.

Initial value data serving as a reference for the signal output from the central processing circuit is set in one or more registers, and based on the initial value data, the addressing means determines the address of the waveform data stored in the memory. specify.

The waveform data at the designated address is read out by the signal processing means, and the signal processing means performs signal processing on the waveform data and outputs the signal to the outside. Therefore, since the waveform data is read from the address specified by the addressing means, the central processing circuit is not directly involved in memory addressing, and a program for reading the waveform data is not required. Since the read waveform data is subjected to signal processing by the signal processing means, there is no need for a program related to such signal processing, and moreover, the addressing means and the signal processing means are provided independently of the central processing circuit. , the signal generation circuit according to the invention is capable of performing processing operations at high speed.
A signal having a highly accurate pulse waveform can be output.

Furthermore, reading out the waveform data to the signal processing means does not need to go through the central processing circuit, so only when reading out the waveform data is the path line between the memory and the central processing circuit connected to the memory and the waveform generation circuit. The switching means switches to the pass line between the two. Therefore, the waveform data and the operation program can be stored in the same memory, and the time required to create the program and the amount of space occupied by piggybacking during the rM generation stage can be significantly reduced.

Embodiment FIG. 1 is a block diagram showing a simplified configuration of a signal generation circuit 21 according to an embodiment of the present invention, and FIG. 2 shows a case where the operating state of a compressor 42 is controlled using the signal generation circuit 21. FIG. 2 is a block diagram showing the configuration of FIG. For example, a control signal output from the signal generating circuit 21 of this embodiment is given to the inverter 43, and the operation of the compressor 42, that is, the rotation speed of the motor as a load, etc. are controlled. A photocoupler 40 is interposed and connected between the signal generation circuit 21 and the inverter 43 in order to suppress disturbances such as noise.

The signal generation circuit 21 is a central processing circuit (hereinafter referred to as rcPUJ) 34 realized by a microcomputer or the like.
, random access memory (hereinafter referred to as rRAMJ)
) 45, read-only memory (hereinafter referred to as FROM) 28, consists of each block of the waveform generation circuit 46 and line selection switches 47a, 47b, 47c as switching means, the blocks of the waveform generation circuit 46 are Inside, it includes a plurality of registers and addressing means 35, which will be described later, and further a signal processing means 36.

In the ROM 28, an operation program P necessary for the operation of the CPU 34 and waveform data regarding a three-phase AC waveform to be applied to the compressor 42 are stored in a predetermined area. Further, data such as the motor rotation speed set by the external controller 20 and temperature information from the temperature sensor are written in the RAM 45. In this embodiment, the line changeover switches 47a to 47c are provided, and the CPU 3
4 and the ROM 28, the switching contacts SW1 to SW3 of the line changeover switches 47a to 47c are
is set on the CPU 34 side, and the path line 115. is set for address data. &16, pass lines 111 and #12 for program data, and read control buses 118 and f19 are connected, respectively. CPU3
4 controls other blocks, such as setting initial value data F to the registers forming the waveform generation circuit 46 via the pass line 124, based on the read operation program P.

On the other hand, when requesting reading of waveform data from the ROM 28, a switching request signal Dk is output from the waveform generating circuit 46 to the CPU 34 via the line 122, and the CPU 34
Then, in response to the switching request signal Dk, a bus switching signal Bk is outputted via the line 123, and switching contacts SW1 to SW3 of the line switching switches 47a to 47c are switched to the waveform generation circuit 46 side. As a result, the waveform data pass lines /12 and 113, the address data pass lines 116 and 117, and the read control buses I19 and 120 are interconnected.

CP to the waveform generation circuit 46 in which the initial value data F is set.
U34 is not involved, therefore, the address data is transferred from the waveform generation circuit 46 to the RAM 45 and the ROM 28, and the data in the RAM 45 and the ROM 2 are transferred.
When reading out the waveform data of No. 8, it is not necessary to connect the pass lines for address data and waveform data to the CPU 34.

That is, the CPU 34 is in a standby state. In this way, the waveform generation circuit 46 outputs the read command RD, and necessary addressing and waveform data transfer are performed between the waveform generation circuit 46 and the ROM 28. When the waveform data is stored in the waveform generation circuit 46, the bus switching signal B
k, the switching contacts SW1 to SW3 of the line changeover switches 47a to 47c return to the CPU 34 side, and thereafter,
The CPU 34 executes the suspended operation program.

Note that the write control bus 121 is always connected to the CPU 34.
, the waveform generating circuit 46 and the RAM 45.

Therefore, according to this embodiment, depending on the timing at which the operating program P is read out in the CPU 34 and the timing at which the waveform data is read out at the waveform generation port 46,
From the memory to the CPU 34 and the waveform generation circuit 46
Since the configuration is such that the path lines to the ROM 28 are individually switched, even if different types of data are stored in the common ROM 28, the problem of data bus occupancy when reading data does not occur. memory of R
Since the operating program P and waveform data can be stored in the OM 28, it is possible to sufficiently reduce the cost of space, time, and labor when creating a program by piggybacking as described in the prior art during the development stage.

Furthermore, the waveform generation circuit 46 uses a so-called direct memory access (abbreviation DMA) transfer method in which an address is directly specified to the ROM 28 and the read waveform data is directly read, and the waveform data can be directly read without the intervention of the CPU 34. Therefore, there is no need to write a program for reading waveform data into the ROM 28, and there is no need for a program to process the waveform data.Therefore, the burden of program creation is significantly reduced, and the process can be performed at high speed. Since waveform data can be read, control responsiveness is greatly improved.

A configuration for controlling the compressor 42 using a control signal from the signal generation circuit 21 will be described below with reference to FIG. A clock signal CK for operating the signal generation circuit 21 is provided from a clock signal generation circuit 39 via a terminal T9.

The signal output from this signal generation circuit 21 is given to the transistors Tri to Tr6 of the converter 43 via the photocoupler 40 as described above.

Transistors Trl, Tr2, transistors Tr3, T
r4 and transistor Tr5. The transistors Tr6 are connected in series, and the transistors Tr 1 and Tr
A DC power supply voltage from a power supply circuit 41 is applied in parallel to the collectors of T.3 and T.sub.r5. The output signals R1, R1 of the photocoupler 40 are applied to the bases of the transistors Tri, Tr2, respectively, and the output signals R2, R2 are applied to the bases of the transistors Tr3. The output signals R3 and R3 are given to the bases of Tr4, respectively, and the output signals R3 and R3 are provided to the bases of transistors T r 5 and T r
6 bases each. Transistor Tr
1, connection portion of Tr2, transistor Tr3. Connection portion of Tr4 and transistor Tr5. Signals at the connections of Tr 6 are applied to compressors 42 via lines La, Lb, and Lc, respectively.

The compressor 42 is operated, for example, by a three-phase AC motor, equivalently having coils 42a, 42b.

42C. Coils 42a-42
One end of c is connected to the above-mentioned line L.
a to Lc are connected to the other ends of the coils 42a to 42c, respectively.

In this way, the inverter 43 converts the DC output from the power supply circuit 41 into a rectangular wave equivalent to three-phase AC, and applies it to the coils 42a to 42c, thereby changing the operating state of the compressor 42, that is, the rotational speed of the motor. controlled.

Note that the photocoupler 40 is different from, for example, a photodiode and a phototransistor, and since its output voltage is inverted from the input voltage, it is represented using the symbol of an inverter in FIG.

The specific configuration of the signal generation circuit 21 will be explained below with reference to FIG.

This signal generation circuit 21 includes an addressing means 35, a ROM 28 in which waveform data is stored, a signal processing means 36,
Furthermore, it is configured to include a plurality of registers. Note that a plurality of registers are indicated using the same reference numeral as the register name. These registers are connected to the CPU 34 via an address bus and a data bus 124 (not shown), and the initial value data F is input at a predetermined timing. Set. The address and register name of each register are shown in Table 1.

(Left below) Table 1 The address designation means 35 includes, for example, a logical product n22, an up counter 23, an address signal generation circuit 24, a coincidence determination circuit 26, and a multiplexer 27.The above-mentioned clock signal generation circuit A clock signal CK of, for example, 4 MHz generated by the circuit 39 is applied to one input terminal of the AND circuit 22 via the terminal T9.

Furthermore, the 7th bit of the register C0NT is a start flag, and the logical value of this 7th bit is the AND circuit 22.
is applied to the other input terminal of

For example, the initial value data F set in the register SAMP is set as an initial value in the up counter 23 having a 10-bit configuration, and the up counter 23 performs counting operation based on the output from the AND circuit 22. When the up counter 23 overflows, , for example, a high level signal is applied to the address signal generation circuit 24. This address signal generation circuit 24 is, for example, a 13-bit up/down counter, and performs a counting operation at the rising edge of the signal from the up counter 23. The operation mode of the counting operation is based on the control signal from the decoder 29. It is set as described below.

Further, the signal that becomes the high level is the switching request signal D.
It is given to the CPU 34 as k. In the CPU 34, in response to the signal Dk, the line 1 shown in FIG.
23, the switching contacts SW1 to SW3 of the line changeover switches 47a to 47C are switched to the waveform generation circuit 46 side, and the address data is designated and the waveform data is transferred to the ROM 28 as described later. Execute.

The initial value of address signal generation circuit 24 is given from multiplexer 27 . The multiplexer 27 selects the values stored in the register 5TRT and the register END according to a signal from a decoder 29, which will be described later, and outputs the selected value to the address signal generation circuit 24. multiplexer 2
The output from 7 is also given to the match determination circuit 26. The match determining circuit 26 compares the data derived from the multiplexer 27 and the address data output from the address signal generating circuit 24, and outputs a signal that goes high, for example, when the two match.

The register CNT12 is a counter that counts, for example, from "0" to "11", and performs a counting operation based on a match judgment signal from the match judgment circuit 26. At this time, the register CNT12 is a counter that counts from "0" to "11". 4th in
If the bit is "0", the count up number is preset by the sixth and fifth bits of register C0NT. Further, when the fourth bit of the register C0NT is "1", the register CNT12 is not used as a counter, and an arbitrary value is set by the CPU 34.

The data stored in register CNT12 is sent to decoder 29.
Based on this numerical value, the address designation manner in the address signal generation circuit 24, the derived data selection manner in the multiplexer 27, and the data Q conversion manner in the data conversion circuit 3o are set.

Note that the fourth bit of register C0NT is rQ.

If this is the case, that is, if the register CNT12 is used as a counter, then the switch 25 will cause a signal to go high, for example, to the line 38 when the register CNT12 overflows. Further, when the fourth bit of the register C0NT is "1", the signal from the match determination circuit 26 is led out to the line 38 by the switch 25. The signal on line 38 is CP
It is given to U34 as an interrupt signal. register c.

When the fourth bit of NT is "1", the third to Oth bits of register CNT12 are set to desired numerical values by the interrupt processing by this interrupt signal. Also line 38
The signal is the register CNTFF, which is a 1-byte counter.
This also provides the CPU 34 with an interrupt signal every 256 cycles of signal generation. That is, the initial value data F etc. to each register are updated by interrupt processing executed at the timing of these interrupt signals, etc.
As a result, the frequency of the power applied to the motor can be smoothly changed to achieve optimal control.

The ROM 28 is a read-only memory having, for example, 8 bytes and 3 bits, and the address signal generation circuit 24
The 3-bit data of the address designated by the address data via the line changeover switch 47a is outputted to the signal processing means 36 via the line changeover switch 47b as waveform data Da, Db, and Dc, respectively.

The signal processing means 36 includes a data conversion circuit 30, a rise delay circuit 31, and an output circuit 32. Waveform data Da, Db, D from ROM28
c is given to the data conversion circuit 30.

The data conversion circuit 30 converts data based on the signal from the decoder 29 described above, and generates a signal Ea.

Output to 31. The rise delay circuit 31 receives these signals E
The rising edges of a to Ec and Ea to Ec are delayed by a delay time d set by the third to Oth bits of the register C0NT, and the signal signals Fa to Pc are generated.

It is output to the output circuit 32 as Fa to Fc. Output circuit 3
2 is for driving the photocoupler 40 described above based on the signals F a to F c and F a to F c.
The signals Pa to Pc and Pa to Pc for controlling the compressor 42 described above are connected to the terminal T with a suction current of 20 mA.
1 to T6.

Note that the output operation of the output circuit 32 can be stopped by sending a stop signal from the outside to the latch circuit 33 via the terminal T7. Also, this stop signal is C
This becomes an interrupt signal to the PU34.

The operation of the signal generation circuit 21 will be briefly described below with reference to the flowchart of FIG. Signal generation circuit 21
In step n1, initial value data F to be stored in each register group of the signal generation circuit 21 is set, prior to generating a signal for controlling the compressor 42 from 0.Next, in step n2, initial value data F to be stored in the registers is set. Based on the initial value data F stored in the ROM 28 by the addressing means 35,
address is specified. At this time, the switching contacts SWI to SW3 of the line changeover switches 47a to 47c are set to the waveform generation circuit 46 side. This allows step n3
The waveform data of that address D a , D b , D
c is output and read out by the signal processing means 36.

After the reading, the switching contact pieces SW1 to SW3 are connected to the CPU 3.
Based on the bus switching signal Bk from 4, the setting is switched to the CPU 34 side.

In step n4, the signal processing means 36 performs signal processing on the waveform data Da, Db, Dc,
In step n5, the signal processing results are output as signals Pa to Pc,
Output as Pa to Pc.

Next, in step n6, it is determined whether the signal derived by the multiplexer 27 and the address data output from the address signal generation circuit 24 match. If they do not match, address signal generation circuit 2
The address data output from 4 is incremented or decremented, and the process returns to step n2 described above. If the determination at step n6 is affirmative, the processing operation branches depending on the logical value of the fourth bit of register C0NT. If this logical value is "0", a counting operation is performed using register CNT12. The count-up number at this time is the register C0N as mentioned above.
Set by the fifth and sixth bits of T.

Thereafter, in step n9, it is determined whether the count value in the register CNTl2 is a predetermined value, that is, 12 or more. If this judgment is negative, address signal generation port #! The initial value of the address data output from 24 is set again, and the process returns to step n2 described above. Also, if this judgment is affirmative, step nlo, which will be described later.
Move to.

If the value of the fourth bit of register C0NT is "1" in step n7, an interrupt is generated in step nlo, and the CPU 34 uses this interrupt to set a desired value in register CNT12 in the interrupt processing routine. register C in step nll due to the input signal.
A count-up operation of NTFF is performed, and step n1
2, the count value of register CNTFF becomes the predetermined value 256.
It is determined whether or not this is the case. If this determination is negative, the address signal generated from the address signal generation circuit 24 is set again and the process returns to step n2 described above.

If this determination is affirmative, the process moves to step n13 and an interrupt signal is generated.

In this embodiment, the CPU 34 can be configured to perform a predetermined interrupt operation such as updating the initial value data F of each register when an interrupt signal is input.

In this way, the signal processing means 36 outputs the signal to the compressor 4.
Signals Pa~Pc, Pa~ for controlling the operating state of 2
Pc is output.

Each operation in the signal generation circuit 21 will be described in detail below.

■The sampling time setting signal generation circuit 21 receives the waveform data Da from the ROM 28.
The time interval for reading ~Dc (hereinafter referred to as sampling time) can be changed based on the initial value data set in the register SAMP. Register SAMP is stored in a storage area specified by address number FF25h ("h" indicates hexadecimal notation) and address number FF26h, and the meaning of each bit is as shown in Table 2.

(Margins below) Table 2: address number FF25h represents the lower 8 bits of data representing the sampling time, and address number FF2
The lower 2 bits of 6h represent the upper 2 bits of data representing the sampling time. Therefore, the data representing the sampling time can take values from 00h to 3FFh. This value becomes the initial value of the up counter 23.

Since the up counter 23 performs counting operation using a clock signal of maximum 4 MHz, the sampling time is OOh.
It is possible to select every 0.25 μsec from 256 μsec to 0.25 μsec corresponding to ~3FFh. Note that when the data representing the sampling time is OOh, the sampling time is 256 μsec.

The seventh bit of the address number FF26h is an up counter set flag, and when the logic value "1" is set, data representing the sampling time is set in the up counter 23 as an initial value. After being set as the initial value, this up counter set flag is set to “O”.
”.

(2) Creation of Waveform Data The address signal generation circuit 24 outputs address data to the ROM 28 every time the signal from the up counter 23 rises. The waveform data stored in this ROM 28 is created as described below and is stored in advance.

The waveform of the three-phase AC required to drive the three-phase AC motor is the fifth waveform.
As shown in Figure (1), the phases are 2π/3 (
The rotational speed of the motor is controlled by changing the frequency of the three-phase sine waves 11 to 13 separated by 120'').

The variable range of the frequency is, for example, 20 to 180 Hz. The waveform data Da to Dc are a triangular wave 14 with a period of 2π/n (n is an integer, and n=24 in FIG. 5(2)) shown in FIG. 5(2), and a triangular wave 14 shown in FIG.
13 by sampling with pulse width modulation (PWM).

In FIG. 6, as an example, 30
To explain the generation of degree waveform data Da to Dc,
A waveform diagram showing the waveform of three-phase alternating current at the time θl is shown.

That is, the time .theta.1 is further time-divided into, for example, 16 times corresponding to 16 bits, and the magnitudes of the sine waves 11-13 and the triangular wave 14 at each time tO-t15 are compared. Waveform data Da is created by comparing the sine wave 11 and the triangular wave 14, waveform data Db is created by comparing the sine wave 12 and the triangular wave 14, and further waveform data Db is created by comparing the sine wave 12 and the triangular wave 14.
Data Dc is created by comparison with 4. In other words, at each time tO to t15, if the values of the sine waves 11 to 13 are less than or equal to the value of the triangular wave 14, the logical value of the waveform data becomes "0", and the values of the sine waves 11 to 13 become the value of the triangular wave 14. If the waveform data exceeds Da, the logical value of the waveform data becomes "1".
~Dc is shown in Table 3. Note that the bit length of the data increases or decreases depending on the number of divisions, and the triangular wave 1 to which pulse modulation is applied
The sampling accuracy is determined by the period of 4. Therefore, the accuracy improves as the period of the triangular wave 14 becomes shorter and the number of divisions increases.

(Left below) Table 3 When generating one cycle of signals from 30 degrees of waveform data as described later, the data conversion circuit 30 performs data conversion on the 30 degrees of waveform data as described below. waveform data over a - period is obtained. For example, from the waveform data Da for 30 degrees shown in Table 3, the waveform data shown in Table 4 is created by data conversion.

Table 4 In Table 4, waveform data (-Da) is waveform data Da.
It is the reverse direction of each logical value arranged in chronological order,
This can be obtained by updating the address specification direction in the opposite direction.

Further, the waveform data Da can be obtained by inverting the waveform data Da. Therefore, the waveform data (-D
a) is the inversion of the waveform data (-Da).

(2) Conversion of Waveform Data The waveform data Da to DC output from the ROM 28 are converted in a plurality of ways according to the initial value data F set in the registers C0NT and CNTl2.

The contents of register C0NT are shown in Table 5.

(Left below) Table 5 The Oth bit to the third bit of the register C0NT are used to set a delay time d as described later. Further, the fourth bit serves as a selection flag for selecting whether or not to use the register CNT12 as a counter, as described above.

The fifth pit and the sixth bit are provided for selecting the type of waveform data. Note that the seventh bit is a start flag, and when the logical value is "O", output of the signal from the signal generating circuit 21 is stopped. When this start flag changes from "0" to "1", register CN
T12 and register CNTFF, which will be described later, have an initial value of “O”.
”, and registers 5TRT, END, and S
The most significant bit of AMP is reset.

The third bit to the Oth bit of the register CNT12 are provided to set the conversion mode of the waveform data, and when the fourth bit of the register C0NT mentioned above is "1", the CPU 34 can input any numerical value ( 0 to 11) can be set. The relationship between the values of the third bit to the Oth bit of the register CNT12 and the data conversion mode is shown in Table 7, as will be described later.

If the fourth bit of register C0NT is "OJ," the third to Oth bits of register CNT12 are used as a counter. The relationship with the number of ups is shown in Table 6.

Table 6 below describes in detail the conversion of waveform data Da to Dc for each value of the sixth to fourth bits of register C0NT.

(a) The 6th to 4th bits of register C0NT are r
o 00 J, the 6th to 4th bits of register C0NT are ro 0
In the case of 0 J, one cycle of output signal is generated from 30 degrees of waveform data. At this time, register CNT12
The count-up number is set to "+1", and the counting operation is performed sequentially from "O" to "11" with the count-up number "10l". This results in 30 degrees worth of waveform data D a
-D c is the angle θa1 to θa in Fig. 7 in one cycle.
The data will be read out 12 times by 12 times.

Further, a signal is derived from the decoder 29 to the address signal generation circuit 24 and the multiplexer 27 based on the Oth bit of the register CNT12.

Therefore, when the O-th bit of register CNT12 is "0", multiplexer 27 first outputs register 5T.
Derive the numerical value stored in RT.

As a result, the initial value of the address signal generation circuit 24 becomes the initial value data F stored in the register 5TRT. Further, the address signal generation simultaneous 24 functions as an up counter based on the signal from the decoder 29, and specifies the address value while sequentially incrementing it. At this time, the multiplexer 27 is switched to derive the register END, and the match determination circuit 26 compares the address data from the address signal generation circuit 24 with the initial value data F stored in the register END. In this case, when the address is specified, for example, 16 times by the address signal generation circuit 24, the output of the match determination circuit 26 changes to, for example, a high level.

Further, when the 0th bit of the register CNT12 is "1", the multiplexer 27 first derives the initial value data F stored in the register END to the address signal generating circuit 24. In this case, the address signal generation circuit 24 functions as a down counter by the control signal from the decoder 29.

When the address is specified 16 times by the address signal generation circuit 24, the initial value data F of the register 5TRT, which is switched and derived from the multiplexer 27, and the address data from the address signal generation circuit 24 match.
The output of the match determination circuit 26 becomes high level.

Waveform data D output from the ROM 28 in this way
A to Dc are subjected to data conversion by a data conversion circuit 130. That is, from the decoder 29, the register CN
The data of the 3rd bit to the Oth bit of T12 is derived,
Based on this, the data is converted as described above. The conversion mode in the data conversion circuit 30 is shown in Table 7.

That is, for example - as an example, at angle θa1,
Since the value stored in the register CNT12 is "0", the waveform data Da to Dc are directly converted to the waveform data Ea to E.
Output as c. The waveform data Ea to Ec are data obtained by inverting the waveform data Ea to Ec, respectively. Also, at angle θa2, the value of register CNT12 is “1”.
'', waveform data Dc is output as waveform data Ea, waveform data Db is output as waveform data Eb, and waveform data Da is output as waveform data Ec.

In this way, at each angle θa1 to θa12, as shown in Table 7, the data conversion circuit 30 converts the waveform data Da
~Dc and waveform data Da~DC are converted into waveform data Ea~E in different ways based on data from the decoder 29.
c and waveform data Ea to Ec.

In this way, the data conversion circuit 30 converts 30 degrees worth of waveform data Da~Dc into one period worth of waveform data Ea~
Ec and Ea to Ec are created by data conversion.

Therefore, each coil 42a to 42c of the compressor 42 operated based on the waveform data E a -E c has a sine wave 11 a constituting the three-phase alternating current shown in FIG.
A voltage drop close to ~11C occurs.

In FIG. 7, sine waves 1'la to 11C individually correspond to waveform data Ea to Ec.

That is, by storing at least three types of waveform data Da to Dc as shown in Table 4 in the ROM 28, it is possible to easily demodulate the three-phase AC waveform necessary for driving the motor. Also, waveform data D from ROM28
By varying the sampling speed of a%Dc, it is possible to easily match the rotational speed required of the motor.

(b) The 6th to 4th bits of register C0NT are r
o In the case of 10 J, the 6th to 4th bits of register C0NT are '010'
In the case of J, one cycle of output signal is generated from 60 degrees of waveform data. At this time, register CNT12
The count up number is set to ``+2'', and the counting operation is performed sequentially from ``0'' to rlo with the count up number ``+2'', thereby generating 60 degrees of waveform data Da to D.
c is read six times in one period over the angles θb1 to θb6 in FIG. Therefore, the numerical value of the register CNT12 is always an even number, and the Oth pit is rO'', so the multiplexer 27 first derives the initial value data F stored in the register 5TRT. As a result, the initial value of the address signal generation circuit 24 becomes the initial value data F stored in the register 5TRT. Further, the address signal generating circuit 24 functions as an up counter in response to a signal from the decoder 29, and specifies the address value while sequentially incrementing it. At this time, the multiplexer 27 is switched to derive the register END, and the match determination circuit 26 outputs the register END.
The address data from 4 and the initial value data F stored in the register END are compared. In this case, the address signal generating circuit 24 generates, for example, each angle θb1 to θb.
When the addresses for 32 time divisions of 6 are specified, the output of the match determination circuit 26 changes to, for example, a high level.

Waveform data D output from the ROM 28 in this way
A to Dc are subjected to data conversion by a data conversion circuit 30. That is, from the decoder 29, the register C
The data of the 3rd bit to the Oth bit of NT12 is derived, and based on this data, the data is converted as described above. The conversion mode in the data conversion circuit 30 is shown in Table 8.

Table 8: For example, for angle θb1:
Since the value stored in the register CNT12 is "O", the waveform data Da to Dc are directly converted to the waveform data Ea to E.
Output as c. The waveform data Ea to Ec are data obtained by inverting the waveform data Ea to Ec, respectively. Also, at angle θb2, the value of register CNT12 is "2"
Therefore, waveform data Db is output as waveform data Ea, waveform data Dc is output as waveform data Eb, and waveform data Da is output as waveform data Ec.

In this way, at each angle θb1 to θb6, the data conversion circuit 30 converts the waveform data Da to D as shown in Table 8.
c and waveform data Da to Dc are derived as waveform data Ea to Ec and waveform data Ea to Ec in different ways based on the data from the decoder 29.

In this way, the data conversion circuit 30 converts 60 degrees of waveform data Da to Dc into one cycle of waveform data Ea to
Ec and Ea to Ec are created by data conversion.

Therefore, each coil 42a-42c of the compressor 42 operated based on the waveform data Ea-Ec has sine waves 12a-12 constituting the three-phase alternating current shown in FIG.
A voltage drop close to c occurs.

In FIG. 8, the sine waves 12a to 12c individually correspond to the waveform data Ea to Ec.

(C) The 6th to 4th bits of register C0NT are r
In the case of loOJ, the 6th to 4th bits of register C0NT are rloO.
In the case of J, one period of output signal is generated from 120 degrees of waveform data. At this time, register CNT12
The count-up number is set to "+4", and the counting operation is performed sequentially from r
is read out three times in one period over the angles θc1 to θc3 in FIG. Therefore, since the numerical value of register CNT12 is always an even number and its Oth bit is "O", multiplexer 27 first derives initial value data F stored in register 5TRT. As a result, the initial value of the address signal generation circuit 24 becomes the initial value data F stored in the register 5TRT. Further, the address signal generating circuit 24 functions as an up counter by the signals from the decoder 29, and specifies the address value while sequentially incrementing it. At this time, the multiplexer 27 is switched to derive the register END, and the match determination circuit 26 outputs the register END.
The address data from and the initial value data F stored in the register END are compared. In this case, the address signal generation circuit 24 generates, for example, each angle θc1 to θc3.
When the addresses for 64 times of time-division are specified, the output of the match determination circuit 26 changes to, for example, a high level.

Waveform data D output from the ROM 28 in this way
A to Dc are subjected to data conversion by a data conversion circuit 30. That is, from the decoder 29, the register C
The data of the 3rd bit to the 0th bit of NT12 is derived, and based on this data, the data is converted as described above. Table 9 shows the conversion mode in the data change detection circuit 30.

Table 9: For example, for angle θC1:
Since the value stored in the register CNT12 is r
-E c is output. The waveform data Ea to Ec are data obtained by inverting the waveform data Ea to Ec, respectively.

Furthermore, at angle θC2, the value of register CNT12 is "4", so waveform data Dc is output as waveform data Ea, waveform data Da is output as waveform data Eb, and waveform data Db is output as waveform data Ec. Ru.

In this way, at each angle θC1 to θC3, the data conversion circuit 30 converts the waveform data Da to θC3 as shown in Table 9.
Dc and waveform data Da to Dc are converted into waveform data Ea to Ec in different ways based on data from the decoder 29.
and waveform data Ea to Ec.

In this way, the data conversion circuit 30 converts the waveform data Ea for one cycle from the waveform data Da to Da for 120 degrees.
~Ec and Ea~Ec are created by data conversion.

Therefore, each coil 42a-42c of the compressor 42 operated based on the waveform data Ea-Ec has sine waves Z3a-13 constituting the three-phase alternating current shown in FIG.
A voltage drop close to c occurs.

In FIG. 9, the sine waves f3a to 13c individually correspond to the waveform data Ea to Ec. 9(d) When the fourth bit of the register C0NT is "1" (the waveform data for 90 degrees is (When the fourth bit of the register C0NT is "1", one period of output signal is generated from the waveform data for an arbitrary angle. Hereinafter, a case where one period of output signal is generated from 90 degrees worth of waveform data will be explained with reference to FIG. 10. At this time, numerical values as shown in Table 10 are set in the register CNT12 at each of the angles θd1 to θd4. When the value of this register CNT12 is an even number, that is, the Oth bit is r□, the multiplexer 27 first derives the initial value data F stored in the register 5TRT. As a result, the initial value of the address signal generation circuit 24 becomes the initial value data F stored in the register 5TRT. Further, the address signal generating circuit 24 functions as an up counter in response to a signal from the decoder 29, and specifies the address value while sequentially incrementing it. At this time, the multiplexer 27 is connected to the register EN.
D is switched to derive the initial value data F of D, and the match determination circuit 26 uses the address data from the address signal generation circuit 24 and the initial value data F stored in the register END.
Compare with. In this case, C= is address signal generation circuit 2
4 for a predetermined number of times (for example, each angle θd1 to θd4
When the address is specified 48 times (by time-division), the output of the match determination circuit 26 changes to, for example, a high level.

Further, when the O-th bit of the register CNT12 is "1", the multiplexer 27 first derives the initial value data F stored in the register END to the address signal generation circuit 24. In this case, the address signal generation circuit 24 functions as a down counter by the control signal from the decoder 29.

When the address is specified 48 times by the address signal generation circuit 24, the initial value data F of the register 5TRT which is switched and derived from the multiplexer 27 and the address data from the address signal generation circuit 24 match.
The output of the match determination circuit 26 becomes high level.

Waveform data D output from the ROM 28 in this way
A to Dc are subjected to data conversion by a data conversion circuit 30. That is, from the decoder 29, the register CN
The data of the third bit to the Oth bit of T12 is derived,
Based on this, the data is converted as described above. The conversion mode in the data conversion circuit 30 is shown in Table 10.

Table lO, for example - As an example, at angle θdl,
Since the value stored in the register CNT12 is rOJ, the waveform data Da~Dc are directly converted into the waveform data Ea~
It is output as Ec. The waveform data Ea to Ec are data obtained by inverting the waveform data Ea to Ec, respectively. At angle θd2, the value of register CNT12 is "5", so waveform data Da is output as waveform data Ea, waveform data Dc is output as waveform data Eb, and waveform data Db is output as waveform data Ec. .

In this way, at each angle θd1 to θd4, as shown in Table 10, the data conversion circuit 30 converts the waveform data Da to
Dc and waveform data Da to Dc are converted into waveform data Ea to Ec in different ways based on data from the decoder 29.
and waveform data Ea to Ec.

In this way, the data conversion circuit 30 converts 90 degrees of waveform data Da to Dc into one cycle of waveform data Ea to Dc.
Ec and Ea to Ec are created by data conversion.

Therefore, each coil 42a to 42c of the compressor 42 operated based on the waveform data Ea to Ec has sine waves 14a to 14a constituting the three-phase alternating current shown in FIG.
A voltage drop close to 4c occurs. In addition, in Figure 10,
The sine waves 14a-14C individually correspond to the waveform data Ea-Ec.

(e> If the 4th bit of register C0NT is “1” (1
(When 80 degrees worth of waveform data is stored in the ROM 28) When the fourth bit of register C0NT is 11'' and one period of output signal is generated from 180 degrees worth of waveform data, see Figure 11. and explain. At this time, numerical values as shown in Table 11 are set in the register CNT12 at each angle θel and θe2. The value of this register CNT12 is always an even number, and the Oth bit is "
0'', multiplexer 27 first selects register 5.
Initial value data F stored in TRT is derived.

As a result, the initial value of the address signal generation circuit 24 becomes the initial value data F stored in the register 5TRT. Further, the address signal generating circuit 24 functions as an up counter in response to a signal from the decoder 29, and specifies the address value while sequentially incrementing it. At this time, the multiplexer 27 outputs the initial value data F of the register END.
The match determining circuit 26 compares the address data from the address signal generating circuit 24 with the initial value data F stored in the register END. In this case, the address signal generation circuit 24 performs a predetermined number of times (for example, 96 times by time-division of each angle θel, θe2).
When an address is specified, the output of the match determination circuit 26 changes to, for example, a high level.

Waveform data D output from the ROM 28 in this way
A to DC are subjected to data conversion by a data conversion circuit 30. In other words, from the two decoders, register CN
The data of the 3rd bit to the Oth bit of T12 is derived,
Based on this, the data is converted as described above. The conversion mode in the data conversion circuit 30 is shown in Table 11.

(Margins below) In Table 11, that is, for the angle θe1, the value stored in the register CNT12 is r□, so the waveform data D a
% D c is output as is as waveform data Ea to Ec. Waveform data Ea to EC are waveform data E a %
This is data obtained by inverting Ec. Also the angle θ
In e2, the value of the register CNT12 is "6", so the waveform data Da is output as the waveform data Ea, the waveform data Db is output as the waveform data Eb,
Waveform data DC is output as waveform data Ec.

In this way, in each period θel, θe2, the data conversion circuit 30 converts the waveform turns Da to
Dc and waveform data Da to Dc are converted into waveform data Ea to Ec in different ways based on data from the decoder 29.
and waveform data Ea to Ec.

In this way, the data conversion circuit 30 converts one period of waveform data Ea from 180 degrees of waveform data Da to Dc.
~Ec and Ea~Ec are created by data conversion.

Therefore, each coil 42a to 42c of the compressor 42 operated based on the waveform data Ea to Ec has a sine wave f5a which transmits the three-phase alternating current shown in FIG.
A voltage drop close to ~1'5c occurs. In FIG. 11, the sine waves 15a to 15C individually correspond to the waveform data Ea to Ec.

■Delay operation Waveform data Ea to Ec, Ea converted as described above
~Ec is the desired delay time d set by the rise delay circuit 31
Its rise is delayed. The reason why such an output signal requires a delay is due to the power transistor Tr mentioned above.
Since the turn-off times of transistors Tr1 to Tr6 are slow, for example, when mutually inverted signals are applied to the bases of transistors Tr1 and Tr2, both transistors Tri and Tr2 temporarily become conductive. As a result, an excessive current may flow through the transistors Tri and Tr2. In order to prevent such a situation, the rise delay circuit 31 delays the rise of the waveform data Ea to Ec and Ea to Ec.

That is, as shown in FIG. 12 (1), the waveform data D
When a (waveform data Da in Table 3) is output to the data conversion circuit 30, the value of the register CNT12 is "O".
In this case, the data conversion circuit 31 outputs the data as shown in FIG.
2) and waveform data as shown in FIG. 12 (3),
Ea and waveform data Ea are respectively output.

The rising edge of the waveform data Ea and waveform data Ea is delayed by a delay time d in a rising edge delay circuit 31. The output signal Fa and the output signal Fa from the rise delay circuit 31 are as shown in FIG. 12 (4) and FIG. 12 (5>), respectively.

Note that the output signals Fa to Fc, F from the rise delay circuit 31
a to Fc are output by the output circuit 32 at 20. Output with mA sink current. Therefore, inverted signals are output from the output terminals T1 to T6.

The signals Pa and Pa output from the output terminals TI and T2 are as shown in FIG. 12 (6> and FIG. 12 (7), respectively. The signals Pa and Pa are inverted via the phototrapper 40 and controlled. Therefore, the control signal R1°R1 corresponds to the output signals Fa and Fa shown in FIG. 12 (4) and FIG. 12 (5), respectively, and the simultaneous conduction of transistors Tri and Tr2 be spared.

In the signal generation circuit 21, the third
The bits to the Oth bit are provided for setting the delay time d. The relationship between the delay time d and the values of the third to zeroth bits of the register C0NT is as shown in Table 12.

As described above, in this embodiment, the desired delay time d is determined depending on the types of power transistors Trl to Tr6 used.
can be given selectively.

The signal Pa output from the terminals T1 to T6 in this way
~Pc, Pa~Pc are applied to the power transistors Tri to Tr6 via the photocoupler 4o, thereby controlling the applied voltage applied to the compressor 42 and controlling the rotation in the compressor 42.

In this manner, in this embodiment, the conversion of address designation data is performed by hardware based on the initial value data F stored in each register.

Therefore, there is no need to create a program for such address designation and data conversion, and the burden of program creation is significantly reduced.

Moreover, since the command cycle time of the CPU 34 does not depend on the length of the subroutine of the program and the waveform does not change, highly accurate signals can be output. Therefore, it is also possible to perform signal processing such as finely setting the delay time d to an optimal value.

Furthermore, the line selection switch allows the memory CPU to
The data transfer between the memory waveform generation circuit and the memory waveform generation circuit is configured to switch according to the timing of reading the data to be transferred, solving the problem of data bus occupancy.
The waveform data and operating program can be stored in the same memory. Therefore, the amount of space occupied by piggybacking during the development stage of the signal generation circuit can be reduced, and as a result, the burden of creating programs and data can be significantly reduced.

Although this embodiment is described in relation to a configuration for driving a motor, this is not a limitation.

Effects of the Invention As described above, according to the present invention, the waveform data on the memory is read from the address specified by the addressing means without involving the central processing circuit. No program required. Furthermore, since the read waveform data is subjected to signal processing by the signal processing means, there is no need for a program related to such signal processing, and furthermore, the addressing means and the signal processing means are provided independently of the central processing circuit. Since this method can be executed at high speed, it is possible to output a signal having a highly accurate pulse waveform. Furthermore, since the switching means switches between reading the waveform data to the signal processing means and reading the operating program to the central processing circuit, the waveform data and the operating program can be stored in the same memory.

Therefore, the burden of creating programs and adjusting waveform data etc. from the development stage can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a simplified configuration of a signal generating circuit 21 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration when the operating state of a compressor 42 is controlled by the signal generating circuit 21. , Figure 3 shows the signal generation port N12.
1 is a block diagram showing the specific configuration of 1, FIG. 4 is a flowchart for explaining the operation of the signal generation circuit 21, and FIG. 5 is a waveform diagram showing three-phase AC and triangular waveforms used to create waveform data. , FIG. 6 is a waveform diagram showing an enlarged view of the time 81 portion in FIG. AC waveform diagram. Figure 8 is a three-phase AC waveform diagram to explain the signal conversion operation that generates one cycle of signals from 60 degrees of waveform data. Figure 9 is 120 degrees of waveform data. Figure 10 is a three-phase AC waveform diagram to explain the conversion operation of a signal that generates a signal for one period from 90 degree waveform data. Figure 11 is a waveform diagram of three-phase AC to explain the signal conversion operation that generates one cycle of signals from 180 degrees of waveform data, and Figure 12 is a waveform diagram of three-phase AC to A waveform diagram for explaining the delay operation in the delay circuit 31, FIG. 13 is the signal generation circuit 1 of the prior art.
FIG. 14 is a block diagram showing a simplified configuration of the signal generation circuit 15 considered to solve the problem of the prior art, and FIG.
FIG. 2 is a perspective view showing the configuration of a piggyback 51 used for creating a program in a PROM. 21... Signal generation circuit, 23... Up counter,
24... Address signal generation circuit, 26... Match determination circuit, 27... Multiplexer, 28... Read only memory (ROM), 29... Decoder, 30...
Data conversion circuit, 31...Rise delay circuit, 32...
・Output circuit, 34...Central processing circuit (CPLI), 3
5... Address designation means, 36... Signal processing means,
40... Photocoupler, 41... Power supply, 42... Compressor, 47a to 47c... Line selection switch, C0NT.

Claims (1)

[Scope of Claims] A central processing circuit that processes signals based on an operation program; and 1, which is connected to the central processing circuit via a data bus and stores initial value data that serves as a reference for output signals.
one or more registers, a memory in which waveform data related to the operating program and the signal to be output are stored, and an address of the waveform data stored in the memory is specified based on initial value data stored in the register; addressing means; signal processing means for responding to the waveform data from the memory, performing signal processing on the waveform data based on initial value data stored in the register, and outputting the signal to the outside; Corresponding to the reading of the operating program from the memory to the central processing circuit and the reading of waveform data from the memory to the signal processing means, a data bus between the central processing circuit and the memory and a connection between the signal processing means and the memory are provided. and switching means for switching data buses between the two.