JPH03255545A - Error reset control circuit - Google Patents

Abstract

PURPOSE:To efficiently realize a fault analysis by executing an error reset based on an error reset signal and a condition setting signal. CONSTITUTION:This control circuit is constituted of an error resetting instruction receiving circuit 1 for outputting an error reset signal 11 based on an error reset instruction 10 from a host device, a condition setting circuit 2 for setting a condition at the time when an error reset is effective based on a condition setting signal 13 and outputting an effective condition signal 14, an error reset executing circuit 3 for outputting an error reset executing signal 12 based on the error reset signal 11 and the condition setting signal 14, and an error and auxiliary information holding circuit 4 for resetting an error and auxiliary information held until that time, in the case the error reset executing signal 12 is supplied. In such a manner, setting for a detailed fault analysis can be executed efficiently on a case-by-case basis without executing a complicated work.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error reset control circuit, special G4, and an error reset control circuit for a main memory device.

[Conventional technology]

In the main memory, there is a circuit that holds the details of errors detected in the main memory and auxiliary information such as addresses and commands at that time.
An error reset command is input from the host device, and the error contents etc. are reset.

When a conventional error reset control circuit receives an error reset command from a host device, it directly outputs an error reset signal to an error and auxiliary information holding circuit to reset the contents.

The main storage device constitutes the entire system together with a plurality of information processing devices, and is operated by a complex intertwining of hardware, firmware, and software.

Furthermore, as the scale of the system increases, the number of people involved in various designs increases, and the roles become more divided, making it difficult to see each other's operations.

If an error is detected in main storage in this situation,
For example, errors are collected using the following steps:

When the main storage device detects an error, it reports the error to the host device.

In response to this, the host device reads the error and auxiliary information in the main memory, stores the information in a storage location such as a floppy, and then outputs an error reset command to the main memory 7 to clear the error in the main memory. Reset information.

[Problem to be solved by the invention]

In the conventional error reset control circuit described above, failure analysis is performed from the collected information, but since the error collection work involves hardware, software, and firmware other than the main memory, it is difficult to verify the correctness of the corrected error. If you suspect that something is wrong or want to view the error details by adding various conditions, it is not easy to do, so even if you try to perform simple failure analysis, it will take a lot of people in charge of hardware, software, and firmware to do the work. This method has the disadvantage of being inefficient because it requires multiple steps.

[Means to solve the problem]

The error reset control circuit of the present invention includes: (^) an error reset command receiving circuit that outputs an error reset signal based on an error reset command from a host device; (B) an error reset command receiving circuit that outputs an error reset signal based on a condition setting signal; a condition setting circuit that sets conditions and outputs a valid condition signal; (C) an error reset execution circuit that outputs an error reset execution signal based on the error reset signal and the condition setting signal; (D) the error reset If execution signal is supplied 1
．． The error and auxiliary information holding circuit resets the error and auxiliary information held up to that point.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The error reset control circuit shown in FIG. 1 includes: (^) an error reset command receiving circuit 1 which outputs an error reset signal 11 based on an error reset command 1o from a host device; (B) a condition setting signal 13; (C) A condition setting circuit 2 that sets conditions when error reset is valid and outputs a valid condition signal 14; (C) an error reset that outputs an error reset execution signal 12 based on the error reset signal 11 and condition setting signal 14; (D) An error and auxiliary information holding circuit 4 that resets the error and auxiliary information held until then when the error reset execution signal 12 is supplied.

Next, the operation will be explained.

If no valid condition for error reset is set in the condition setting circuit 2 using the condition setting signal 13, when an error reset command 10 is sent from the host device, the error reset command receiving circuit 1 sends an error reset signal. 11, the error reset execution circuit 3 receives it, outputs an error reset execution signal 12, and resets the contents of the error and auxiliary information holding circuit 4.

In other words, if the conditions are not set, when the error reset command 10 is received from the host device, the error and auxiliary information contents will be reset unconditionally.

When various enabling conditions for error reset are set in the condition setting circuit 2 using the condition setting signal 13, for example, the error reset command is suppressed, the error reset command is enabled from which time, or the next error reset command after a certain operation is set. , or when an error reset command 10 is sent from the host device, the error reset command receiving circuit 1 outputs the error reset signal 11, and the error reset execution circuit 3 outputs the error reset signal 11 and the valid condition signal 14. is received and the error reset execution signal 12 is output only when the error reset validity condition is satisfied, and the contents of the error and auxiliary information holding circuit 4 are reset.

In this way, even if an error reset command is received from a host device, if the valid conditions for the error reset command can be set in the error reset control circuit in the main memory, the error will not be detected in the main memory. Errors are collected by the system as a system, and even if an error reset command is finally issued, the error reset is not effective, or it is enabled conditionally, and the errors are left in the main memory. Even if the firmware is complicated, it is possible to efficiently set up detailed failure analysis on a case-by-case basis without involving many people or doing complicated work.

〔Effect of the invention〕

The error reset control circuit of the present invention has the advantage that failure analysis can be carried out efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Error reset command receiving circuit, 2...
. . . Condition setting circuit, 3 . . . Error reset execution circuit, 4 . . . Error and auxiliary information holding circuit.

Claims (1)

[Claims] (A) An error reset command receiving circuit that outputs an error reset signal based on an error reset command from a host device; (B) Setting conditions when error reset is valid based on a condition setting signal. (C) an error reset execution circuit that outputs an error reset execution signal based on the error reset signal and the condition setting signal; (D) the error reset execution signal is If supplied,
An error reset control circuit comprising: an error and auxiliary information holding circuit that resets error and auxiliary information held until then;