JPH03255698A - Printed wiring board and manufacture thereof - Google Patents
Printed wiring board and manufacture thereofInfo
- Publication number
- JPH03255698A JPH03255698A JP5413090A JP5413090A JPH03255698A JP H03255698 A JPH03255698 A JP H03255698A JP 5413090 A JP5413090 A JP 5413090A JP 5413090 A JP5413090 A JP 5413090A JP H03255698 A JPH03255698 A JP H03255698A
- Authority
- JP
- Japan
- Prior art keywords
- ferrite
- layer
- circuit
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 7
- 238000007650 screen-printing Methods 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 239000007787 solid Substances 0.000 abstract description 2
- 239000000843 powder Substances 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板とその製造方法に関し、特に電
磁波を吸収することが可能なプリント配線板とその製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board and a manufacturing method thereof, and more particularly to a printed wiring board capable of absorbing electromagnetic waves and a manufacturing method thereof.
近年、電子機器より放出される電磁波(ノイズ)に対す
る規制が強化されてきている。In recent years, regulations regarding electromagnetic waves (noise) emitted from electronic devices have been tightened.
この電磁波放出をおさえるために、第3図(a)〜(d
)に示したように、プリント配線板の表面の回路2上に
銅ベーストなどの導電性樹脂により導電層6を形成した
プリント配線板がある。In order to suppress this electromagnetic wave emission, Fig. 3(a) to (d)
), there is a printed wiring board in which a conductive layer 6 is formed of a conductive resin such as a copper base on a circuit 2 on the surface of the printed wiring board.
上述した従来のプリント配線板は、第3図(a)〜(d
)のように、回路2上に導電層6を形成するので、回路
2と導電層6を絶縁するための絶縁層5が必要となる。The conventional printed wiring board described above is shown in FIGS. 3(a) to (d).
), since the conductive layer 6 is formed on the circuit 2, the insulating layer 5 is required to insulate the circuit 2 and the conductive layer 6.
この絶縁層5は、絶縁樹脂をスクリーン印刷することで
形成されるが、ピンホールを防ぐため、2〜3回のスク
リーン印刷が必要となる欠点がある。This insulating layer 5 is formed by screen printing an insulating resin, but has the disadvantage that screen printing is required two to three times to prevent pinholes.
又、導電層6やその上に形成する保護層7もスクリーン
印刷により形成される。よって、計4〜5回のスクリー
ン印刷工程が必要となり、これが従来技術によるプリン
ト配線板のコスト上昇の一因となっている欠点がある。Further, the conductive layer 6 and the protective layer 7 formed thereon are also formed by screen printing. Therefore, a total of 4 to 5 screen printing steps are required, which is a disadvantage of causing an increase in the cost of printed wiring boards according to the prior art.
本発明の目的は、スクリーン印刷回数が少く、安価なプ
リント配線板とその製造方法を提供することにある。An object of the present invention is to provide a printed wiring board that requires less screen printing and is inexpensive, and a method for manufacturing the same.
本発明のプリント配線板は、導体により回路形成された
絶縁基板上の所定部分にフェライト層を有している。The printed wiring board of the present invention has a ferrite layer at a predetermined portion on an insulating substrate having a circuit formed of conductors.
本発明のプリント配線板の製造方法は、導体により回路
形成された絶縁基板上の所定部分に回路上を覆うように
フェライト層を形成する工程を含んで構成されている。The method for manufacturing a printed wiring board of the present invention includes the step of forming a ferrite layer on a predetermined portion of an insulating substrate on which a circuit is formed using a conductor so as to cover the circuit.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)、(b)は本発明の第1の実施例の製造方
法を説明する工程順に示した断面図である。FIGS. 1(a) and 1(b) are sectional views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.
第1の実施例は、第1図(a>のように、回路2が形成
されている絶縁基板1に、第1図(b)のようにフェラ
イト層3をスルホール、パッドなど部品搭載部分を逃げ
て形成する。In the first embodiment, as shown in FIG. 1(a), a ferrite layer 3 is formed on an insulating substrate 1 on which a circuit 2 is formed, and component mounting parts such as through holes and pads are formed as shown in FIG. 1(b). Escape and form.
このフェライト層3の形成方法は、例えば、固形フェラ
イトを粉砕し、これをエポキシ樹脂を主成分とする熱効
果樹脂と混合しインク状にしたものをスクリーン印刷す
る方法などがある。使用するフェライトの成分、又、フ
ェライト層3の厚みは、吸収させないノイズの周波数に
より決定すればよい。The ferrite layer 3 can be formed by, for example, pulverizing solid ferrite, mixing it with a heat-effect resin mainly composed of epoxy resin, making an ink, and screen-printing the ink. The components of the ferrite used and the thickness of the ferrite layer 3 may be determined depending on the frequency of the noise that is not absorbed.
第2図(a)〜(c)は本発明の第2の実施例の製造方
法を説明する工程順に示した断面図である。FIGS. 2(a) to 2(c) are cross-sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps.
第2の実施例は、第2図(a>のように、回路2が形成
されている絶縁基板1に、第2図(b)のように、ソル
ダーマスク4を、例えば、写真現像方法により露光・現
像・硬化を行なって形成し、第2図(C)のように、ソ
ルダーマスク4上にフェライト層3を、例えば、第1の
実施例に説明したフェライトインクをスクリーン印刷す
ることにより形成する。In the second embodiment, as shown in FIG. 2(a), a solder mask 4 is applied to an insulating substrate 1 on which a circuit 2 is formed, as shown in FIG. The ferrite layer 3 is formed by exposing, developing and curing, and as shown in FIG. 2(C), the ferrite layer 3 is formed on the solder mask 4 by, for example, screen printing the ferrite ink described in the first embodiment. do.
フェライト層3の下部にソルダーマスク4を形成するこ
とにより、部品実装時のはんだブリッジを低減すること
ができる。By forming the solder mask 4 under the ferrite layer 3, solder bridging during component mounting can be reduced.
以上説明したように本発明では、導電層、絶縁層、保護
層のスクリーン印刷が不要で、単に、フェライト層を印
刷するだけでよいため、スクリーン印刷回数を大幅に低
減でき、電磁波ノイズの放射を抑えることができるプリ
ント配線板が安価に製造できる効果がある。As explained above, in the present invention, there is no need to screen print the conductive layer, insulating layer, and protective layer, and it is sufficient to simply print the ferrite layer, so the number of screen prints can be significantly reduced, and the radiation of electromagnetic noise can be reduced. This has the effect of making it possible to manufacture printed wiring boards at low cost.
第1図(a)、(b)は本発明の第1の実施例の製造方
法を説明する工程順に示した断面図、第2図(a)〜(
C)は本発明の第2の実施例の製造方法を説明する工程
順に示した断面図、第3図(a)〜(d)は従来の製造
方法の一例を説明する工程順に示した断面図である。
1・・・絶縁基板、2・・・回路、3・・・フェライト
層、4・・・ソルダーマスク、5・・・絶縁層、6・・
・導電層、7・・・保護層。
(0)
(bン
第1霞FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps, and FIGS. 2(a)-(
C) is a cross-sectional view shown in the order of steps to explain the manufacturing method of the second embodiment of the present invention, and FIGS. 3(a) to (d) are cross-sectional views shown in the order of steps to explain an example of the conventional manufacturing method. It is. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Circuit, 3... Ferrite layer, 4... Solder mask, 5... Insulating layer, 6...
- Conductive layer, 7... protective layer. (0) (bn first haze
Claims (2)
にフェライト層を有することを特徴とするプリント配線
板。(1) A printed wiring board characterized by having a ferrite layer at a predetermined portion on an insulating substrate on which a circuit is formed using a conductor.
に回路上を覆うようにフェライト層を形成する工程を含
むことを特徴とするプリント配線板の製造方法。(2) A method for manufacturing a printed wiring board, comprising the step of forming a ferrite layer on a predetermined portion of an insulating substrate on which a circuit is formed using a conductor so as to cover the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5413090A JPH03255698A (en) | 1990-03-05 | 1990-03-05 | Printed wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5413090A JPH03255698A (en) | 1990-03-05 | 1990-03-05 | Printed wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03255698A true JPH03255698A (en) | 1991-11-14 |
Family
ID=12962007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5413090A Pending JPH03255698A (en) | 1990-03-05 | 1990-03-05 | Printed wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03255698A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2192824A1 (en) * | 2008-11-27 | 2010-06-02 | Siemens Aktiengesellschaft | Printed circuit board with an electromagnetic wave shield layer |
| JP2014030067A (en) * | 2013-11-15 | 2014-02-13 | Shin Etsu Polymer Co Ltd | Printed wiring board and optical module |
-
1990
- 1990-03-05 JP JP5413090A patent/JPH03255698A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2192824A1 (en) * | 2008-11-27 | 2010-06-02 | Siemens Aktiengesellschaft | Printed circuit board with an electromagnetic wave shield layer |
| JP2014030067A (en) * | 2013-11-15 | 2014-02-13 | Shin Etsu Polymer Co Ltd | Printed wiring board and optical module |
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