JPH03256149A - Failure information storage device - Google Patents

Abstract

PURPOSE:To decide whether failure information is miswritten or not with high probability by converting the failure information into contents corresponding to respective addresses of the 1st and 2nd storage means and respectively writing the converted contents in the storage areas of the corresponding addresses. CONSTITUTION:At the time of detecting the generation of a failure, a failure detecting means 2 outputs the failure information to a writing means 5, which changes the failure information into the contents corresponding to respective addresses of the 1st and 2nd storage means 3, 4 and writes the changed contents in the storage areas 3a, 4a of respective corresponding addresses. A reading means 6 reads out the contents stored in the areas 3a, 3b having the addresses mutually related to the means 3, 4 and outputs the read contents to a deciding means 7. The means 7 decides whether the two contents of the failure information correspond to respective addresses of the areas 3a, 3b or not. When the means 7 decides that one of the two read failure information corresponds to the address of the area 3a and the other does not correspond to the address of the area 4a, a correcting means 8 corrects the storage contents not corresponding to the address based upon the storage contents of the corresponding storage area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a failure information storage device for storing failure information when a failure occurs in equipment such as a vehicle.

[Prior Art] Generally, in a vehicle equipped with a microcomputer (hereinafter referred to as microcomputer), when a failure occurs in the engine or other parts, the failure location (failure details) is memorized and the failure location is repaired. When repairing, the location of the failure is determined from the memory contents, and appropriate repairs are made based on this information. Therefore, the stored contents must be accurate, and it is important to prevent erroneous information from being output.

However, microcomputers installed in vehicles can be accidentally disconnected due to instantaneous disconnection of the microcomputer (hereinafter referred to as "instantaneous disconnection") caused by disconnection of the ignition key or loosening of the connection between the power supply and the microcomputer due to vibrations during driving. The contents may be stored.

Therefore, the inventor of this application stored the same failure information in three areas of a storage device, and compared the three stored contents to determine whether the stored contents were correct. That is, if the storage contents of the three storage areas are respectively A, B, and C, and A, B, and C are stored in the order, the following four cases are assumed when the storage contents are compared.

A=B=C...(1) A=B≠C...(2> A≠B=C...(3) A#B≠C... ...(4) In the case of formula (1), memory contents A, B, and C are all correct; in the case of formula (2), memory content C was written incorrectly due to the effect of a momentary interruption. (hereinafter referred to as erroneous writing), and in the case of formula (3), where stored contents A and B are correct, stored contents A was written incorrectly due to the influence of a momentary interruption, and stored contents B.

In the case of formula (4) in which C is correct, it is determined that memory content B was written in error and memory content A is correct.

[Problems to be Solved by the Invention] However, when making the determination as described above, there have been cases where incorrect stored content is incorrectly determined to be correct.

In other words, in the conventional storage method described above, since failure information is simply written to three storage areas of the storage device, it is not possible to determine whether the content written to each storage area is correct or not. . For this reason, equation (1)
Although the probability of misjudgment is low in the case of , Equation (2) and Equation (
In the case of equation (3) and equation (4), incorrect memory contents may be mistakenly determined to be correct. In particular, in the case of equation (4), the probability that all of the memory contents A, B, and C were written incorrectly was extremely high (and the probability that the content of the failure was incorrectly determined was also high).

In addition, since erroneous writing due to instantaneous interruptions occurs over time,
Although equation (1) was initially established, equation (2),
(3) or equation (4) may be obtained.

Here, in equations (2) and (3), the probability that both of the same memory contents have been written by mistake is calculated by the equation (
This is lower than the probability that the stored content A was written in error in 4). Therefore, when formulas (2) and (3') hold true, if the different memory contents are corrected into two equal memory contents so that formula (1) holds true, then the formula ( 4) can be prevented, thereby lowering the probability that erroneous memory contents will be judged as correct. However, in the conventional storage method described above, no correction is performed at all, resulting in a high probability of misjudgment.

This invention was made in consideration of the above circumstances, and it is possible to determine with a high probability whether or not the memory contents have been written in error, thereby preventing erroneously determining the location of the failure. An object of the present invention is to provide a failure information storage device capable of correcting erroneously written memory contents. ), (B), and (C), information indicating the status of each part of equipment 1 is input from various sensors (not shown) installed in each part of equipment 1, and each part is controlled based on the input information. A first storage means 3 having a plurality of storage areas 3a, . . . each having a plurality of storage areas 3a, . storage area 4 a
+ . . . and a storage area 3a of the corresponding address by making the failure information from the failure detection means 2 correspond to the address of the first storage means 3.
At the same time, the same failure information is written to the second storage means 4.
The writing means 5 writes the content corresponding to the address in the storage area 4a of the corresponding address, and the failure information written in the storage areas 3a and 4a of the mutually related addresses of the first and second storage means 3 and 4 is written in the storage area 4a of the corresponding address. A reading means 6 for reading each, and a storage area 3 in which each failure information read by the reading means 6 is written.
The determination means 7 determines whether or not the address corresponds to the address a, 4a, and the failure information read from either the first storage means 3 or the second storage means 4 corresponds to the address, and the failure information is determined from the other. When the determination means 7 determines that the read failure information does not correspond to an address, the failure information read from one side is associated with the address of the storage area 3a (4a) from which the failure information was read. The correction means 8 writes the contents corresponding to the address of the other storage area 4a (3a) to which the address is attached to the other storage area 4a (3a).

[Operation] The failure detection means 2 detects whether or not a failure has occurred in each part of the equipment 1 based on human power information from various sensors installed in each part of the equipment 1. When detecting that a failure has occurred, the failure detection means 2 outputs failure information to the writing means 5. The writing means 5 changes the failure information to contents corresponding to either of the addresses of the first and second storage means 3, 4, and writes the contents into the storage areas 3a, 4a of the corresponding addresses, respectively. In this case, which failure information is written to which address is determined in advance. For example, let the failure information output from the failure detection means 2 be A, , A, .
Letting the addresses of the storage area 4a be L'M', . . . , the failure information A.

A3. . . are respectively changed to AL, A, . . . and written to the storage areas 3 a + 3 a + . . . to which addresses L, M, . Along with A L', A M',...
・The addresses L' and M' of the second storage means 4 are changed to
, . . . second storage areas 4a, 4a, ・
・Written in

The reading means 6 reads the storage areas 3a and 4 of the first storage means 3 and the second storage means 4 to which mutually related addresses are assigned.
The memory contents (failure information) of a are read and the read memory contents are output to the determining means 7.

The determining means 7 determines whether the two pieces of failure information correspond to the respective addresses of the storage areas 3a and 4a to which they are written. When the determining means 7 determines that one of the two read failure information corresponds to the address of the storage area 3a (4a) and the other does not correspond to the address of the storage area 4a (3a). The correcting means 8 corrects the storage contents of the storage area where the failure information and the address do not correspond based on the storage contents of the storage area where the address and the storage content correspond.

For example, the storage content of the storage area 3a to which the address S of the first storage means 3 is attached is X that does not correspond to the address, and the storage area 4a of the second storage means 4 to which the address S' related to the address S is attached. Assuming that the stored content of is failure information A8' corresponding to the address, the correction means 8 converts the stored content of the storage area 3a to which the address S of the first storage area 3 is attached to the address based on the failure information As'. Correct the corresponding failure information A8. Conversely, failure information A7 corresponding to the address is written in the storage area 3a of the first storage means 3 to which the address T is attached, and that address is written to the storage area 4a of the second storage means 4 to which the address T' is attached. If failure information Y that does not correspond to
The stored contents of the storage area 4a marked with ' are corrected to AT'.

Note that it is not necessary to associate one piece of fault information with one address, and instead change the contents of a plurality of pieces of fault information into one that corresponds to one address, and write it to the storage areas 3a and 4a of the corresponding address. You can do it like this. For example, the failure information A I+A may be collectively written as AL and written in the storage areas 3a and 4a assigned addresses L and L', respectively.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 2 to 9.

FIG. 2 shows a microcomputer 10 for controlling a vehicle for implementing the present invention, and the microcomputer 10 is equipped with a central processing unit (hereinafter referred to as CPU) 11 and a memory 12. Of course, the microcomputer IO has other configurations as well, but they are the same as well-known ones, so they are omitted.

Information is input to the CPU 1l from various sensors (not shown) installed in various parts of a vehicle (not shown) serving as equipment to be detected for failure.

Then, it is detected from the input information whether a failure has occurred in the failure detection target. In this example, there are 24 detection targets.
There are 24 types of failure information corresponding to each detection target in the CP.
It is output from the UII and written to the memory 12 as detailed below.

As shown in FIGS. 3 to 5, the memory 12 has 00
0. , (hereinafter, lower chamber H indicates hexadecimal number) to 7FF
, (2047 in decimal), an 8-bit EEP R having storage areas 12a, etc., with addresses up to (2047 in decimal)
OM(E 1 electrically E rasab
le and programmable ROM
) is used. In this case, the memory 12 is virtually partitioned into a main block (first storage means 03) and a sub-block (second storage means) 14, and the main block 13 is divided into a first, second and third main block 13A.
, 13B and 13C, sub-block 4 is virtually divided into first, second and third sub-blocks 14A and 14814C, respectively.

As will be described later, the main block 13 and sub-block 14 have storage areas 12a and 12a assigned mutually related addresses with the same failure information (the stored contents are different).

).

This corresponds to the storage areas 12a and 12 of the main block 13 and the sub-block 14, which are assigned mutually related addresses.
This is to correct one of the stored contents of a when it is determined that one of them has been erroneously written due to a momentary interruption or the like, based on the other.

The main and sub blocks 13 and 14 are each divided into three blocks for the following reason. That is, each storage area 12a of the memory 12 has 8 bits, and each bit represents one piece of failure information. However, there are 24 types of failure information to be stored. Therefore, the main block 13 is divided into the first, second and third main blocks 13A.
It is divided into 13813C, and eight types of failure information are stored in each section. This point is subblock 1
The same applies to 4.

Further, failure information is written in each block 13A to 14C as follows.

Currently, we have information on each of 24 types of failures.

...+Kt4, failure information 1-8 goes to the first main block 13A, failure information 9-KI8 goes to the second main block 13B, and failure information 17-! 4 is the third
Each is written to the main block 13C. First, to describe writing to the first main block 13A, as shown in FIG. is written by converting each digit of the storage area 12a from 1 to O. Further, depending on the plurality of pieces of failure information, the digit corresponding to each piece of failure information is converted from 1 to O.

For example, the storage contents of the storage area 12H are rewritten from (111111111) to (111111101) based on the failure information 2. In other words, is written to the memory information. In addition, the storage contents of the storage area 12a are rewritten to (111111001) by 3 in the storage information.

This rewriting is performed only on the storage area 12a at an address corresponding to the stored content, and the stored content and address are related according to the following fixed rules.

Now, if we invert (11111101), it becomes (000
00010). If we consider this as a binary number, 1
0B (hereinafter, the subscript B indicates a binary number), and 16
The base number is 2□ (hereinafter, the subscript H indicates a hexadecimal number). Then, storage area 1 with address 002H
(11111101) is written to 2a. Similarly,
If the failure information is 8, (10000000) is 08
0. is written to the storage area 12a assigned the address.

Also, if the failure occurs after the failure information is issued,
If the failure information corresponding to the failure is 3, the failure information is 2. The content represented by 3 is (1111
1001), and if you invert this, (0000011)
0). This is 110, and 6. It is.

Therefore, in the storage area 12a at address 006, (1
1111001) is written. Similarly, if 8 is issued as the fault information after , then (01111101) is written in the storage area at address 082. Further, when all 8's are issued in the failure information, (00000000) is written in the storage area 12a at address OFF□.

As is clear from the above content, the first main block 13A has addresses 0OOI (~OFF, hereinafter referred to as 100.~), and the addresses up to FF correspond to the second main blocks 13B, 200.~OFF. 2FF +1 The third main block 13C, 300, to 3FFH is the first subblock 14A, 400. to 4FF, and the second subblock 14B, 50'O, to 5FF is the third subblock. It is said to be 14C, and the address is 600□
The storage area 12a from 7FFn to 7FFn is an unused area.

In addition, the storage area 12a having the largest number of addresses among the storage areas 12a and 2H in which failure information has been written is where all failure information that has occurred in the past is written.

Therefore, when retrieving the memory contents of the first main block 13A, it is necessary to read the contents from address OFF□ to address 000.
．． If the information is read sequentially toward , all of the failure information that has occurred in the past can be obtained based on the storage contents of the storage area 12a from which the failure information was first read. This point applies to the second and third main blocks 1 described below.
The same applies to 3B and 13C.

Regarding writing to the second main block 13B, digits 9 to 18 correspond to the failure information sequentially from the nearest digit of the storage area 12a, and 9 to 111 correspond to the failure information in the same way as above. The number represented and the lower two of the three-digit address (100, ~IFF,) of the second main block.
Failure information is written to the storage area of the address that matches the number of digits.

The same applies to the third main block 13B.

Next, to explain the writing to the first sub-block 14A, the first sub-block 14A contains a binary number obtained by subtracting 1 from the binary number obtained by inverting the memory contents related to the failure information written in the first main block 13A. The binary number is written into the storage area 12a. in this case,
The address of the storage area 12a to be written has a certain relationship with the last two digits of the address of the storage area 12a of the first main block 13a. In other words, failure information that is the same in content (different in form as described above) is stored in the first main block 13A to which addresses have the same last two digits.
and each storage area 12a12H of the first sub-block 14A.
will be written to.

For example, as shown in FIG.
In the storage area 12a of address OO2 of A (1111
1101) is written, by reversing this and subtracting l, it becomes (00,000001).
is obtained. Then, this is written to the storage area 12a having the address 302, . . . of the first sub-block 14A.

Regarding the second and third sub-blocks 14B and 14C, the stored contents of the second and third main blocks are written in the same manner as described above.

Note that this embodiment uses EEFROM,
In that case, the steady state of each bit is 1, so 1
However, as long as the steady state is O, it may be converted from O to l. In this case, the storage contents of the main blocks 13A, 13B, and 13G may be regarded as binary numbers as they are, and these may be written into the storage area 12H at the corresponding address. Sub-block 14A.

For 14B and 14C, main blocks 13A to 1
It is sufficient to subtract 1 from the storage contents of 3C and write it to the corresponding storage area 12H.

Furthermore, among the storage areas 12a of the main block 13 and the sub-block 14, the storage area 12H in which all the failure information that occurred in the past is written is the storage area 12H of the main block 13 and the sub-block 14. If the failure information written in the area 12H corresponds to an address and the failure information written in the other storage area 12a does not correspond to the address, then the failure information written in the other storage area 12H where the address and the failure information do not correspond. The stored contents are corrected based on the stored contents of one storage area 12a to which the address and the failure information correspond.

For example, the address of the first main block 13A is 008
It is assumed that all the failure information that occurred in the past has been written in the storage area 12a which is 1 (.1). In FIG.
) and corresponds to the address. Address 0O8H
The storage contents of the storage area 12a to which the address 308□ of the sub-block 14A related to is (0000100
0) and does not correspond to the address. In this case, address 008. address 30 based on the memory contents of
8, so that the memory contents of address 308H correspond to (
00000111).

Of course, the second. Third main blocks 13B, 13C and second
．． The same applies to the third sub-blocks 14B and 14G. Further, if the failure information written in the n-th sub-blocks 14A, 14B, 14C corresponds to the address, and the failure information written in the n-th main block 13A, 13B, 13C does not correspond to the address, The storage contents written in the n-th main blocks 13A-13C are corrected based on the storage contents written in the n-th sub-blocks 14A-14C.

Writing and correction to the memory 12 as described above are performed according to a predetermined program.

Below, the sixth section regarding writing and correction to the memory 12 will be explained.
This will be explained based on the flowcharts shown in the figures and subsequent figures.

FIG. 6 shows the main routine of writing and correction processing. After the program starts, step 1
At 01, the memory clear switch (not shown) is turned on.
It is determined whether or not the state has been reached. The memory clear switch is for setting all the stored contents of the memory 12 to the initial state, and if the memory clear switch is in the ON state, that is, if the memory clear switch is turned on by the operator, in step 102 Memory clear is executed. This memory clear is done by EEPRO
A well-known memory clearing method for M is employed.

Furthermore, this is not the gist of the invention, so to briefly explain, the data is written in 16-byte units in a so-called page write mode. And memory clear is 96(-600,/16
) times, the entire memory 12 is cleared.

Note that it is necessary to turn on the memory clear switch until the entire memory 12 is cleared, but the time required is about 3 seconds.

If the memory clear switch has not been turned on, the memory 12 is searched in step 103.

As will be described in detail later, the memory search involves reading out the latest and correct failure information from the memory 12 and reading out the failure information from a RAM (random access memory) that can be processed by the CPU.
etc., and correction of failure information is performed.

When the memory search is completed, it is determined whether a failure has occurred at the present time (step 104).

If there is a current failure, a memory update is performed in step 105. As will be described later, memory updating is performed by adding the current failure to the past failures and writing it to the corresponding address when all the failures that have occurred in the past are different from the current failure.

When the memory clear in step 102 is completed,
If the determination in step 104 is negative, and if the memory update in step 105 is completed, the program ends.

The above memory search is executed based on the flowchart shown in FIG. As shown in this flowchart, first, in step 201, the address counter of the first main block 13A is initialized, and the value n of the address counter is initialized.
is set to 0FFH.

Next, the first main block 13A and the first sub-block 14A are read (step 202). As will be described in detail later, this reading is performed for the first main block 13A in the storage area 12a assigned the address indicated by the address counter, and for the first sub-block 14A, the first
This is performed for the storage area 12a assigned an address related to the address of the storage area 12a of the main block 13A. In this case, the value of the address counter is decremented by 1 when one storage area 12a of the first main block 13A and the second main block 14A is read. Therefore, reading is performed from address OFF to address 000. It will be carried out sequentially towards. Reading continues until valid fault information is first read from at least one of the first main block 13A and the first sub-block 14A.

Valid fault information is sent to the CPUI in step 203.
I is written (saved) as failure data in an available memory (a memory different from memory 12, of course).
. Here, failure data is used to distinguish it from failure information written in the memory 12 for convenience of explanation. Furthermore, as is clear from the order in which the failure information is read and the manner in which the failure information is written to the memory 12 described above, the failure data includes all the failure information that has occurred up to now, and is the latest.

Therefore, hereinafter, the failure data will be referred to as the latest failure data, and the failure information corresponding to this latest failure data will be referred to as the latest failure information.

Hereafter, address counter initialization (n-1F
F, ), the latest failure information of the second main block 13B and second sub-block 14B is read and saved (steps 204, 205, 206), and then the address counter is initialized (n=2 F F ,), Third
The latest failure information of the main block 13G and third sub-block 14C is read and saved (steps 207, 208, and 209).

The latest failure information is read based on the flowchart shown in FIG.

In step 301, failure information of the main block 13 is read. This reading is performed in the storage area 12.
This is performed every time a, and is performed for the storage area 12a assigned the same address as the value n of the address counter. In this case, in the case of reading in step 202, since the address counter has been initialized (n-〇FF,) in step 201, the first reading is performed at the address OFFO of the first main block 13A.
This is performed for the storage area 12a marked with .

In the following, only the first main block 13A and the first sub-block 14A will be explained, and the second. Third main blocks 13B, 13G and second
．． The description of the third sub-block will be omitted.

Next, in step 302, the first sub-block 13
The storage area 12a of the first sub-block 14A, which has an address related to the address of the storage area 12H from which B was read, is read. Of course, the first reading is performed on the storage area 12a assigned the address 3FF.

Next, it is determined whether the failure information read from the first main block 13A is valid (step 303).
. Whether or not the failure information is valid is determined by whether or not the failure information corresponds to the address of the storage area 12a from which it was read. For example, the address is 008. On the other hand, if the failure information written there is (11110111), the failure information is determined to be valid; otherwise, it is determined to be invalid.

If the failure information of the first main block L4A is not valid, it is determined in step 304 whether the failure information read from the first sub-block 14A is valid.

This determination is also made based on the correspondence between failure information and addresses.

If the failure information of the first sub-block 14A is not valid,
That is, if both the failure information of the main block 13A and the failure information of the first sub-block 1.4A are not valid, the address counter is updated in step 305. This update is performed by decrementing the value of the address counter by one. Then, in step 306, it is determined whether the value n of the address counter after being decremented by 1 is O.

If it is neo, the process returns to step 301, where the storage area 12H of the first main block 13A with the same address as the address counter value n is read, and the first sub-block with the associated address is read. Reading of the storage area 12a of 14A is performed. Thereafter, until an affirmative determination is made in step 303 or step 304, it is determined that either the fault information read from the main block 13A or the fault information read from the first sub-block 14A is valid. repeated until.

Note that if the value n of the address counter becomes O after repeated reading, that is, if the judgment in step 306 is affirmative, the first main block 13A and the first
Valid failure information is not written in any of the sub-blocks 14A and the first main block 13A.
and the first sub-block 14A are completed, and the second sub-block 14A is read.
reading main and sub-blocks 13B, 14B;
Reading of the third main and sub-blocks 13C and 14C is performed according to the flowchart shown in FIG.

If the determination in step 304 is affirmative, the contents stored in the storage area 12H of the first main block 13a are corrected based on the failure information read from the first sub-block 14A.

Of course, the storage area 12a where the correction is made is the storage area 1 of the first sub-block 14A from which valid failure information has been read.
This is the storage area 12a of the first main block 13A to which an address related to the address assigned to 2a is assigned. Then, valid failure information is obtained in step 2, as described above.
At 03, it is written to the memory as the latest failure data.

Note that the latest failure data is written to the memory for each main block or subblock from which it is read.

If the determination in step 303 is affirmative, that is, if the failure information read from the first main block 13A is valid, it is determined in step 308 whether the failure information read from the first sub-block is valid. will be judged.

If valid, the failure information of the first main block 13A or the failure information of the first sub-block 14A is set as the latest failure data.

If it is not valid, in step 309, the first sub-block 14A is corrected and the valid failure information is made the latest failure data.

Further, the above memory update is executed based on the flowchart shown in FIG.

First, in step 401, a main block counter is initialized (n-1). Next, the latest failure data read from the nth main block indicated by the main block counter is retrieved (step 40
2). Of course, since the value n of the main block counter is set to 1 in step 401, the latest failure data that is retrieved first is the latest failure data read from the main block counter first main block 13A.

Next, among the currently occurring fault data, fault data to be written into the n-th main block (hereinafter referred to as current fault data) is extracted (step 403).

The current failure data is updated every time a new failure occurs.
Furthermore, the failure information is written in advance in a memory such as a RAM that can be processed by the CPU 11 for each main block to which it is to be written.

Thereafter, the latest failure data and the current failure data are ORed (step 404). In this case, if the current failure data is not included in the latest failure data, it is added to the current failure data or the latest failure data. Of course, if the current fault data is already included in the latest fault data, it will not be further added to the latest fault data. Next, the latest failure data to which the current failure data was added is compared with the latest failure data immediately before the current failure data was added, and it is determined whether the number of failures has increased (step 405).

If the number of failures is not increasing, the value n of the main block counter is incremented by 1 (step 406).
. As a result of the increment, it is determined whether the value n of the main block counter is 4 (step 407). If n=4, the program ends, but n
If is 2 or 3, the process returns to step 402 and repeats steps up to step 405. In other words, the second. It is determined whether a new failure has occurred as a failure to be written into the third main blocks 13B, 13c.

On the other hand, if it is determined in step 405 that the number of failures is increasing, the address to which the failure data is to be written is set based on the failure data obtained by adding the current failure data to the latest failure data (step 408). For example, if the failure data to be written is (00100101
), the address is m25. (m=n-1). Here, rnJ is the value of the main block counter. Therefore, the address setting is performed according to the value of the main block counter. Second. This is performed for any of the third main blocks (sub-blocks).

Next, failure information to be written to the memory 12 is set (step 409). Fault information is set by inverting the fault data.
In the above example, the failure information is (11011010). This failure information is written to the address set as described above (step 410).

Next, a write address for the nth sub-block is set (step 411). The address to be written is set to be an address related to the address of the storage area written to the main block. For example, in the above example, the address is set to 25H (k=m+3).

Next, in step 412, failure information to be written in the n-th sub-block is set.

This is to set the value obtained by subtracting l from the binary number obtained by inverting the failure information set in step 409 as the failure information to be written.

For example, in the above example, (11011010) is inverted to become (00100101), and 1 is subtracted from it to obtain (00100100). The failure information set in this way is written to the storage area 12a at the address set in step 411 (step 4
13).

Next, the main block counter is updated (step 414). This is done similarly to step 408. Thereafter, it is determined whether the value n of the main block counter is 4 (step 415). If n=4, the process returns to step 402 and the failure information for the other n-th main block and n-th sub-block is updated. On the other hand, if n=4, this subroutine ends.

In the above storage device, since the stored content (failure information) is associated with the address of the storage area 12H where it is written, if incorrect information is written to the storage area 12a due to the influence of a momentary power outage, etc. It is possible to easily determine from the stored contents and address whether or not it has been written in error. Therefore, it is possible to prevent erroneously determining the location of the failure. Of course, the probability that erroneous failure information will be written to the corresponding address is not zero, but the probability is very low.

Therefore, the probability that erroneous failure data is determined to be correct can be significantly reduced compared to the conventional method.

In addition, in the storage device of this embodiment, newly generated failure information is written in addition to past failure information, so all failure information in one main block is extracted and the most By subtracting the storage content with the next largest number of information from the storage content with the largest number of information, and repeating this process sequentially, it is possible to know the order in which the failure occurred. This is important in elucidating the causal relationship of failure.

Note that the order of occurrence of faults can be known only for faults written in the same n-th main block, and cannot be known about the order of occurrence of faults between different n-th main blocks. Although there are 24 types of failure detection targets, an 8-bit memory is used, and the 24 types of failure information are divided into three groups, and each of the three groups is written to the three n-th main blocks. This is because there is. However, if a memory having the same number of bits as the fault detection target is used, the order in which all faults occur can be known.

Furthermore, the nth main block 13A (13B).

13C) and 0th subblock 14A (14B, 14C)
If either one of the failure information is valid (the address and the failure information correspond), and the other is not valid, the other is corrected based on one so that the contents of the two always match. Therefore, when failure information is read from this storage device, it is possible to further reduce the probability that incorrect information is mistakenly judged as correct.

In the above embodiment, newly occurring failures are added to previously occurring failures so that the order in which failures occur can be clarified; however, in cases where it is not necessary to clarify the order in which failures occur. In this case, only newly occurring failures may be written in a manner corresponding to the address.

[Effects of the Invention] As explained above, according to the failure information storage device of the present invention, failure information is made to correspond to each address of the first and second storage means and stored in the storage area of the corresponding address. Because it is written, it is possible to judge with a high probability whether or not the memory content (fault information) was written in error, and the probability of incorrectly determining the location of the fault can be reduced accordingly. can. Moreover, if the failure information written to either the first or second storage means is invalid, it is corrected based on the valid failure information, so that if the memory contents are written incorrectly, Therefore, it is possible to judge with a higher probability whether or not the problem occurs, and it is possible to prevent erroneously determining the location of a failure with a higher probability.

[Brief explanation of drawings]

FIG. 1(A) is a block diagram showing a configuration corresponding to the claims of the present invention, and FIGS. 1(B) and 1(C) are respectively 1. Figures 2 to 9 schematically show the contents of the second storage means, and Figures 2 to 9 show an embodiment of the present invention, Figure 2 is a schematic diagram thereof, and Figure 3 shows the contents of the memory. 4 is a diagram showing the addresses in the main block of the memory and the storage contents of the storage area to which the addresses are assigned,
FIG. 5 is a diagram showing addresses in memory sub-blocks and the storage contents of storage areas to which those addresses are assigned, and FIG. 6 is a diagram showing the main routine of a program for writing and correcting failure information to memory. 7 is a flowchart showing a subroutine for searching memory, FIG. 8 is a flowchart showing a subroutine for reading the latest failure information, and FIG. 9 is a flowchart showing a subroutine for updating failure information. ■... equipment, 2... failure detection means, 3... first storage means, 3a, 4a... storage area, 4... second storage means, 5... writing means, 6.・Reading means, 7
. . . Discrimination means, 8 .
Sub-block (second storage means).

Claims (1)

[Claims] a failure detection means for detecting a failure in each part of the device; a first storage means having a plurality of storage areas assigned addresses;
A second storage means has a plurality of storage areas each having an address associated with each address of the first storage means, and the failure information from the failure detection means is made to correspond to the address of the first storage means. and writes the content to the storage area of the first storage means at the corresponding address, and writes the content to correspond to the address of the second storage means associated with the address of the storage area of the first storage means where the failure information is written. a writing means for writing into a storage area of the second storage means to which an address is assigned; a reading means for reading the failure information written in the storage area of the first and second storage means at mutually related addresses; and this reading means. determining means for determining whether each piece of fault information read by corresponds to the address of the storage area in which it was written; and a fault read from either the first storage means or the second storage means. When the determining means determines that the information corresponds to the address and the failure information read from the other side does not correspond to the address, the failure information read from one side is transferred to the storage area from which the failure information was read. A failure information storage device comprising: a correction means for writing contents corresponding to the address of the other storage area associated with the address in the other storage area to which the address is attached.