JPH03256335A - Manufacture of gate electrode of transistor - Google Patents

Abstract

PURPOSE:To easily separate a gate electrode and a pad from the deposited layer on a lower layer by forming a lower layer resist in a 2-layer structure, and so forming the edge of a first lower layer near a base at a position retracted from the edge of a second lower layer on the first lower layer when openings for forming the gate electrode and the pad are formed. CONSTITUTION:After a metal deposited layer 24 is removed, a remaining first lower layer 12a as a mask first and second grooves 28, 30 are simultaneously or sequentially formed on a base 10 by wet etching or dry etching or both the etchings in combination. Then, a gate electrode material is deposited, and a gate electrode 32 and a pad 34 are formed. A deposited layer 38 is formed at the upper side of an upper layer resist pattern 18, a deposited layer 36 is formed on a second lower layer pattern 40, the electrode 32 is formed in the groove 28, and the pad 34 is formed in the groove 30 of the Al depositing material by the depositing. The edge of the opening 26a of the layer 12a is formed at a position retracted from the edge of the opening 26b of the pattern 40.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method of manufacturing a gate electrode of a transistor, and particularly to a method of manufacturing a gate electrode of a transistor, and in particular, a method of manufacturing a gate electrode of a transistor, etc. The present invention relates to a method of manufacturing an extremely short gate electrode.

(Prior Art) Conventionally, as technologies in this field, there have been the following, for example.

FIG. 2 is a sectional view showing the manufacturing process of the gate pole of such a conventional transistor.

First, as shown in FIG. 2(a), a lower resist layer 12 is formed on a base 10. As shown in FIG. Note that 14 is a channel region.

Next, as shown in FIG. 2(b), a lower resist pattern 16 is formed on the channel region 14 of the base 10 using photolithography.

Next, as shown in FIG. 2(c), an upper resist pattern 18 is formed. Therefore, first, an upper resist layer is coated and formed, and then a first opening 20 is formed on the lower resist pattern 16 through which a part of the surface thereof is exposed, and a gate pad part or a pad part for wiring connection is formed. A second opening 22 is formed by etching.

Next, as shown in FIG. 2(d), a suitable metal such as An (aluminum) is directionally deposited on the upper layer from the surface side of the resist pattern 18 at an angle of θ with respect to the normal to the underlying surface. Metal vapor deposition layer 24 (24a, 24b,
24c). The vapor deposition direction θ in this case is determined depending on the design depending on how the gate length of the gate electrode to be formed in a subsequent process is determined. By this directional vapor deposition, the upper surface of the upper resist pattern 18,
Metal vapor deposition layers 24a, 24b, and 24c are formed on the exposed surface of the lower resist pattern 16 in the first opening 20 and the exposed surface of the base 10 in the second opening 22, respectively. In this case, as is well known, the width of the metal vapor deposition layer 24b in the channel direction is determined by the above-mentioned vapor deposition direction θ and the position of the vapor deposition surface and the upper surface edge portion of the first opening 20 examples of the upper resist pattern 18.

Next, as shown in FIG. 2(e), a third opening 26 is formed in the lower resist pattern 16. In this case, using the metal vapor deposited layer 24 as a mask, dry etching is performed using an appropriate ion species, for example, R I E (R
active Ion Etching).
A third opening 26 is formed to partially expose the surface of the base 10. By this etching, the metal vapor deposited layer 24b
The lower portion of the edge portion of the upper resist pattern 18 is also underetched.

Next, as shown in FIG. 2(f), the exposed surface of the base 10 is etched to form a first groove (recess) 28 for forming a gate electrode and a second groove (recess) for forming a pad portion. )
30 simultaneously or sequentially. Therefore, first, the metal vapor deposited layer 24b temporarily provided in the first opening 20 and the metal vapor deposited layer 24c in the second opening 22 are removed, and then this etching is performed by one or both of dry etching and wet etching. This is done using a combination of

Subsequently, as shown in FIG. 2(g), a suitable gate electrode material is deposited to form the gate electrode 32 and the second gate electrode in the first groove 28.
Pad portions 34 are formed in each groove 30 at the same time. As is well known, the width (gate length) W of the gate electrode 32 in the channel direction in this case is the width of the edge portion of the lower resist pattern 16 in contact with the base 10 and the upper resist pattern forming the wall of the first opening 20. The width W2 of the pad portion 34 in the channel direction is determined by the width between the edge portions of the upper surface of the pattern 18, and the width W2 of the pad portion 34 in the channel direction is determined by the width between the edge portions of the upper surface on both sides of the upper resist pattern 18 forming the wall of the second opening 22. It is determined by

The other vapor deposition layer 36 (formed on the lower resist pattern 16) and the vapor deposition layer 38 (formed on the upper resist pattern 18) formed by this vapor deposition are usually separated from the gate electrode 32 and pad portion 34. are not continuous but are formed at intervals.

Next, as shown in FIG. 2(h), when the lower resist pattern 16 and the upper resist pattern 18 on the base 10 are removed by so-called lift-off, the first groove 28 of the base 10 is removed.
A gate electrode 32 having a narrow width in the channel direction is formed in the second trench 30, and a gate electrode 32 having a narrow width in the channel direction is formed in the second trench 30.
A pad portion 34 wider than 2 is left behind.

In this way, according to the above-described conventional technology, it is possible to form a gate electrode of a transistor whose width is narrow to a certain extent, exceeding the resolution of the resist.

(Problem B to be Solved by the Invention) However, in the case of the above-described conventional method for forming the gate electrode of a transistor, as shown in FIG.
The lower resist pattern 16 forming the wall of the opening 26 is normally etched into a tapered shape, so when a gate electrode material is deposited, the deposited layer 36 formed on the lower resist pattern 16 and the gate electrode 32 are separated. It was difficult for them to form separately without being continuous. Therefore, even if the lower resist pattern 16 and the upper resist pattern 18 are removed by the lift-off method, the vapor deposited layer 36 remains without being separated from the gate electrode 32, which causes problems in the post-process for fabricating the semiconductor device. there were.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a highly reliable method for manufacturing a gate electrode of a transistor, in which the gate electrode can be easily separated from a deposited layer on a lower resist.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a gate electrode of a transistor, in which a lower layer consisting of two layers, a first lower layer and a second lower layer, is sequentially formed on a base. further forming the second lower layer pattern on the channel region; a first opening providing a partially exposed surface of the second lower layer pattern; and a second opening providing a partially exposed surface of the first lower layer. selectively etching the first lower layer exposed at the second opening to expose the underlayer, and then exposing the exposed surface of the second lower layer pattern and the underlayer; A step of forming a metal vapor deposition layer on the surface and the upper surface of the upper resist pattern using a directional vapor deposition technique, and using the metal vapor deposition layer as a mask, selectively etching the second lower layer and the first lower layer in order, and etching the first lower layer. forming a third opening in which the underlying surface is exposed by forming an edge of the opening at a position set back from an edge of the second lower layer;
etching the exposed surfaces exposed in the opening and the third opening to form a first groove for forming a gate electrode and a second groove for forming a pad portion in the base; A step of simultaneously forming a gate electrode and a pad metal layer by depositing a gate metal in the second groove, and a step of removing the second lower layer pattern and the upper resist pattern are performed.

Further, the step of sequentially forming two lower layers, a first lower layer and a second lower layer, on the underlayer, and further forming the second lower layer pattern on the channel region, and using the second lower layer pattern as a mask, etching away the first lower layer and forming both the first lower layer and the second lower layer only on the channel region;
The method may include a step of forming an upper resist pattern, and forming a first opening in which the surface of the second lower pattern is partially exposed, and a second opening in which the surface of the base is partially exposed.

(Function) As described above, in the present invention, the lower resist has a two-layer structure, and when forming an opening for forming a gate electrode and a pad portion, the edge portion of the first lower layer near the base is 1
Since the gate electrode and the pad portion are formed at a position recessed from the edge portion of the second lower layer on the lower layer, the gate electrode and the pad portion can be easily separated from the vapor deposited layer on the lower layer. Furthermore, the width of the gate electrode does not depend on the edge portion of the first lower layer, and can be formed narrower than the limit of resist resolution with good reproducibility.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of the manufacturing process of a gate electrode of a transistor showing an embodiment of the present invention.

First, as shown in FIG. 1(a), a lower layer 1 is placed on a base 10.
2, that is, a first lower layer 12a and a second lower layer 12b are formed.

As the base 10, a compound semiconductor such as GaAs, S
i or other materials commonly used as substrates. Furthermore, the base 10 may or may not have a region necessary for the semiconductor element formed therein in advance. Furthermore, the lower layer 12 (12a).

12b), the first lower layer 12a is a PC.
VD (Plasma Chem)
The SiN film deposited by the ical vapor deposition method, the second lower layer 12b, is made of 0DU manufactured by Tokyo Ohka.
I? (product name), but other materials can also be used if these materials can be selectively etched away by selecting an appropriate ion species when forming the third opening in the post-process. can. Further, the layer thicknesses of the first lower layer 12a and the second lower layer 12b are set so that the gate electrode 32 and the vapor deposition layer 36 formed on the second lower layer 12b can be easily separated from each other, as described later.

Next, as shown in FIG. 1(b), a second lower layer pattern 40 is formed on the channel region 14 of the base 10.

Next, as shown in FIG. 1(c), an upper resist pattern 18 is formed, and a first opening 20 is formed in which a portion of the surface of the second lower layer pattern 40 is exposed and a portion of the surface of the first lower layer 12a is exposed. An exposed second opening 22 is formed. As an example of the upper resist pattern 18, LMRF22 (manufactured by Fuji Yakuhin) is used.
(product number), but other suitable resists may be used. However, it is desirable to obtain a shape in which the opening widens toward the base 10 side.

Next, the first lower layer 12a exposed through the second opening 22
are selectively etched away as shown in FIG. 1(d).

Next, as shown in FIG. 1(e), the metal vapor deposition layer 24 (2
4a, 24b, 24c). The metal vapor deposited layer 24 is made of Aj2 as an example, but the material is not limited to this as long as it can be used as a mask for various etchings in subsequent steps, and the layer thickness may be set appropriately. Furthermore, the width of the metal vapor deposited layer 24b in the channel direction within the first opening 20 is determined by the vapor deposition direction θ of this metal material, and this vapor deposition direction θ is determined by the width of the gate electrode to be formed along the channel direction. You can set it appropriately according to
The first lower layer 12a is etched using SF, for example.
This may be carried out by the IE method, whereby the first lower layer 12a is selectively removed and the surface of the base 10 is partially exposed in the second opening 22.

Next, as shown in FIG. 1(f), a third opening 26 (26a26) is formed in the second lower layer pattern 40 and the first lower layer 12a.
b) form. In this case, for example, RIE using 02
After selectively vertically etching the second lower pattern 40 to form the opening 26b by etching, for example, SF etching is performed.
1, the first lower layer 12a is selectively etched by the RIE method using 4 to form an opening 26a and partially expose the surface of the base 10. The edge portion of the opening 26b is
The opening 26a is formed so as to coincide with the edge of the metal vapor deposition layer on the opening side, and the edge of the opening 26a is slightly set back from the edge of the opening 26b.

Subsequently, as shown in FIG. 1(g), a metal vapor deposition layer 24 is formed.
After removing (24a, 24b, 24c), using the remaining first lower layer 12a as a mask, first grooves 28 and second grooves are formed in the base 10 by wet etching, dry etching, or a combination of both.
The grooves 30 are formed simultaneously or sequentially.

Next, as shown in FIG. 1(h), a gate electrode material is deposited to form a gate electrode 32 and a pad portion 34. For example, A2 is used as the gate electrode material, but the material is not limited thereto.

Through this vapor deposition, the Af vapor deposition material forms a vapor deposition layer 38 above the upper resist pattern 18, a vapor deposition layer 36 above the second lower pattern 40, a gate electrode 32 in the first groove 28, and a pad portion 34 in the second groove 30. is formed. Since the edge of the opening 26a of the first lower layer 12a is formed at a position set back from the edge of the opening 26b of the second lower layer pattern 40, the thickness of each layer of the first lower layer 12a and the second lower layer 12b is 1
By appropriately selecting the depths of the groove 28 and the second groove 30 and the vapor deposition thickness of the gate electrode material, the gate electrode 32 and the pad portion 34 can be easily separated from the vapor deposition layer 36 on the second lower pattern 40. can be formed.

Next, as in the conventional method, as shown in FIG. 1(i), the upper resist pattern 18 and the second lower layer pattern 40 are removed by lift-off, so that the gate electrode 32 and the pad portion 34 remain. Ru.

FIG. 3 is a cross-sectional view of the manufacturing process of a gate electrode of a transistor showing another embodiment of the present invention.

First, as shown in FIG. 3(a), the lower layer 1 is placed on the base 10.
2 (first lower layer 12a and second lower layer 12b).

This step is similar to the step shown in FIG. 1(a) described above.

Next, as shown in FIG. 3(b), a second lower layer pattern 40 is formed on the channel region 14 of the base 10.

This step is similar to the step shown in FIG. 1(b).

Next, as shown in FIG. 3(c), the first lower layer 12a is etched away using the second lower layer pattern 40 as a mask, and both the first and second lower layers are formed only on the channel region.

Next, as shown in FIG. 3(d), an upper resist pattern 18 is formed, and a first opening 20 is formed in which the surface of the second lower pattern 40 is partially exposed, and the surface of the base 10 is partially exposed. A second opening 22 is formed.

Next, as shown in FIG. 3(e), the metal vapor deposition layer 24 (2
4a, 24b, 24c).

Next, as shown in FIG. 3(f), a third opening 26 (26a) is formed in the second lower layer pattern 40 and the first lower layer 12a.

26b). In this case, for example, R using 02
After selectively etching the second lower layer pattern 40 vertically by the IE method to form the opening 26b, for example,
By RIE using SF, the first lower layer 12a is selectively etched to form an opening 26a, and the surface of the base 10 is partially exposed. The edge portion of the opening 26b is formed to match the edge portion of the metal vapor deposition layer on the opening side, and the edge portion of the opening 26a is formed to be slightly inside than the edge portion of the opening 26b. .

Subsequently, as shown in FIG. 3(g), a metal vapor deposition layer 24 is formed.
After removing (24a, 24b, 24c), using the remaining first lower layer 12a as a mask, first grooves 28 and second grooves are formed in the base 10 by wet etching, dry etching, or a combination of both.
The grooves 30 are formed simultaneously or sequentially.

Next, as shown in FIG. 3(h), a gate electrode material is deposited to form a gate electrode and a pad portion.

Through this vapor deposition, the An vapor deposition material forms a vapor deposition layer 38 above the upper resist pattern 18, a vapor deposition layer 36 above the second lower pattern 40, a gate electrode 32 in the first groove 28, and a pad portion 34 in the second groove 30. is formed. Since the edge of the opening 26a of the first lower layer 12a is formed to be recessed from the edge of the opening 26b of the second lower layer pattern 40, the thickness of each layer of the first lower layer 12a2 and the second lower layer 12b is , by appropriately selecting the depths of the first groove 28 and the second groove 30, and the vapor deposition thickness of the gate electrode material.
The pad portion 34 can be easily formed separately from the deposited layer 36 on the second lower pattern 40.

Next, as shown in FIG. 3(i), similar to the conventional method, by removing the upper resist pattern 18 and the second lower layer pattern 40 by lift-off, the gate electrode 32, the pad portion 34, and the first lower layer pattern are removed. 12a remains formed.

FIG. 4 shows the experimental results of parameters such as the thickness of each of these layers, vapor deposition thickness, etc., and the ratio of separated formation.

That is, the deposition thickness of the gate electrode material, that is, the gate electrode 32
When the thickness of the gate electrode 32 is thinner than the sum of the depths of the first lower layer 12a and the first groove 28, the gate electrode 32 and the vapor deposited layer 36 are formed separately, and when the thickness is thicker, it becomes difficult to form the separation. I know what will happen. Therefore, the required gate electrode 32
From the thickness of the first lower layer 12a and the depth of the first groove 28, the layer thickness of the first lower layer 12a that allows easy separation can be set.

The width of the gate electrode 32 in the channel direction is determined by the width W between the edge of the opening 26b of the second lower pattern 40 and the edge of the upper surface of the upper resist pattern 18 forming the wall of the first opening 20. , opening 26b of first lower layer 12a
A narrow gate electrode can be formed with good reproducibility regardless of the edge portion of the gate electrode.

Similarly, the width of the pad portion 34 in the channel direction is determined by the width W2 between the edge portions of the upper surface on both sides of the upper resist pattern 18 forming the wall of the second opening 22.

Next, as in the conventional method, as shown in FIG. 1(i), the upper resist pattern 18 and the second lower layer pattern 40 are removed by lift-off, so that the gate electrode 32 and the band portion 34 remain. Ru.

In this embodiment, the first lower layer 1 in the second opening 22
It is possible to prevent thinning of the upper resist pattern 18 that may occur during etching of the etching pattern 2a, and to obtain a gate electrode with a desired narrow width with high precision.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, when the lower resist has a two-layer structure and an opening for forming a gate electrode and a pad portion is formed, Since the edge portion of the first lower layer is formed at a position recessed from the edge portion of the second lower layer on the first lower layer, the gate electrode and the pad portion can be easily separated from the deposited layer on the lower layer. Furthermore, the width of the gate electrode does not depend on the edge portion of the first lower layer, and can be formed narrower than the limit of resist resolution with good reproducibility.

Furthermore, thinning of the upper resist pattern can be prevented, and a gate electrode with a desired narrow width can be obtained with high precision.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the manufacturing process of a gate electrode of a transistor showing an embodiment of the present invention, FIG. 2 is a sectional view of the manufacturing process of a gate electrode of a conventional transistor, and FIG. 3 is a sectional view of another embodiment of the invention. Cross-sectional view of the manufacturing process of transistor gate electrodes,
FIG. 4 shows the experimental results of the rate at which the gate electrode and the vapor deposited metal on the second lower layer pattern are formed separately, using the thickness of the first lower layer, the thickness of the underlying groove, and the elegance of the gate electrode as parameters. It is a diagram. 10... Base layer, 12a... First lower layer, 12b...
Second lower layer, 14... Channel region, 18... Upper layer resist pattern, 20... First opening, 22... Second opening, 24 (24a, 24b, 24c)
-Metal deposited layer, 26 (26a, 26b) ・=
Third opening, 28...first groove, 30...second groove, 3
2... Gate electrode, 34... Pad portion, 36.38
... Vapor deposition layer, 40... Second lower layer pattern.

Claims (2)

[Claims] (1) (a) Forming a lower layer consisting of two layers, a first lower layer and a second lower layer, on the base in order, and further forming the second lower layer pattern on the channel region, (b) The second lower layer a first opening providing a partially exposed surface of the pattern; and a second opening providing a partially exposed surface of the first underlying layer.
(c) selectively etching the first lower layer exposed at the second opening to expose the base, and then forming an exposed surface of the second lower resist pattern; (d) using the metal vapor deposition layer as a mask, selectively forming a second lower layer and then the first lower layer in order; (e) forming a third opening in which the underlying surface is exposed by etching so that the edge of the opening in the first lower layer is set back from the edge in the second lower layer; (f) etching the exposed surfaces exposed in the second opening and the third opening to form a first groove for forming a gate electrode and a second groove for forming a pad portion in the base; a step of simultaneously forming a gate electrode and a pad metal layer by depositing a gate metal in the first groove and the second groove; and (g) a step of removing the second lower layer pattern and the upper resist pattern. A method for manufacturing a gate electrode of a transistor. (2) (a) forming a lower layer consisting of two layers, a first lower layer and a second lower layer, on the base in order, and further forming the second lower layer pattern on the channel region; (b) the second lower layer; etching away the first lower layer using the pattern as a mask and forming both the first lower layer and the second lower layer only on the channel region; and (c) forming an upper resist pattern so that the surface of the second lower layer pattern is A first opening that partially exposes the opening, and a second opening that partially exposes the surface of the base.
(d) forming a metal vapor deposition layer on the exposed surface of the second lower layer pattern, the exposed surface of the underlayer, and the upper surface of the upper resist pattern using a directional vapor deposition technique; Second as a mask
The lower layer and the first lower layer are selectively etched in this order so that the edge of the opening in the first lower layer is set back from the edge of the second lower layer to form a third opening in which the underlying surface is exposed. (e) etching the exposed surfaces exposed in the second and third openings to form a first groove for forming a gate electrode and a second groove for forming a pad portion in the base; (f) forming a gate electrode and a pad metal layer simultaneously by depositing a gate metal in the first groove and the second groove; (g) the second lower layer pattern and the upper resist layer; 1. A method of manufacturing a gate electrode of a transistor, comprising sequentially performing steps of removing a pattern.