JPH0346340A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To execute a fine gate patterning operation by a method wherein an interval between sidewalls by an insulating film which is formed between a source and a drain is replaced by an opening part in a gate patterning operation. CONSTITUTION:A source electrode and a drain electrode 3, 4 are formed on a semiconductor active layer 2 which has been formed on a semiconductor substrate 1; sidewalls 8S, 8d by an insulating film 8 are formed between the source and the drain; after that, the whole surface is coated with a photoresist 5; a gate patterning operation of the photoresist 5 is executed to form an opening part; after that, the semiconductor active layer is etched to form a recess region 6; a gate electrode 7 is vapor-deposited on the whole surface to form the gate electrode 7 in the recess region 6. As a result, even when an interval between the source and the drain is narrowed, a gate length is decided by the sidewalls. Thereby, a gate patterning operation which is executed after that can be executed by aligning a mask with an accuracy that an interval between the sidewalls is opened surely; and a gate can easily be photoengraved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which the source-drain interval can be shortened.

[Conventional technology]

Figures 2 (a) to (d) show that the source-drain spacing is
FIG. 3 is a process cross-sectional view for explaining a method for manufacturing a semiconductor device in a wide case.

First, as shown in FIG. 2(a), a source t4 is placed on a semiconductor active layer 2 formed on a semiconductor substrate 1 made of GaAs.
After the electrode 3 and the drain electrode 4 are formed with an interval of Lso as shown, a photoresist 5 is applied over the entire surface by a spin-to-1 method or the like for gate photolithography. At this time, the resist thickness t2 between the source and drain is thicker than the resist thickness t□ on the source electrode 3 and drain electrode 4. Next, as shown in FIG. 2(b), an opening is formed in the photoresist 5 by gate photolithography,
The semiconductor active layer 2 in the gate formation region is etched to form a recess region 6. Photoresist at this time. Next, as shown in FIG. 2(e), the gate metal 7'
is deposited on the semiconductor active layer 2 in the recess region 6 through the opening L8 of the photoresist 5. Thereafter, the photoresist is removed by lift-off, and a gate electrode 7 is formed in the recess region 6 as shown in FIG. 2(d).

As described above, a semiconductor device is formed. Even when the north-drain interval Lso is wide as shown in FIG. 2(a), the resist thickness t2 is large between the source electrode 3 and the drain electrode 4. Therefore, gate patterning is difficult.

Under these circumstances, if the source-drain spacing is further narrowed to Lso as shown in Figure 3, the resist thickness t between the source and drain becomes even thicker, making gate patterning even more difficult. . Narrow sauce
When performing getto photoengraving at the drain interval Lso',
In addition to increasing the difficulty of mask alignment, the increased resist thickness also makes fine gate patterning difficult.

[Problem to be solved by the invention]

Conventional semiconductor devices are configured as described above, so
When the source-drain distance is narrowed, it becomes difficult to match the mask for gate photolithography, and the resist thickness between the source and drain increases, making it difficult to perform fine gate patterning. Ta.

This invention was made to solve the above-mentioned problems, and provides a method for manufacturing a semiconductor device that facilitates gate photolithography mask alignment and allows fine gate patterning even when the source-drain distance is narrowed. The purpose is to obtain.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, after forming a source electrode and a drain electrode by narrowing the source-drain interval, an insulating film is deposited on the entire surface to a desired thickness, and the gap between the source and drain is etched by anisotropic etching. A sidewall is provided between the sidewalls, and this sidewall spacing is used as an opening during gate patterning.When performing photoresist and gate photolithography after that, the mask alignment accuracy is sufficient as long as there is an opening between the sidewalls. That is.

[Effect]

The method for manufacturing a semiconductor device according to the present invention substitutes the sidewall interval of the insulating film formed between the source and drain for the opening during gate patterning.
Since the sidewall spacing determines the gate length, when applying photoresist and performing gate photoengraving after that, the gate length is already determined by the sidewalls, so it is necessary to ensure that there is an opening between the sidewalls. All you have to do is match the mask to , making photoengraving easier.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1(a) to 1(f).

First, as shown in FIG. 1(a), a source electrode 3, After forming the drain spacing electrode 4,
The entire surface is covered with an insulating film 8 such as a SiN film. At this time, the plasma CVD method is used to form the insulating film 8. Plasma C
According to the VD method, since the step coverage for the stepped portion is good, the insulating film 8 is laminated corresponding to the surface shape as shown in FIG. 1(a). Next, anisotropic etching is performed using a dry etching method such as RIE to leave an insulating film between the source and drain as shown in FIG. 1(b). Hereinafter, this insulating film will be referred to as sidewalls 88, 8D. The semiconductor active layer 2 is the outermost surface between the sidewalls 83 and 8D. Further, the distance between the sidewalls 88 and 8D, l, determines the gate length. By optimizing the thickness of the insulating film 8, the coating shape, and the anisotropic etching conditions, the gate length can be shortened.

Next, as shown in FIG. 1(C), the thickness t4 of the resist between the photoresist source and drain for gate photolithography is naturally compared to the resist thickness t1 on the source electrode 3 and drain electrode 4. It's getting thicker. However, since the opening that determines the gate length L6 is fixed by the interval between the sidewalls 83 and 8D, the opening in the photoresist formed by gate patterning is formed between the sidewalls 8S and 8D, as shown in FIG. 1(d). It is only necessary to ensure that the space between 8D is opened, and alignment accuracy and the like can be easily achieved, thereby facilitating mask alignment. However, the opening of the photoresist 5 should not reach above the source electrode 3 and drain electrode 4. After the opening is reliably formed, the semiconductor active layer 2 is etched to form the recess region 6. After that, as shown in FIG. 1(e), a gate metal 7' is deposited, and unnecessary gate metal 7' on the photoresist 5 is removed by a lift-off method, as shown in FIG. 1(f). , a gate electrode 7 is formed within the recess region 6.

In addition, in FIG. 1(f), the side wall 88.

Although the case where 8D is removed is shown, it may be left as is if there is no problem in terms of characteristics, regardless of the appearance.

Also, in the above example, it is impossible! Although the SiN film has been described as an example of iMs, similar effects can be obtained by using a SiON film or a SiO2 film.

〔Effect of the invention〕

As explained above, in the present invention, source and drain electrodes are formed on a semiconductor active layer formed on a semiconductor substrate, and a sidewall of an insulating film is formed between the source and drain. This photoresist is gate patterned to form an opening, and then the semiconductor active layer is etched to form a recess region, and Ge~I-flJi is deposited on the entire surface to form an opening in the recess region. Since the gate electrode is formed, even if the source-drain spacing is narrowed, the gate length is determined by the sidewalls, so the gate patterning performed afterwards must be done to ensure that the gap between the sidewalls is opened. It is only necessary to match the masks with high precision, making gate photolithography easier.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are process cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (f) are
d) is a process cross-sectional view showing a conventional semiconductor device manufacturing method;
FIG. 3 is a sectional view showing another conventional example in which the source-drain interval is narrowed. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor active layer, 3 is a source electrode, 4 is a drain electrode, 5 is a resist, 6 is a recess region, 7 is a gate electrode, 8 is an absolute R film, 8
S and 8D are side walls. The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] After forming a source electrode and a drain electrode on a semiconductor active layer formed on a semiconductor substrate, a step of covering the entire surface with an insulating film and anisotropic etching using dry etching are performed to optionally remove the insulating film between the source and drain. a step of leaving a sidewall shape with a spacing of A method for manufacturing a semiconductor device, comprising the steps of etching to form a recessed region, depositing gate metal over the entire surface, and removing unnecessary gate metal on the photoresist by a lift-off method.