JPH03257516A - Protection system for battery at bus terminal - Google Patents

Protection system for battery at bus terminal

Info

Publication number
JPH03257516A
JPH03257516A JP2057035A JP5703590A JPH03257516A JP H03257516 A JPH03257516 A JP H03257516A JP 2057035 A JP2057035 A JP 2057035A JP 5703590 A JP5703590 A JP 5703590A JP H03257516 A JPH03257516 A JP H03257516A
Authority
JP
Japan
Prior art keywords
battery
memory
cpu
release button
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2057035A
Other languages
Japanese (ja)
Inventor
Masabumi Nishioka
正文 西岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2057035A priority Critical patent/JPH03257516A/en
Publication of JPH03257516A publication Critical patent/JPH03257516A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To protect the memory contents by outputting an alarm signal to a CPU when the push of a release button is detected then outputting a signal to a memory buffer to inhibit the R/W operations of a memory when detection of the exclusion of a battery. CONSTITUTION:A release button switch 1 is used for taking out a battery, and a sensor 2 detects the come-off of the battery. These switch 1 and sensor 2 are connected to a control circuit 3 which is connected to a CPU 4 and a memory buffer 5. The power is always supplied to the circuit 3 and the buffer 5 from a secondary battery 6. Then the circuit 3 outputs an alarm signal to the CPU 4 with detection of the push of the button 2 and then outputs a signal to the buffer 5 to inhibit the R/W operations of a memory with detection of the take-out of the battery. Thus it is possible to prevent the destruction of the memory contents when a working battery is inadvertently excluded due to an operating mistake.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はハンディターミナルに関し、特に動作中のオペ
ミスによる電池抜は保護方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a handy terminal, and particularly to a protection system against battery removal due to an operational error during operation.

〔従来の技術〕[Conventional technology]

従来、この種のハンディターミナルは、オペミスにより
、動作中に電池を抜こうとした場合に警告をだす機能、
電池抜けが発生した場合に、メモリの内容を保護する機
能が不足していた。
Conventionally, this type of handy terminal has a function that issues a warning if the battery is removed during operation due to an operational error.
There was a lack of functionality to protect the contents of memory in the event of a battery disconnection.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述したこの種のハンディターミナルは、オペミスによ
り、動作中に電池を抜こうとした場合に警告をだす機能
、電池抜けが発生した場合に、メモリの内容を保護する
機能が不足している為に、オペミスにより不用意に動作
中に電池が抜かれた為に、メモリの内容を破壊すること
があるという欠点がある。
Due to an operational error, this type of handheld terminal mentioned above lacks the function to issue a warning if an attempt is made to remove the battery during operation, and the function to protect the contents of the memory in the event that the battery is removed. However, if the battery is carelessly removed during operation due to an operational error, the contents of the memory may be destroyed.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のハンディターミナルにおける電池抜は保護方式
の構成は、電池を取りはずして抜く為のリリースボタン
スイッチ、電池抜けを検出する為のセンサ、前記リリー
スボタンが押されたことを検出してCPUに警告信号を
出力したり、前記電池抜けを検出して前記CPUのデー
タバスをロックし、メモリの内容を保護する回路を有す
ることを特徴とする特 〔実施例〕 次に、本発明について図面を参照して説明する。
The protection system for battery removal in the handy terminal of the present invention consists of a release button switch for removing and removing the battery, a sensor for detecting battery removal, and a warning to the CPU when the release button is detected to be pressed. [Embodiment] Referring to the drawings for the present invention, the present invention is characterized by having a circuit that outputs a signal, detects the disconnection of the battery, locks the data bus of the CPU, and protects the contents of the memory. and explain.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

電池を抜く為のリリースボタンスイッチ1、電池抜けを
検出する為のセンサ2は、制御回路3に接続される。制
御回路3は、CPU4、メモリバッファ5と接続される
。制御回路3、メモリバッファ5は、常時、副電池6か
ら電源を供給される。
A release button switch 1 for removing the battery and a sensor 2 for detecting battery removal are connected to a control circuit 3. The control circuit 3 is connected to the CPU 4 and the memory buffer 5. The control circuit 3 and memory buffer 5 are always supplied with power from the auxiliary battery 6.

制御回路3は、電池を抜く為のリリースボタン2が押さ
れたことを検出すると、CPU4に対してアラーム信号
を出力し、その後、電池が抜かれたことを検出すると、
メモリバッファに対しメモリのR/Wを禁止する信号を
出力する。
When the control circuit 3 detects that the release button 2 for removing the battery has been pressed, it outputs an alarm signal to the CPU 4, and after that, when it detects that the battery has been removed,
Outputs a signal to the memory buffer to inhibit memory R/W.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、電池を抜く為のリリース
ボタンが押されたことを検出すると、CPUに対してア
ラーム信号を出力し、その後電池が抜かれたことを検出
するとメモリバッファに対しメモリのR/Wを禁止する
信号を出力することにより、オペミスにより動作中、不
用意に電池を抜くことを少なくシ、また、もし抜いてし
まった場合でも、メモリの内容を保護することができる
効果がある。
As explained above, when the present invention detects that the release button for removing the battery has been pressed, it outputs an alarm signal to the CPU, and when it detects that the battery has been removed, it outputs an alarm signal to the memory buffer. By outputting a signal that prohibits R/W, it is possible to reduce the possibility of accidentally removing the battery during operation due to an operational error, and to protect the contents of the memory even if the battery is removed. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図である。 1・・・電池を抜く為のリリースボタン、2・・・電池
抜けを検出する為のセンサ、3・・・制御部、4・・・
CPU15−・・メモリバッファ、6・・・副電池。
FIG. 1 is a block diagram of one embodiment of the present invention. 1...Release button for removing the battery, 2...Sensor for detecting battery removal, 3...Control unit, 4...
CPU15--Memory buffer, 6--Sub battery.

Claims (1)

【特許請求の範囲】[Claims] 電池を取りはずして抜く為のリリースボタンスイッチ、
電池抜けを検出する為のセンサ、前記リリースボタンが
押されたことを検出してCPUに警告信号を出力したり
、前記電池抜けを検出して前記CPUのデータバスをロ
ックし、メモリの内容を保護する回路を有することを特
徴とするハンディターミナルにおける電池抜け保護方式
Release button switch for removing and removing the battery,
A sensor for detecting battery disconnection, detects when the release button is pressed and outputs a warning signal to the CPU, or detects battery disconnection and locks the data bus of the CPU, saving the contents of the memory. A battery disconnection protection method for a handy terminal characterized by having a protective circuit.
JP2057035A 1990-03-07 1990-03-07 Protection system for battery at bus terminal Pending JPH03257516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2057035A JPH03257516A (en) 1990-03-07 1990-03-07 Protection system for battery at bus terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2057035A JPH03257516A (en) 1990-03-07 1990-03-07 Protection system for battery at bus terminal

Publications (1)

Publication Number Publication Date
JPH03257516A true JPH03257516A (en) 1991-11-18

Family

ID=13044188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2057035A Pending JPH03257516A (en) 1990-03-07 1990-03-07 Protection system for battery at bus terminal

Country Status (1)

Country Link
JP (1) JPH03257516A (en)

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