JPH03257643A - Information processor - Google Patents

Abstract

PURPOSE:To shorten time for generating a logic/real address without requiring useless machine cycle for address conversion by providing the first and second address conversion buffer circuits. CONSTITUTION:When the first address conversion buffer circuit 100 and no real address exists, before generating the real address by a real address generating circuit 300, the second address conversion buffer circuit 400 is accessed and the pair of the logic/real address, which is generated when the same address generation request is continuously outputted plural times from the first address conversion buffer circuit 100, is written into the first address conversion buffer circuit 100. Simultaneously, the pair of the logic/real excluded from the first address conversion buffer circuit 100 is written into the second address conversion buffer circuit 400. Thus, any useless machine cycle is not required for the address conversion and the time for generating the logic/real address is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having virtual memory, and more particularly to an address conversion buffer circuit that converts a logical address created by a virtual computer into a real address.

[Prior Art] Conventionally, this type of address translation buffer circuit has been designed to have a large buffer capacity in order to reduce conversion loss from a logical address to a real address, or to have multiple buffers for different purposes, for example, one for fetching instructions and one for fetching operands. was.

[Problems to be Solved by the Invention] In the conventional method described above, as the machine cycles of computers become extremely fast, the capacity of the address translation buffer that can be accessed within one machine cycle time is limited, and it is no longer possible to have a large buffer capacity. Therefore, data that could be used is replaced by new data due to buffer capacity limitations, and when trying to use old data again, a real address is created from the virtual address and stored in the address translation buffer, so address translation is not possible. This has the disadvantage that it requires wasted machine cycles, and since address translation buffers are provided for each purpose, logical addresses/real addresses must be generated for each request from each address translation buffer even when a common address area is used. There was a drawback that it was done twice.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that does not require wasted machine cycles for address conversion and reduces the time required to generate logical addresses/real addresses.

[Means for Solving the Problems] An information processing device of the present invention includes an address translation buffer that translates from a virtual address to a real address, and updates the contents of a replacement memory every time the address translation buffer is accessed. Record that the data is the latest, and if the required data does not exist in the address conversion buffer, create a new real address from the virtual address and store it in the block to be evicted based on the read data of the replace memory. a first address translation buffer circuit and a second address translation buffer circuit; and a real address generation circuit that indexes an address translation table in a main storage device and generates a real address corresponding to a virtual address; If the logical address/real address translation pair corresponding to the virtual address is not registered in the address translation buffer, the address translation buffer circuit issues a real address generation request to the second address translation buffer circuit, and requests the same real address generation. When it is notified from the second address translation buffer circuit that the address translation buffer circuit continues for a predetermined number of times, the logical address/real address translation pair of the level to be evicted from the address translation buffer is read out and sent to the second address translation buffer circuit. , takes in the real address held in the second address translation buffer circuit and stores the logical address/real address pair in the address translation buffer at the evicted level, and the second address translation buffer circuit
When the same real address generation request is received a predetermined number of times consecutively from the address translation buffer circuit of the first address translation buffer circuit, the real address is passed to the corresponding first address translation buffer circuit, and data registration instruction is given to the address translation buffer. The translation pair of logical address/real address evicted from the first address translation buffer circuit is registered in the own address translation buffer, and if the same real address generation request is not repeated a predetermined number of times, the own address translation buffer is indexed and the logical address is /Checks whether a real address translation pair is registered, and if not registered, generates a real address by the real address generation circuit and notifies the corresponding first address translation buffer circuit.

[Function] If the first address translation buffer circuit is accessed and a real address does not exist, the second address translation buffer circuit is accessed and the first address translation is performed before the real address generation circuit generates a real address. Writing the logical address/real address pair generated when the same address generation request is consecutively received from the buffer circuit a predetermined number of times into the first address translation buffer circuit, and the logical address/real address evicted from the first address translation buffer circuit. the second pair of
write to the address translation buffer circuit.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

The information processing device of this embodiment performs logical/real address conversion corresponding to an instruction fetching unit 1 that requests instruction fetching, an operand fetching unit 2 that requests fetching data for operation, and each fetching unit 1.2. An address translation buffer circuit 100 for instructions, an address translation buffer circuit 200 for operands, and an address translation buffer circuit 100 for instructions using an address translation buffer (TLB). The address translation buffer circuit 400 when there is no corresponding real address in the operand address translation buffer circuit 200 and the second address translation buffer circuit 4
It includes a real address generation circuit 300 that generates a real address using an address conversion table in the main memory 3 when there is no real address corresponding to 00.

When the address translation buffer circuit 400 receives the real address from the real address generation circuit 300, it passes the obtained real address to the requested instruction or operand address translation buffer circuit 100 or 200.

Further, the address translation buffer circuit 400 includes a circuit that checks whether an address translation request for the same address has been received twice consecutively from the address translation buffer circuit 100 or 200, and the address translation buffer circuit 400 includes a circuit that checks whether an address translation request for the same address has been received twice in a row from the address translation buffer circuit 100 or 200. If there is, the corresponding address translation buffer circuit 100
Or, it passes real address data to the instruction or operand address translation buffer circuit 100 or 200 and instructs the address translation buffer to register the data.
The logical address/real address translation pair evicted from 0 is registered in the address translation buffer.

Instruction or operand address translation buffer circuit 1
00 or 200 reads the real address data held in the address translation buffer in which new data should be registered when receiving two consecutive address translation requests for the same address from the address translation buffer circuit 400, and performs address translation. The data is sent to the buffer 7 circuit 400 to register new logical/real address conversion pair data.

Figure 2 shows the instruction address translation buffer circuit 1 in Figure 1.
00, operand address conversion buffer circuit 200,
This is the detailed S cause of the real address generation circuit 300 and address translation buffer circuit 400.

The instruction address translation buffer circuit 100 includes a virtual address register 110, an address translation buffer 120 that holds virtual address information and corresponding real address information, and a replacement register when registering a new entry in the address translation buffer 120. A control circuit 140;
LRU that holds information for the replacement algorithm
(Least Recently Llsed) Memory 1
30, a comparison circuit 150 that compares the virtual address of part of the virtual address register 110 and the read data of the address translation buffer 120, and a selector 160 that selects the read data from the address translation buffer 120 or the newly obtained real address. configured. The address translation buffer 120 has two levels, and new entries are added to the address translation buffer 120! I! The replacement algorithm when recording is LRU (Least Re
used).

The operand address translation buffer circuit 200 has the same configuration as the instruction address translation buffer circuit 100, and includes a virtual address register 210, an address translation buffer 220 that holds virtual address information and corresponding real address information in pairs, and an address translation buffer circuit 200 for address translation. a replacement control circuit 240 when registering a new entry in the buffer 220;
LRU that holds information for the replacement algorithm
The memory 230, a comparison circuit 250 that compares a part of the virtual address register 210 with the virtual address of the data read from the address translation buffer 220, and selects the data read from the address translation buffer 220 or the newly obtained real address. It is composed of a selector 260.

The real address generation circuit 300 converts the real address corresponding to the accessed virtual address into the instruction address translation buffer 1.
20, it is not registered in the operand address translation buffer 220, and the address translation buffer circuit 400
It operates when the virtual address is not registered in the address conversion table of the main memory 3 and generates a real address corresponding to the virtual address.

The address translation buffer circuit 400 includes a selector 410 that selects data from a virtual address register 110 for instructions and a virtual address register 210 for operands;
A virtual address register 430, a selector 420 that selects successive data from the instruction and operand address translation buffers 120 and 220, or the obtained real address data 302, a second address translation buffer 460, and a second address translation buffer 460. Write holding register 440 to address translation buffer 460, replacement control circuit 4AO when registering a new entry to address translation buffer 460
and L that holds information for the replacement algorithm.
RU memory 470, a comparison circuit 490 that compares a part of the virtual address register 430 with the virtual address of the read data from the second address translation buffer 460, and a real address generation circuit 300 for the read data from the address translation buffer 460. Real address generated by selector 4
a selector 4BO for selecting one of the real addresses of 45; a register 4CO for sending out the real address requested for the instruction and operand; and a register 4CO for the instruction and for checking whether the same address request is made twice in succession Registers 40A and 40B that hold virtual addresses for operands, selector 41A, comparison circuit 480, instruction register 40C that holds the obtained real address, register 40D for operand, and selector 44 for selecting real address data.
Consists of 5.

Next, the operation of this embodiment will be explained using FIG. 2.

If the request is from the operand fetching unit 2, the virtual address is taken into the virtual address register 210, the address translation buffer 220 is indexed, and it is checked whether a logical/real address translation pair is registered. If it is registered, the obtained real address is used as is and the process moves to the next operation.

Whether a logical/real address pair is registered or not is determined by the address translation buffer 220 as part of the virtual address register.
The read data and a further part of the virtual address register 210 are determined by a comparison circuit 250. If they match, it is registered, and if they do not match, it is unregistered, and is notified via a signal line 251.

In this embodiment, the address translation buffer 22 (12 levels) is included, and comparison is also performed for 2 levels at the same time.
A translation pair of real addresses is always registered in one level or is in an unregistered state.

An LRU control method is adopted in which which level of the two-level address conversion buffer to register is determined by read data from the replacement control circuit 240 and the LRU memory 230 that holds information for the replacement algorithm. If the logical/real address translation pair is unregistered, it is sent from the operand address translation buffer circuit 200 to the address translation buffer circuit 400 via the signal line 251.
to notify. When the address translation buffer circuit 400 receives an unregistered notification, the selector 410 selects the virtual address register 210 for the operand, and at the same time, the selector 410 takes the contents of the virtual address into the register 430.
1A selects the register 40B holding the previously requested virtual address for the operand, and compares the two in the comparison circuit 480. Registers 40A and 40B have previously been used for instructions,
Operand address conversion buffer circuit 100°200
The virtual address requested from is retained. Further, the real addresses obtained at that time are held in registers 40C and 40D. As a result of address comparison in the comparison circuit 480,
If the addresses match, the contents of register 40D are selected by selector 445.4BO and taken into register 4CO, and the operand address conversion buffer circuit 2
Notify 00.

Address conversion back 7 circuit 2 for the notified operand
00, the logical/real address pair data of whichever level is removed based on the determination of the replacement control circuit 240 is read out from the address translation buffer 220, selected by the selector 260, and sent to the address translation buffer circuit 400. The real address held in the address translation buffer circuit 400 is taken into the ejected level and the logical/real address pair is stored. Writing to the address translation buffer 220 is performed from the output (logical address) of the register 210 and the output (actual address) of the register 4CO.

At the same time, the register 4CO is selected by the selector 260, and the obtained real address is used as it is to proceed to the next operation. On the other hand, the address translation buffer circuit 400 selects the logical/real address pair evicted from the operand address translation buffer circuit 200 by the selector 420, takes it into the register 440, and writes it into the address translation buffer 460.

The write level is determined by replacement control circuit 4AO.

If the result of the address comparison in the comparison circuit 480 is a mismatch, the address translation buffer circuit 400 indexes the address translation buffer 460 using the virtual address register 430 and checks whether a logical/real address translation pair is registered. .

The check is performed in the same way as the indexing of the address translation buffer 220 for operands, and a part of the virtual address is read out from the logical address part of the address translation buffer 460, and a comparison circuit 490 compares and determines whether it is part of the virtual address register 430 or not. If they match, it will be registered; if they do not match, it will be unregistered. When there is a mismatch, the real address generation circuit 3 is sent to the signal line 491.
00 will be notified.

In this embodiment, the address translation buffer 460 has two levels, and there is no problem even if the comparison is performed simultaneously for two levels or if it has a larger capacity. If it is registered in the address conversion buffer 460, the obtained real address is selected by the selector 4BO and taken into the register 4CO, and the signal @403 is sent to the operand address conversion buffer circuit 2.
Notify 00. At this time, the result of the comparison circuit 480 is also notified. The result of the comparison circuit 480 is used to determine whether or not to write the received real address into the operand address conversion buffer circuit 200.

At this time, the address translation buffer circuit 400 takes in the virtual address from the register 210 that holds the virtual address for the operand into the register 40B, and also takes in the real address data from the register 4CO into the register 40D.

When the operand address translation buffer circuit 200 is notified via the signal line 403 that there is a discrepancy in the result of address comparison and that the real address has been obtained, it does not write the obtained real address data to its own address translation buffer 220. Then, the selector 260 immediately selects the real address data from the register 4CO and moves on to the next operation.

The register 40B of the address translation buffer circuit 400 contains the virtual address accessed immediately before, and the register 40B contains the virtual address accessed immediately before.
A corresponding real address is prepared in 0D, making it possible to respond to the next request.

In the address translation buffer circuit 400, if the results of the address comparison in the comparison circuit 480 do not match and the address translation buffer 460 is further indexed and no logical/real address translation pair is registered, the signal line 401 is sent to the real address generation circuit 3.
Report to 00.

The real address generation circuit 300 is a virtual address register 43
With the content of 0, the content of the address translation pair table in the main storage device 3 is referred to to obtain the real address. Real address generation circuit 3
It is well known that 00 generates a real address by referring to a table in the main storage device 3, so a description thereof will be omitted. When the real address is obtained, it is notified to the address conversion buffer circuit 400 via the signal line 301. When the address translation buffer circuit 400 receives the notification, the selector 4BO
selects the real address data 302 and notifies the register 4CO through the take-in signal line 403 that the real address has been found. The operand address translation buffer circuit 200 that has received the notification is also notified of the result of the comparison circuit 480, so it does not write the real address data obtained as described above to its own address translation buffer circuit 220, but immediately selects the address data. At step 260, the real address data from the register 4CO is selected and the process moves to the next operation. The address translation buffer circuit 400 transfers the virtual address from the register 210 holding the virtual address for the operand to the register 40.
At the same time, the real address data is fetched from register 4CO to register 40D. Then, the selector 420 selects the logical address data 430 and the real address data from the register 4CO, respectively, and takes them into the register 440 and writes them into the address conversion buffer 460. The writing level is determined by replacement control circuit 4AO.

The operation from the operand address translation buffer circuit 200 has been described above, but the operation from the instruction address translation buffer circuit 100 is also similar to the operation from the operand register 40.
40A instead of B.

The operation is the same just by using 40C instead of 40D.

The instruction address translation buffer circuit 100 and the land address translation buffer circuit 200 operate simultaneously in parallel. When the address translation buffer circuit 400 receives requests from the instruction address translation buffer circuit 100 and the operand address translation buffer circuit 200 at the same time, it accepts and processes the request from either one, but in the embodiment, priority is given to the instruction side. It is prescribed that

[Effects of the Invention] As explained above, the present invention provides the first address translation buffer circuit with a real address generated by the real address generation circuit when there is no logical/real address translation pair to be obtained in the first address translation buffer circuit. When accessing, it is not registered in the first address translation buffer circuit, but is registered in the buffer and register in the second address translation buffer circuit that can be accessed in common, and then ejected when it is registered in the first address translation buffer circuit. The transformation pair ′! By registering in the address translation buffer circuit of J2, the first address translation buffer circuit is not used for only one address translation, and the first address translation buffer circuit is notified when the same access occurs continuously. 1! ! / By registering pairs of real addresses, the address translation buffer can be used effectively.
Furthermore, by having 1J2 address translation buffer circuits and accessing them in common, the generation time of logical/real addresses, which were generated for each individual request, can be shortened by accessing the second address translation buffer circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a detailed configuration diagram of a portion surrounded by a dashed line in FIG. DESCRIPTION OF SYMBOLS 1... Instruction fetch unit, 2... Operand fetch unit, 3-- Main memory device, 100... Instruction address conversion buffer circuit, 300
-Real address generation circuit, 400.-Address translation buffer circuit. 130.230,470-LRU me%, 140°240 4 A O-・Replace control circuit

Claims (1)

[Scope of Claims] 1. An information processing device that includes an address translation buffer that translates from a virtual address to a real address, and updates the contents of a replacement memory every time the address translation buffer is accessed so that the accessed data is the latest. A plurality of first registers record a certain fact, and if the required data does not exist in the address translation buffer, create a new real address from a virtual address and store it in the block to be evicted based on the read data of the replace memory. The first address translation buffer includes an address translation buffer circuit, a second address translation buffer circuit, and a real address generation circuit that indexes an address translation table in a main memory and generates a real address corresponding to a virtual address. If the logical address/real address translation pair corresponding to the virtual address is not registered in the address translation buffer, the circuit issues a real address generation request to the second address translation buffer circuit, and the same real address generation request is made a predetermined number of times in a row. When notified from the second address translation buffer circuit that the conversion has occurred, the logical address/real address translation pair at the level to be evicted from the address translation buffer is read out and sent to the second address translation buffer circuit. The logical address/real address pair is stored in the address translation buffer at the level at which the real address held in the address translation buffer circuit has been taken in and has been ejected, and the second address translation buffer circuit receives the real address from the first address translation buffer circuit. If the same real address generation request is made a predetermined number of times in succession, the real address is passed to the corresponding first address translation buffer circuit, and data registration instructions are given to the address translation buffer, and the corresponding first address translation buffer circuit The logical address/real address translation pair that has been kicked out of the circuit is registered in the own address translation buffer, and if the same real address generation request is not repeated a predetermined number of times, the own address translation buffer is indexed and the logical address/real address translation pair is registered. 1. An information processing apparatus, characterized in that the information processing apparatus checks whether the address is registered, and if it is not registered, generates a real address by a real address generation circuit and notifies the corresponding first address translation buffer circuit.