JPH0325794A - Memory control circuit - Google Patents
Memory control circuitInfo
- Publication number
- JPH0325794A JPH0325794A JP1161588A JP16158889A JPH0325794A JP H0325794 A JPH0325794 A JP H0325794A JP 1161588 A JP1161588 A JP 1161588A JP 16158889 A JP16158889 A JP 16158889A JP H0325794 A JPH0325794 A JP H0325794A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- voltage
- switching signal
- circuit
- voltage switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims abstract description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Power Sources (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はメモリ制御回路、特に、低電源電圧時データを
保持する機能を持つメモリを使用しているメモリ制御回
路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit, and particularly to a memory control circuit using a memory having a function of retaining data at low power supply voltage.
従来の低電源電圧時データを保持する機能を持つメモリ
の使用法としては第２図がある。FIG. 2 shows a conventional method of using a memory having the function of retaining data at low power supply voltages.
ここで１はＣＰＵであり、メモリ１０の読み書きの動作
をコントロールする。装置が動作状態の時は、４の電源
から５の＋５Ｖライン，３の電圧切換回路８のメモリ供
給電圧ラインを通って、メモリに＋５Ｖの電圧が供給さ
れる。Here, 1 is a CPU, which controls reading and writing operations of the memory 10. When the device is in operation, a +5V voltage is supplied to the memory from the power supply 4 through the +5V line 5 and the memory supply voltage line of the voltage switching circuit 8 3.
装置の電源が切れている時は９の電池から６の＋３ｖラ
イン，３の電圧切換回路８のメモリ供給電圧ラインを通
ってメモリに＋３ｖの電圧が供給される。When the device is powered off, +3V voltage is supplied from the battery 9 to the memory through the +3V line 6 and the memory supply voltage line of the voltage switching circuit 8 3.
この回路では、装置に電源が入っている時はメモリｌＯ
に常に＋５ｖの電圧が供給されている。In this circuit, when the device is powered on, the memory lO
is always supplied with +5V voltage.
また装置の電源が切れている時はメモリの内容を保持す
るために＋３Ｖの電圧が供給されている。Further, when the device is powered off, a voltage of +3V is supplied to maintain the contents of the memory.
上述した従来のメモリ制御回路は、装置の電源が入って
いる時は常にメモリに＋５Ｖが供給されているので、メ
モリの読み書きをしない時には無駄な電圧が供給されて
いることになる。In the above-mentioned conventional memory control circuit, +5V is always supplied to the memory when the device is powered on, so when the memory is not read or written, unnecessary voltage is supplied.
本発明の目的は無駄な電圧供給をおさえ、低消費電力の
メモリ制御回路を提供することにある。An object of the present invention is to provide a memory control circuit that suppresses unnecessary voltage supply and consumes low power.
本発明のメモリ制御回路は、電圧可変機能を有すること
により、メモリのデータを保持しかつ消費電力をおさえ
ることができる機能を有している。The memory control circuit of the present invention has a voltage variable function, so that it can hold memory data and reduce power consumption.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
１のＣＰＵからアドレスが出力されるが、そのアドレス
の値がメモリに割当てられているかを２の切換信号回路
で判断して、３の電圧切換回路に７の電圧切換信号を送
る。An address is output from the CPU No. 1, and the switching signal circuit No. 2 determines whether the address value is assigned to the memory, and the voltage switching signal No. 7 is sent to the voltage switching circuit No. 3.
電圧切換回路．３では電圧切換信号の値により、メモリ
動作時か非動作時のデータ保持かを判断して、８のメモ
リ供給電圧ラインに５の＋５Ｖラインを供給するか、６
の＋３Ｖラインを供給するかを切換える。Voltage switching circuit. In step 3, depending on the value of the voltage switching signal, it is determined whether data is to be retained during memory operation or non-operation, and whether the +5V line in step 5 is supplied to the memory supply voltage line in step 8, or whether the +5V line in step 6 is supplied to the memory supply voltage line in step 8.
Switch whether to supply the +3V line.
ここで４は７４源であり、＋５ｖと＋３Ｖの２種類の電
圧を出力する。Here, 4 is a 74 source, which outputs two types of voltages, +5V and +3V.
このように供給電圧を切換えることにより、装置が動作
状態の時でもメモリが非動作のデータ保持状態には、メ
モリへの供給電圧が小さくなり消費電力をおさえる効果
がある。By switching the supply voltage in this manner, even when the device is in the operating state, the voltage supplied to the memory is reduced when the memory is in the inactive data retention state, which has the effect of reducing power consumption.
以上説明したように本発明は、メモリ制御回路に電圧可
変機能を有することにより、メモリのデータを保持しか
つ消費電力をおさえる効果がある。As described above, the present invention has the effect of retaining memory data and reducing power consumption by providing the memory control circuit with a voltage variable function.
第１図は本発明の一実施例を示すブロック図、第２図は
従来の一例を示すブロック図である。
ｌ・・・・・・ＣＰＵ、２・・・・・・切換信号作戊回
路、３・・・・・・電圧切換回路、４・・・・・・電源
、５・・・・・・＋５Ｖライン、６・・・・・・＋３Ｖ
ライン、７・・・・・・電圧切換信号、８・・・・・・
メモリ供給電圧ライン、９・・・・・・電池。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1...CPU, 2...Switching signal generation circuit, 3...Voltage switching circuit, 4...Power supply, 5...+5V Line, 6...+3V
Line, 7... Voltage switching signal, 8...
Memory supply voltage line, 9...Battery.
Claims (1)
とによりメモリのデータを保持し、かつ消費電力をおさ
えることが出来ることを特徴とするメモリ制御回路。A memory control circuit, which is characterized in that it can hold memory data and reduce power consumption, especially by having a voltage variable function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1161588A JPH0325794A (en) | 1989-06-23 | 1989-06-23 | Memory control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1161588A JPH0325794A (en) | 1989-06-23 | 1989-06-23 | Memory control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0325794A true JPH0325794A (en) | 1991-02-04 |
Family
ID=15737986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1161588A Pending JPH0325794A (en) | 1989-06-23 | 1989-06-23 | Memory control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325794A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0675672A (en) * | 1992-05-29 | 1994-03-18 | Internatl Business Mach Corp <Ibm> | Method and system for controlling utilization of electric power |
-
1989
- 1989-06-23 JP JP1161588A patent/JPH0325794A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0675672A (en) * | 1992-05-29 | 1994-03-18 | Internatl Business Mach Corp <Ibm> | Method and system for controlling utilization of electric power |
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