JPH03260631A - Thin-film transistor matrix and production thereof - Google Patents

Abstract

PURPOSE:To obviate the generation of short circuiting in the intersected parts of bus lines by forming the 1st bus line as laminated films provided with upper and lower metallic films on and under a low-resistance metallic film consisting of metals contg. Al and forming a gate electrode of the single layer of the lower layer metallic film. CONSTITUTION:The 1st bus line B-1 formed by using the laminated films of the lower layer metallic film 21, the low-resistance metallic film 22 contg. the Al and the upper layer metallic film 23 and the gate electrode G consisting of the single layer of the lower layer metallic film 21 are formed on the surface of an insulating substrate 1 and the surfaces thereof are commonly coated with a gate insulating film 3. The lower layer metallic film 21 and the upper layer metallic film 23 are the films formed by using the metals selected from Ti, Cr, Ta, Co, Ni, Mo, Nb, W, TaIr. The metallic films which are not damaged even if the surfaces exposed together with the gate electrode G and the 1st bus line B-1 are exposed to plasma are formed and, therefore, the segregation and crystallization of the Al are prevented and the short circuiting between the upper and lower bus lines B-1 and B-2 is substantially prevented.

Description

[Detailed description of the invention]

[Overview] Regarding thin film transistor matrices and their manufacturing methods used in active matrix drive type liquid crystal display panels, etc., the A1 film or Al-Si alloy film formed on an insulating substrate is exposed to plasma in the subsequent process. For the purpose of preventing damage even when the substrate is exposed to heat, thin film transistors having gate electrodes formed on the surface of an insulating substrate are arranged in a matrix, and a plurality of striped first transistors are formed on the surface of the insulating substrate. bus lines are arranged in parallel, and the gate electrode and the first bus line are commonly covered with a predetermined insulating film.
The bus line consists of a low-resistance metal film made of a metal containing Al, and layers of Ti, Cr, Ta, Co, and Ni above and below it. consisting of a laminated film including a lower metal film and an upper metal film made of a metal selected from Mo, Nb, W, and TaIr, and the gate electrode is composed of a single layer of the lower metal film, Further, the manufacturing method includes, on the insulating substrate,
The lower metal film, the low resistance metal film, and the upper metal film are laminated in this order to form a laminated film, and then the exposed portion is removed using the resist film as a mask to form the first bus line and the upper metal film. A narrow gate electrode pattern is formed, and then an isotropic etching method is applied to the low-resistance metal film to side-etch the low-resistance metal film until the low-resistance metal film in the gate electrode portion is removed. The method includes forming a gate electrode made of the lower metal film and a first bus line made of the laminated film, and then removing the resist film. [Industrial Application Field] The present invention relates to a thin film transistor matrix used in an active matrix drive type liquid crystal display panel and a method for manufacturing the same. In a thin film transistor matrix structure used to drive an active matrix type display panel such as a liquid crystal display panel, a short circuit occurs between a gate bus line and a drain bus line, or between a gate bus line and a source bus line, which cross each other via an insulating layer. There is a demand for products that do not cause defects on the display screen. Therefore, there is a strong demand for preventing short circuit defects from occurring at intersections of lot lines. [Prior Art] An active matrix drive type liquid crystal display panel uses thin film transistors (TPTs) arranged in a matrix to correspond to individual pixels that perform dot display.
Each pixel has a memory function, making it possible to display multiple lines with good contrast. Such a liquid crystal display panel has, for example, a large number of gate bus lines and drain bus lines arranged in the X and Y directions, respectively, and a drive voltage is sequentially applied to each of these bus lines to control the intersection of each bus line. By selectively driving correspondingly arranged thin film transistors, a desired pixel is displayed as a dot. The structure of such a conventional thin film transistor matrix is shown in the plan view of FIG. 3(a) and the cross-sectional view of FIG.
- As shown in the cross-sectional view taken from arrow D], a gate bus line CAB and a drain bus line are formed by laminating, for example, a titanium (Ti) film 21 and an aluminum (Affi) film 22 on an insulating substrate 1 such as a glass substrate. For example, the line DB is connected to the gate insulating film 3 through an interlayer insulating film 6 which is a stack of a SiN film as the gate insulating film 3, an amorphous silicon film (a-3j film) as the active semiconductor layer 4, an SiO□ film as the protective WJ 5, etc. Both bus lines G
TFTs 8 are arranged in a matrix corresponding to each intersection of B and DB. The source electrode S of the TFT 8 is connected to the display electrode E, the gate electrode G to the gate bus line GB, and the drain electrode to the drain bus line DB. In addition, the drain bus line DB has a chromium (Cr) film 71 in the figure.
An example of a laminated structure of Aj2 film 72 and Aj2 film 72 is shown. [Problems to be Solved by the Invention] In the conventional thin film transistor matrix described above, as is well known, if a short circuit occurs between the bus lines at the intersection of a large number of gate bus lines CB and drain bus lines DB, In addition, line defects occur on the display screen, which is a fatal failure for the display panel. Short-circuit failures at these intersections are mainly caused by poor groundwork when forming bus lines, interlayer insulating layers, etc., pinholes in the glabella insulating layer, and the like. Such short-circuit faults occur when the lower bus line (third
In the example shown in the figure, after the gate bus line CB) is formed, the gate bus line is This is caused by deterioration of the interlayer insulating film due to segregation or crystallization of the metal forming the line GB. This phenomenon occurs particularly when A1, which is a low melting point metal, is used for the bus line on the substrate side. Even with these problems, AA has a low resistivity and can reduce resistance even if the bus line wiring is made thinner.As the board size increases, the bus line length increases, resulting in higher resistance. It is an extremely useful metal element because it allows the resistance of the bus line to remain low even as the bus line width decreases as the pixel size increases. Therefore, Al or A2 has traditionally been used in bus line wiring for LSIs, etc.
Generally, an alloy of silicon (Si) and silicon (Si) is used. In the manufacturing process of the TPT matrix, it is necessary to form a glabella insulating film on the bus line, and when forming this interlayer insulating film, plasma chemical vapor deposition (P-CVD) is used.
) method is used, and the Aj' film and A#-Si alloy film are subjected to plasma treatment in the previous process to form a two-layer insulating film, and the plasma and ambient temperature cause AN segregation or crystallization, resulting in lotus lines. causing a short circuit. The present invention provides AI! formed on an insulating substrate! Membranes and AI!
The purpose is to prevent the -Si alloy film from being damaged even if it is exposed to plasma in a subsequent process. [Means for Solving the Problems] The present invention will be explained below with reference to FIGS. As shown in FIG. 11+, (b), the thin film transistor of the present invention has a first bus line using a laminated film 2 consisting of a lower metal film 21, a low resistance metal film 22 containing Al, and an upper metal film 23. B-1 and a gate electrode G consisting of a single layer of the lower metal film 21 are formed on the surface of the insulating substrate 1, and a predetermined insulating film (gate insulating film 3 in the figure) is formed on the surface of the insulating substrate 1.
). -F The lower metal film 21 and the upper metal film 23 are made of Ti. The film is formed using a metal selected from Cr, Ta, Co, Ni, Mo, Nb, W, and TaIr. When manufacturing a thin film transistor having this configuration, a laminated film 2 is formed by laminating the lower metal film 21, the low resistance metal film 22, and the upper metal film 23 in this order on the insulating substrate 1, and then , removing the exposed portion using the resist film as a mask to form a pattern of the first bus line B-1 and a narrower gate electrode G, and then isotropically etching the low resistance metal film 22. By performing side etching of the low resistance metal film 22 until the low resistance metal film 22 at the 0 portion of the gate electrode is removed, the gate electrode G consisting of the lower metal film 21 and the three-layer laminated film 2 are removed. By forming a first bus line B-1 consisting of a first bus line B-1 and then removing the resist film, the exposed surfaces of both the gate electrode G and the first bus line B-1 are exposed to plasma. A metal film structure is formed that will not be damaged even when exposed to heat. After doing this, the subsequent steps are carried out to form the gate insulating film 3.
．． Operating semiconductor layer 4. Protection PIi! Further, a second bus line B-2 (the figure shows an example of a drain bus line) intersecting with the first bus line B-1 is formed. [Function] In the thin film transistor matrix of the present invention, the exposed surfaces of both the gate electrode G and the first bus line B-1 are metal films that are not easily damaged even when exposed to plasma. . Therefore, even if exposed to plasma during plasma ashing using oxygen (02) to remove the resist film or during the formation of the gate insulating film 3, etc. in the manufacturing process, the quality of Al2 will change due to segregation and crystallization. This prevents the upper and lower bus lines B-1. A short circuit between B-2 is less likely to occur. [Example] An example of the present invention will be described below with reference to FIG. 2 along with its manufacturing method. In this example, Ti/A 1
This is an example in which a three-layer gate bus is formed by laminating Ti films. In the same figure) -1 to (bL8 and (C) -
1 to (C)-8 are B-B of (a)-1 to (a)-8
FIG. 2 is a cross-sectional view of a main part shown in a cross-sectional view along arrows and a cross-sectional view in a CCC direction.

[Figure 2 fa) -1, 1bl-1, (CLI reference reference Ladrum rotation system) It has several targets and the substrate temperature is 20
Use a sputtering device that can raise the temperature to 0°C. 2
The materials of the two targets are Al on one side and Ti on the other side. First, the glass substrate 1 set in the sputtering apparatus is heated to about 200° C., the rotating drum is rotated at 6 revolutions/min, and Ti is first sputtered by DC sputtering in an Ar gas atmosphere with a pressure of about 0.001 Torr. A Ti film 1 having a thickness of about 80 nm is formed by sputtering. Next, the glass substrate 1 is cooled to room temperature, and the rotating drum 6 is
Rotate at rev/min and apply Ar at a pressure of about 0.001 Torr.
A by DC sputtering method in a gas atmosphere
A film 2 is formed to a thickness of about 80 nm. Furthermore, a Ti target was sputtered by a DC sputtering method in an Ar gas atmosphere with a pressure of about 0.001 Torr by rotating a rotating drum at 6 rotations/min at room temperature.
i) Form 1923 to a thickness of about 40 nm. On this Ti film 23, a resist film 18 having a pattern of a gate electrode with a width of 5 μm and a gate bus line with a width of 25 μm is formed. [See Figures (a)-2, (b)-2, and (C)-2] Using this resist film 8 as a mask, CCZ and gas paste active ion etching are performed to remove the Ti of the upper metal film.
The exposed portion of the membrane 23 is removed. Next, the exposed portion of the low-resistance Af film 2 is removed using a phosphoric acid-based etchant, and is formed in the same pattern as the Ti film 23 described above. Next, reactive ion etching is performed using a mixed gas of CC1, (95%) + 0□ (5%) to remove the exposed portion of the Ti film 1 of the lower metal film. Furthermore, by treatment with a phosphoric acid etchant, Af
Side etching of film formation 2 is performed. By controlling the amount of etching to about 3 μm from the side surface of the pattern, the A! Film 22 is completely removed. As a result, in the gate electrode portion, the upper Ti film 23 is also removed at the same time, leaving only the Ti film 1 as the lower metal film. Also, at this time, about 14 μm in the center of the gate bus line GB having a width of 25 μm is T i /A j! / T i
It is a three-layer laminated film 2 with a thickness of about 3 μm on each side.
The structure is such that the Ti film with a width of . After that, the resist film 8 used as the mask is removed. The substrate is then heated to approximately 300°C in an oxygen and nitrogen atmosphere.
By heating to generate plasma, the gate electrode G
The surface of the substrate is oxidized to form a TiO2 film with a thickness of about 20 nm. At this time, the gate electrode portion is exposed to strong plasma.

[Figure 18+-3, (see bl-3, fcL3]) Next, a SiN film (thickness: about 300 nm) was formed as a gate insulating film by P-CVD, and a was formed as an active half-layer.
-3i film (approximately 25 nm thick)4. 5in2 as a protective film
A film (about 140 nm thick) 5 is continuously formed. The SiN film 3 has a mixed gas atmosphere of SiH and NH.
The a-3i film 4 is formed in a SiH gas atmosphere, and the S i O2 film 5 is formed in a mixed gas atmosphere of S r H4 and N20. Conventionally, in this series of steps, 1. l or A1-3l
When the alloy film is exposed to plasma, it changes in quality, causing the problems described above. However, in this example, since the Al film 2 is not exposed, 81 may segregate and crystals may occur. No alteration occurs due to transformation. [See Figures (a)-4, (b)-4, and (C)-4] Next, the above SiO□)! ! 5, a resist film 9 is formed. This resist film 9 has a width that is wider by about 5 μm on both sides of the bus line at the gate path 94708 portion and narrower by about 1 μm at the gate electrode 0 portion, leaving a gap of about 5 μm between the gate electrode 0 portion and the gate path 94708 portion. The pattern shall be Using this resist film 9 as a mask, the exposed portion of the SiOz film 5 is selectively etched away using an ammonium fluoride-based etching solution.

[Refer to fal-5, (b)-5, and (C)-5 in the same figure] Si doped with PH3 while leaving this resist film 9.
n″a by P-CVD method in an atmosphere of H,
-3T film (approximately 50 nm thick) 10 is formed, and then T
i film (about 100nm in thickness is formed by vacuum evaporation method).

[See Figures (a)-6, (b)-6, and (C)-6] Dissolve the resist film 9 with acetone and
'a-3i film 10 and Ti film 1 are lifted off.

[See Figures (a)-7, (b)-7, and (C)-7] Next, a resist film (not shown) for forming source and drain electrodes is formed, and using this as a mask, CC1, ( 95
%)+0□ (5%) Perform reactive ion etching in a mixed gas atmosphere to form a Ti film 1. n
By removing the exposed portions of the a-3i film 10 and the a-3i film 4, element isolation is performed, and a source electrode S and a drain electrode are formed. Even after carrying out this step, the SiN film 3 of the gate insulating film remains
It will remain completely.

[Refer to (a)-8, (b)-8, and (C)-8 in the same figure] Next, the drain bus line (for example, a laminated film of Cr1l and Ti film, about 500 nm thick), DB, ITO film (thickness Approximately 2
00 nm) is formed, and the thin film transistor matrix according to this example is completed. In this embodiment described above, when the metal films constituting the gate electrodes and gate bus lines are exposed to plasma, the /l or Al5j alloy film, which is easily damaged, is covered with a Ti film, Therefore, there is no risk of Af segregation or crystallization, thus reducing short circuits at the intersection of two bus lines, improving the reliability and manufacturing yield of the thin film transistor matrix. [Effects of the Invention] As described above, according to the present invention, a highly reliable gate is provided in which a short circuit due to deterioration of the gate metal at the intersection of two bus lines is unlikely to occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of the configuration of the present invention, FIG. 2 is an explanatory diagram of the embodiments of the present invention, and FIG. 3 is an explanatory diagram of conventional problems. In the figure, 1 is an insulating substrate (glass substrate), 2 is a laminated film, 3 is a gate insulating film (SiN film), 4 is an active semiconductor layer (a-3l layer), 5 is a protective film (SiO! film), 6 is an insulating film between the eyebrows, 21 is a lower metal film (Ti film), 22 is a low resistance metal film (AilB!J), 23 is an upper metal film (Ti film)
, B-1 is the first bus line, B-2 is the second bus line, G is the gate electrode, GB is the gate bus line, D is the drain electrode, DB is the drain bus line, S is the source electrode, E indicates a display electrode. 1st figure f8-close l odor jt mouth month n mouth figure 3

Claims (2)

[Claims] (1) Gate electrode (G
) are arranged in a matrix, and a plurality of striped first bus lines (B-1) are arranged in parallel on the surface of the insulating substrate, and
In the thin film transistor matrix having a structure in which the gate electrode and the first bus line are commonly covered with a predetermined insulating film, the first bus line is a low resistance metal film (22) made of a metal containing Al. and Ti, Cr, Ta, and C above and below it.
A lower metal film (21) and an upper metal film (23) made of a metal selected from o, Ni, Mo, Nb, W, and TaIr.
1. A thin film transistor matrix comprising a laminated film (2) in which said gate electrode is made of a single layer of said lower metal film. (2) On the insulating substrate (1), the lower metal film (2
1), the low-resistance metal film (22) and the upper metal film (23) are laminated in this order to form a laminated film (2), and then the exposed portion is removed using the resist film as a mask, and the upper metal film (23) is laminated in this order. 1 bus line (B-1) and a narrower gate electrode (G) are formed, and then the low-resistance metal film is subjected to isotropic etching to side-etch the low-resistance metal film. is performed until the low resistance metal film of the gate electrode portion is removed, forming a gate electrode made of the lower layer metal film and a first bus line made of the laminated film, and then removing the resist film. A method for manufacturing a thin film transistor matrix, comprising: