JPH03260701A - Fa controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an FA controller having a means for communicating with external equipment such as R5232C, and is particularly intended to prevent malfunctions caused by instantaneous power outages.

(Prior Art) Fig. 6 is a hardware configuration diagram showing a conventional FA controller. In the figure, (1) is a transformer, (2)
is constant voltage circuit, (3) is CPII, (4) is ROM
, (5) is a RAM, and (6) is a communication control circuit with external equipment. Note that an interface with a display device, a hard disk, etc. are also connected, but their explanation will be omitted.

In the above configuration, an AC voltage supplied from an AC power supply (not shown) is converted to an isolated secondary voltage (for example, 30V) via a transformer (1), and the constant voltage circuit (2
) is done manually. The constant voltage circuit (2) generates a DC constant voltage (for example, DC5V) from the secondary voltage, and
Supplied as the power supply voltage for U (3) or communication control circuit (6).

The CPU (3) writes and reads data to and from the communication control circuit (6) and hard disk (not shown) according to predetermined procedures written in the ROM (4), thereby performing the function of an FA controller. . R
AM (5) is used for the purpose of temporarily storing data and temporarily saving calculation results, and the communication control circuit (6) is used for the purpose of temporarily storing data and temporarily saving calculation results. Communication with equipment (not shown) (e.g. R5232C, R
5422, etc.).

Here, if the external device has a function of outputting an ON/OFF signal of an AC signal, the CPU (3) outputs the ON/OFF signal of the external device via the communication control circuit (6). It takes a lot of manpower. That is, the above AC input is ON.
In this case, the CPU H) determines that it is ON by manually setting it to "1", for example. However, at this time, if a momentary power outage occurs in the AC power supply, the CPU (3)
0'' may be input and determined to be OFF.

Further, if the external device is a device having a serial communication function such as R5232C, the following operation is performed. Serial data sent from the external device is executed by the communication control circuit (6). When the communication control circuit (6) receives data, it generates an interrupt signal (not shown) and
Notify PU (3) and request it to read the received data. When the CPU (3) accepts the interrupt signal, it performs operations according to the flow described in FIG. 7, and as a result reads information from the external device.

That is, since a plurality of interrupt signals are normally connected to the CPU (3), the CPU (3) executes determination processing A (step Sl) to determine which block the interrupt signal is from.

Therefore, as a result of executing process A (step St), if it is determined that the communication control circuit (6) is the interrupt generation source, the process of determining whether the communication control circuit (6) is normal or not (
Step S2) is executed. As a result, if it is determined to be normal, process B (step S3) is executed and information from the external device is read; on the other hand, if it is determined to be abnormal, process C (step S5) is executed, (:RT
(not shown), etc., displays a communication error. Here, there are various types of communication errors, such as communication errors due to overflow of data, errors with unknown causes such as noise, and errors due to instantaneous power outages.

(Problems to be Solved by the Invention) Conventional FA controllers are configured as described above, so when a momentary power outage occurs in the AC power supply, incorrect input may occur, and furthermore, the problem that should occur due to the momentary power outage may occur. Despite the error, an error display similar to that of an unknown phenomenon such as noise is displayed, resulting in problems such as prolonging system stoppage due to the error.

This invention was made to solve the above-mentioned problems, and provides an FA that can prevent malfunctions caused by instantaneous power outages, and can also easily restore the system by determining the cause of the error caused by instantaneous power outages. The aim is to get a controller.

(Means for Solving the Problems) The FA controller according to the present invention includes at least a CPU
, a program storage memory, a calculation work memory,
F having an external device communication control circuit that communicates with external devices
In the A controller, a momentary power failure detection circuit detects a momentary power failure of the supplied AC power; a momentary power failure memory circuit stores the instantaneous power failure signal output from the instantaneous power failure detection circuit for a certain period of time; It is provided as an interrupt input of the CPII and has an interruption processing means for interrupting the operation of the CPU, and a status reading circuit that inputs the instantaneous power failure memory signal outputted from the instantaneous power failure memory circuit and the instantaneous power failure signal. be.

In addition, in the FA controller, a CPU restart processing means that stops the above-mentioned interruption processing means immediately after the instantaneous power outage is restored and restarts the above-mentioned processing of the CPt1, and a CPU restart processing means that stops the above-mentioned interruption processing means immediately after the instantaneous power outage is restored, and a and an instantaneous power outage error determination processing means that determines that the error cause is an instantaneous power outage based on the instantaneous power outage signal and the instantaneous power outage storage signal.

[Effect]

In this invention, the operation of the CPU is interrupted based on the instantaneous power outage signal to prevent erroneous calculations due to erroneous input signals, and the cause of the error caused by the instantaneous power outage is determined based on the instantaneous power outage storage signal.

(Embodiment) Hereinafter, an embodiment of the present invention will be described based on FIG. 1, in which the same parts as in FIG. 6 are denoted by the same reference numerals. In FIG. 1, (7) is a momentary power failure detection circuit that detects a momentary power failure, (8) is a momentary power failure memory circuit that stores the instantaneous power failure signal (10) for a certain period of time, and (9) is the momentary power failure signal (10). lO
) and the instantaneous power outage memory signal (11) outputted from the instantaneous power outage memory circuit (8). , shapers (81), (82), diodes (83), and resistors (84).

(85) and a capacitor (86), the detection delay time t, is determined by the parallel resistance of the resistor (84) and the resistor (85), and the charging time of the capacitor (86), and the recovery time t4 is determined by the charging time of the resistor (86). 85) and the discharge time of the capacitor (86).

Next, the operation will be explained. A case will be explained in which the external device connected to the communication control circuit (6) has a function of outputting an ON/OFF signal of an AC signal.

CPt1 (3) converts the 0N10FF signal from the external device to “1” or “0” via the communication control circuit (6).
It is read as a signal and judged as ON/OFF.
This is the same as the conventional example. However, at this time, if a momentary power outage occurs in the AC power supply (not shown), that is, even though the AC input of the external device is ON, the output of the external device becomes "0" due to the momentary power outage. (Therefore, the above CPLI (3) should be determined to be OFF),
The instantaneous power failure detection circuit (7) detects this and activates the instantaneous power failure signal (10). This instantaneous power outage signal (1
0) becomes an interrupt input to CPII (3), which causes CPII (3) to execute an interrupt process predetermined in ROM (4).

Here, as shown in FIG. 4, the interruption process merely executes the processing program "Is there a momentary power outage?", so the input information from the external device is not read out. In other words, erroneous inputs caused by instantaneous power outages will not be read.

Next, when the instantaneous power outage returns, the instantaneous power outage detection circuit (7) deactivates the instantaneous power outage signal (10), and the CPU (3) therefore resumes the interrupted work, e.g. Read information from the above external device. However, the information input from the external device is outputting a normal signal because the instantaneous power outage has been restored, and the information input from the external device is outputting a normal signal.
PII (3) will continue normal operation. Here, a "normal signal" means that even though the AC input of the external device is ON, the output is "0" (O
This means that there is no abnormal state such as FF), and erroneous input can be prevented.

Also, a case will be described in which the external device is a device having a serial communication function such as R5232C. However, since the basic operation is the same as that of the conventional example, it will be omitted, and the case where a momentary power outage occurs will be explained below. That is, a case will be described in which a momentary power outage occurs while the CPU (3) is receiving data from the external device. The above CPU (
3) is a step Sl) in which the interrupt signal generation source is determined in the interrupt processing program shown in FIG.
If it is determined to be normal in the judgment (step S2), the process BJ (step S3) is being executed, and if an instantaneous power outage occurs at this time, the instantaneous power outage detection circuit (7) Activate the power outage signal (lO),
The CPU (3) executes relay processing (see FIG. 4) that is predetermined in the ROM (4). That is,
The above-mentioned "interruption processing" merely executes the processing program "Is there a momentary power outage?". At this time, data is sent from the external device asynchronously with the interruption process of the CPU (3), so when the next data is received, the communication control circuit (6) has a built-in buffer(
(not shown). However, the buffer normally has a data capacity of only 1 to 2 bytes, so if the instantaneous power outage continues,
The buffer becomes overloaded with data and enters an error state.

Next, a case will be described in which the instantaneous power outage is restored in this state. That is, the instantaneous power failure detection circuit (7) deactivates the instantaneous power failure signal (10), so that the CPt1 (3) is released from the interruption process and resumes the work it was doing before the interruption.

Since the interrupt signal received during a momentary power outage is normally held, the CPU (3) executes the interrupt process shown in FIG. 5 and accesses the communication control circuit (6). At this time, as described above, since the communication control circuit (6) is in an error state, an error process is executed in step S2 of the interrupt processing program. Furthermore, in step S4, a processing program for determining whether there was an instantaneous power outage is executed. In step S4, specifically, the instantaneous power outage signal (lO) and the instantaneous power outage storage signal (11) are read out from the status reading circuit (9), thereby making it possible to determine whether or not there is a momentary power outage.

Here, the instantaneous power failure storage signal (11) will be explained. When a momentary power failure occurs, the momentary power failure detection circuit (7)
) makes the momentary power outage signal (10) active. FIG. 3 shows the time chart, and in the figure, the delay time t1 is the detection delay time caused by the instantaneous power failure detection circuit (7). Since the instantaneous power outage signal (10) is manually input to the instantaneous power outage storage circuit (8), the instantaneous power outage storage signal (11) becomes active later than the instantaneous power outage signal (10). In the figure, t3 is the instantaneous power failure memory signal (1
1), which is the detection delay time caused by the instantaneous power failure storage circuit (8).

Next, when the instantaneous power outage returns, the instantaneous power outage signal (10
) returns after a delay time t2. Here, t2 is the recovery delay time caused by the instantaneous power failure detection circuit (7). Further, the restoration of the instantaneous power outage signal (lO) causes the instantaneous power outage storage signal (11) to return to the inactive state, but the restoration time t4 is longer than the instantaneous power outage storage circuit (8).
) at a certain time. Specifically, the interrupt processing program shown in FIG. 5 is executed, and the recovery time t4 is set to be longer than the processing time up to "Is there an instantaneous power outage?" (step 54).

Therefore, the CPU (3) is in states B and C in Figure 3.
The interruption process (see Figure 4) is executed at Therefore, step S4 is executed.

Here, the CPU (3) reads from the status reading circuit (9) that the instantaneous power outage signal (lO) is at H level and the instantaneous power outage memory signal (11) is at L level, and ), it can be seen that there was a momentary power outage. Then, in process D (step S6), the operator or external equipment is informed that an error has occurred due to a momentary power outage, and the process ends.

For reference, when the above operator or external device learns that an error has occurred due to a momentary power outage, they will communicate again (in the past, the cause of the error was unknown, so it took time to investigate the cause. ).

Naturally, in step S4 of FIG. 5, if the error is not due to a momentary power outage, then process
5) is executed, the operator or external device is informed of the owner, and the process is completed.

The error factors here are the same as the conventional error factors, excluding the error factor due to instantaneous power outage.

In addition, in process D (step 5fi) of FIG. 5, the occurrence of an error due to a momentary power outage is notified to an external operator via a display means such as a CRT (not shown), indicating that a communication error has occurred due to a momentary power outage. However, in the process D (step S6) of FIG. 5, instead of displaying the information on the display means, it is possible to request the external device to communicate again. It is also possible to communicate. Here, since the means for displaying certain information on a CRT or the like and the means for requesting communication from an external device are generally known, their explanation will be omitted.

In the above embodiment, the instantaneous power outage signal and the instantaneous power outage signal have been described as being low active, but it goes without saying that the same effect can be achieved even if they are high active.

Furthermore, although an embodiment of the instantaneous power failure memory circuit has been described with reference to FIG. 2, it goes without saying that the same effect can be obtained even if the circuit is constructed using a knot element, an AND gate element, or the like.

Further, in FIG. 2, the charging time and discharging time are set to be different times depending on the diode, but it goes without saying that there is no problem even if the same 08 time constant is used.

Furthermore, although a capacitor is used to store the instantaneous power outage state, it may be stored using other elements, such as a flip-flop, or it may be stored in a RAM or the like through software processing. Needless to say, it is effective.

(Effects of the Invention) As described above, according to the present invention, during momentary power outage, the CP
Since u is in an unprocessed state, AC input from the outside is not erroneously inputted manually, and a highly reliable system can be constructed.

Furthermore, it is possible to determine the cause of errors caused by momentary power outages.
This has the effect of making it easier to recover the system because it is easier to identify errors in data received from the outside.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an FA controller showing an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of the instantaneous power failure memory circuit of FIG. 1, and FIG. 3 is a schematic diagram for explaining the invention. Output waveform diagrams, Figures 4 and 5 are flowcharts of interruption processing and interrupt processing in the event of a momentary power outage in the present invention, and Figures 6 and 7 are block diagrams of a conventional FA controller and interrupt processing in the event of a momentary power outage. This is a flowchart including In the figure, (1) is a transformer, (2) is a constant voltage circuit,
(3) is CPU, (4) is ROM, (5) is RAM
, (6) is a communication control circuit, (7) is a momentary power failure detection circuit,
(8) is a momentary power failure memory, (9) is a status readout circuit, (lO
) is a momentary power failure signal, and (11) is a momentary power failure memory signal. The same reference numerals in the figures indicate the same or corresponding parts. Figure 5 5

Claims (2)

[Claims] (1) Momentary power outage that detects a momentary power outage of the supplied AC power in an FA controller that has at least a CPU, a memory for storing programs, a memory for calculation work, and an external device communication control circuit that communicates with external devices. a detection circuit; an instantaneous power failure memory circuit that stores the instantaneous power failure signal output from the instantaneous power failure detection circuit for a certain period of time; and an interruption process that interrupts the operation of the CPU by giving the instantaneous power failure signal as an interrupt input to the CPU. and a state reading circuit that inputs the instantaneous power failure storage signal outputted from the instantaneous power failure storage circuit and the instantaneous power failure signal.
controller. (2) In the FA controller according to claim 1, there is provided a CPU restart processing means for suspending the interruption processing means immediately after the instantaneous power outage is restored and restarting the above processing of the CPU, and before and after the instantaneous power outage When an error occurs, the present invention is characterized by having an error cause search processing means for searching for the cause of the error, and an instantaneous power failure error determination processing means for determining that the cause of the error is an instantaneous power failure based on the instantaneous power failure signal and the instantaneous power failure memory signal. FA controller.