JPH03260751A - 32-bit input/output device control method for 16-bit bus processor - Google Patents

Abstract

PURPOSE:To realize inexpensive constitution for the title method by providing a control signal generating part, a higher rank data control part, and a data selection part and performing the writing operations twice to a 32-bit I/O via a 16-bit bus CPU. CONSTITUTION:A control signal generating part 8 is provided together with a higher rank data control part 5, and a data selection part 6. Then a 16-bit bus CPU 3 performs the writing operations twice to a 32-bit I/O 1 and also performs the reading operations twice to the I/O 1. When a writing operation is applied to a memory 4 from the I/O 1, 32 bits are written all at once. Then the CPU 3 reads the 32 bits at one time out of the memory 4. Therefore the data equivalent to 32 bits can be outputted at one time when the I/O 1 outputs the data received from the CPU 3 in two times to the outside. Then the DMA transfer is carried out to the memory 4 in 32 bits when the data received from outside are given to the CPU 3. Thus the CPU 3 performs its processing at the highest speed. Then the cost can be reduced in such a state where the CPU 3 does not need so fast processing although the I/O 1 needs the high-speed processing.

Description

[Detailed Description of the Invention] (Summary) 32 bits of a 16-bit bus processor (hereinafter referred to as CPU)
Bit input/output device control (hereinafter referred to as 32-bit I10)
Regarding the method, high-speed processing is required for Ilo, but if high-speed processing is not required for the CPU, a 16-bit bus CPU is used instead of the 32-bit CPU0 to control the 32-bit CPU 110 to reduce the cost. For the purpose of providing a 32-bit I10 control method for a 16-bit CPU when
J, memory, connected to the first terminal of the upper data control unit that controls the data of the upper 16 bits of the data bus, and one input side of the data selection unit that selects and outputs data input from two input sides. The upper 16-bit data bus is connected to the second terminal of the upper data control unit and the other input side of the data selection unit, and the 16-bit data bus on the output side of the data selection unit is connected to the second terminal of the upper data control unit and the other input side of the data selection unit. A signal connected to the memory and indicating the first or second time from the 16-bit bus CPU, a read signal, a write signal, and the 32-bit bus) Il
The configuration includes a control signal generation section that receives a write signal of o and generates and outputs a control signal to the upper data control section and the data selection section.

[Industrial Application Field] The present invention provides a communication unit that performs high-speed communication of, for example, 10 Mbps, with a 32-bit input/output device (hereinafter referred to as 32-bit I1).
0), and the processor side for this is a device that does not require that high speed, and in order to reduce the cost, a 16-bit bus CPU is used instead of a 32-bit CPU to control the 32-bit I10. 32 bins of 16-bit hash CPtJ) I10 control method.

[Prior Art] FIG. 3 is a diagram showing the configuration of a conventional 32-bit computer system.

In a conventional computer system, in the case of a 32-bit CPU 20, a 32-bit bus 1021 and a memory 22 are connected to a 32-bit bus to enable faster processing than in a 16-bit computer system.

Note that the I1021 has a normal DMA transfer function.

[Problem to be solved by the invention]

However, although high-speed processing is required for Ilo, even if high-speed processing is not required for the CPU,
In conventional computer systems, the CPU.

Since both Ilo and Ilo use 32 bits, there is a problem that they are expensive.

The present invention requires high-speed processing as Ilo, but C
As for the PU, if high-speed processing is not required, in order to reduce the cost, a 16-bit bus CPU is used instead of the 32-bit CPU0 to control the 32-bit I10.
The purpose of this invention is to provide a 32-pin 110 control method for a 6-bit bus CPU.

[Means for solving problems] FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, the data bus 2 of the lower 16 bits of the 32-bit l101 is connected to the 16-bit bus CPU3. Memory 4. The first terminal of the upper data control unit 5 that controls the data of the upper 16 bits of the data bus 7, and the data selection unit 6 that selects and outputs data input from two input sides.
The upper 16 bit data bus 7 is connected to the second terminal of the upper data control section 5 and the other input side of the data selection section 6. 16-bit data bus 9 on the output side of
is connected to the memory 4, and a signal indicating the first or second time from the 16-bit bus CPU 3, a read, a write signal, and the 32-bit
A control signal generating section 8 receives a write signal of 101 and generates and outputs a control signal to the upper data control section 5 and the data selection section 6.
When writing to the 2-bit l101, for the first time, data is transmitted from the data bus 2 of the lower 16 bits, and a signal indicating the first time and a write signal are sent to the control signal generation section 8, and the control signal generation section 8 sends the data to the control signal generation section 8. The unit 8 sends a signal to the upper data control unit 5 to send it at the time of the second write, and causes the lower 16 bits of the data sent from the data bus 2 to be fetched. 16-bit data bus 2
2 to the control signal generating section 8.
The control signal generation unit 8 sends a second write signal to the upper data control unit 5, and the data from the data bus 2 of the lower 16 bits that is being fetched for the first time is sent. is transmitted from the data bus 7 of the upper 16 bits to write 32 bits, and when reading from the 32 bits) 1101, the data bus 2 of the lower 16 bits and the data bus 7 of the upper 16 bits are transmitted.
Of the data read from the lower 16 bits of the data bus 2, the data read from the data bus 2 is read for the first time, and at this time, a signal indicating the first time and a read signal are sent to the control signal generation unit 8 to generate the control signal. The unit 8 sends a signal to the higher-order data control unit 5 to send it at the time of the second reading, and once the data read from the data bus 7 of the upper 16 bits is taken in, and at the time of the second read, the control A signal indicating the second time and a read signal are sent to the signal generation section 8, and the control signal generation section 8 sends the signal to the upper data control section 5.
A second read signal is sent, and the data from the data bus 7 of the upper 16 bits that has been taken in is transferred to the lower 16 bits.
Transmit and read from Bint's data bus 2, and read the 32
When writing directly to the memory 4 from bit 101, the lower 16 bits of data from the data bus 2 are sent and written to the memory 4, and at this time a write signal is sent to the control signal generator 8 to generate the control signal. The upper 16 bits of data from the data bus 7 are selected by the data selection unit 6 from the unit 8, and written to be sent to the memory 4 via the data bus 9 on the output side. When reading from the memory 4, the data is read via the data bus 2 of the lower 16 bits.

[Operation] According to the present invention, writing from the 16-bit bus CPU 3 to the 32-bit bus 101 is performed twice.

That is, for the first time, data is transmitted from the data bus 2 of the lower 16 bits, and a signal indicating the first time and a write signal are sent to the control signal generation section 8, and the control signal generation section 8 transmits data to the upper 16 bits. Sends a signal to the data control unit 5 to send it at the time of the second write, and causes the data sent from the data bus 2 of the lower 16 bits to be fetched. Sending data from the data bus 2 to cause it to be written, and sending a signal indicating the second time and a write signal to the control signal generation unit 8;
The control signal generation unit 8 sends a second write signal to the upper data control unit 5, and the data from the lower 16 bits data bus 2 that has been taken in for the first time is transferred from the upper 16 bits data bus 7. Transmit it and write a total of 32 bits.

When reading from the 32-bit data 101, the 16-bit CPU 3 reads the data twice.

That is, the data bus 2 of the lower 16 bits and the upper 16 bits
Among the data read from the bint data bus 7, the data read from the data bus 2 of the lower 16 bits is 1.
At this time, a signal indicating the first reading and a read signal are sent to the control signal generating section 8, and the control signal generating section 8
sends a signal to the higher-order data control unit 5 to send it at the time of the second reading, causes the data read from the data bus 7 of the upper 16 bits to be taken in, and generates the control signal at the time of the second reading. Sending a signal indicating the second reading and a read signal to the unit 8, causing the control signal generating unit 8 to send a second reading signal to the upper data control unit 5;
The fetched data from the data bus 7 of the upper 16 bits is transmitted and read from the data bus 2 of the lower 16 bits.

When writing directly to the memory 4 from the 32 bits 101, 32 bits are written at once.

That is, the lower 16 bits of data from the data bus 2 are sent and written to the memory 4, at this time a write signal is sent to the control signal generator 8, and the control signal generator 8 sends the upper data to the data selector 6. Data from the 16-bit data bus 7 is selected and sent to the memory 4 via the data bus 9 on the output side for writing.

When the 8 to 16-bit nominal CPU 3 sells S from the memory 4, the data bus 2 of the lower 16 bits is used.
32 bits are read out twice. Therefore, from the 32-bit l101, the 16-bit bus CPU3
When outputting 32-bit data sent twice to the outside, 32 bits can be output at once, and when passing external data to the 16-bit bus CPU3, 32-bit data is transferred to memory 4 by DMA. and 16-bit bus CPU3
Since it performs extremely high-speed processing, Ilo requires high-speed processing, but if the CPU does not require such high-speed processing, it can be constructed at low cost.

(Example) FIG. 2 is a block diagram of an embodiment of the invention.

In FIG. 2, the address is sent via the address bus 10, so a description of the address will be omitted below.

In FIG. 2, when writing from the 16-bit CPU 3 to the 32-bit 1101, the writing is performed in two write cycles.

For the first time, data is transmitted from the data bus 2 of the lower 16 bits, and the signal A1 indicating the first or second time is set to 0 to indicate the first time, and the write signal W is set to 1 to write the data. The control signal generation unit 8 sends a signal to the upper data control unit 5 to send it at the time of the second write, and the data bus 2 of the lower 16 bits is
When writing for the second time, data bus 2 of the lower 16 bits is loaded.
At the same time, the control signal generation unit 8 sets A1 to 1 to indicate the second time, sets the write signal W to 1 to indicate writing, and the control signal generation unit 8 sends data to the upper data control unit 5. A second write signal is sent, and the data from the lower 16 bits of the data bus 2 that has been fetched for the first time is transmitted from the upper 16 bits of the data bus 7, so that a total of 32 bits are written.

When the 16-bit bus CPU3 reads from the 32-bit l101, the data is read in two read cycles.

At the first time, the lower 16 bits of data bus 2 and the upper 1
32-bit data is read from the 6-bit data bus 7.

Among the read data, the data read from the lower 16 bits of data bus 2 is read the first time, and at this time,
A signal A1 indicating the first or second time is sent to the control signal generation unit 8.
is set to 0 to indicate the first time, the read signal R is set to 1 to indicate reading, and the upper data control unit 5 is output from the control signal generation unit 8.
A signal is sent to the data bus 7 for the second reading, and the data read from the data bus 7 of the upper 16 bits is temporarily taken in.

When reading for the second time, A1 is set to 1 to indicate the second reading to the control signal generating section 8, read signal R is set to 1 to indicate reading, and the control signal generating section 8 sends the second reading to the upper data control section 5. Top 1 that sends and captures signals
Data from the 6-bit data bus 7 is transmitted and read from the lower 16-bit data bus 2.

Next, the case of DMA transfer from the 32-bit l101 to the memory 4 will be explained.

In this case, first, the priority request signal HOLD is set to 1 from the 32-bit l101 to the 16-bit bus CPtJ3. Then, the 16-bit bus CPU3 sends a signal HO to pass priority.
Pass priority with LDA as 1. then 32 bit l
101 performs DMA transfer to the memory 4.

In the case of Figure 2, the 9U area is divided into 4 parts (32 bits of memory 4), so that writing can be done in byte units, and the 16-bit bus CPU 3 can read from the area in byte units. The byte enable BE specifies whether to write to or read from the SN area (0 to 31 bits), the 0 to 15 bit area, or the 16 to 31 bit area.

Note that A1 of 32 bits l101 is a signal indicating which data bus side is to be selected by the data selection section 6. When it is 0, the data bus 7 side of the upper 16 bits is selected, and when it is 1, the lower 16 bits are selected. Indicates that the 16-bit data bus 2 side is to be selected.

First, the case of DMA transfer to the 0 to 31 bit area of the memory 4 will be explained.

Byte enable BE is a signal specifying the 0 to 31 bit area, A1 is set to O, the control signal generation section 8 specifies the 0 to 31 bit area for the memory 4, and the upper 16 bits are sent to the data selection section 6. - Input a signal to select the data bus 7 side of the client, and send 32-bit data from the data bus 7 of the upper 16 bits and the data bus 2 of the lower 16 bits.

Then, the lower 16 bits of data from the data bus 2 are written to the memory 4, and the higher 16 bits of data from the data bus 7 are written to the memory 4 via the data bus 9.

When reading from the 16-bit bus CPU3, the byte enable BE is set to the 0 to 15 bit area or 16 to 31 bits, for example.
The read signal R is set to 1 as a signal specifying the Pitsu HI region.

Then, the control signal generation unit 8 outputs 0 to 15 to the memory 4.
Specify the Pitsu H1 area or the 16 to 31 bit TiN area and read it via the data bus 2 of the lower 16 bits.

When writing to the 0 to 7 bit area and the 0 to 15 bit area of the memory 4 from the 32 bit l101, use the byte enable BE as a signal indicating this and set AI to 1.
The control signal generator 8 sends the lower 16 data to the data selector 6.
A signal for selecting the data bus 2 side of the bits is output, and the signals from the data bus 2 of the lower 16 bits/7 bits are input to the memory 4 via the data selection section 6 and the data bus 9, and are input to the control signal generation section. 8 is written to the specified area.

When writing to the 16 to 31 bit area or the 16 to 23 bit HJf area of the memory 4, the byte enable BE is used as a signal to indicate this, and when A1 is set to 0, the control signal generation unit 8 sends a signal to the data selection unit 6. , a signal for selecting the data bus 7 side of the upper 16 bits is output, and the signal from the data bus 7 of the upper 16 bits is input to the memory 4 and written to the area specified by the control signal generation unit 8.

When reading byte by byte from the 16-bit hash CPU3, the hide enable BE is set to 0 to 7 bit area, 8 to 7 bit area.
15-bit area, 16-23 bit eM area, 24-31
It may be read out as a signal specifying each bit area.

In this way, when outputting the 32-bit data sent twice from the 16-bit Hass CPU 3 to the outside, 32-bit ■ 101 can output 32 bits at a time, and the data from the outside can be transferred to 16-bit data. When passing it to the bus CPU3, it performs 32-bit DMA transfer to the memory 4, and performs the highest possible high-speed processing as a 16-bit bus CPU3.
Although Ilo requires high-speed processing, if the CPU does not require such high-speed processing, it can be configured at low cost.

(Effect of the invention) As explained in detail above, according to the present invention, 32 bisito
101, when outputting the 32-bit data sent twice from the 16-bit bus CPU3 to the outside, 32 bits can be output at once, and when passing the data from the outside to the 16-bit bus CPU3, the 32-bit data can be outputted at once. DM to memory 4 with bits
It performs A transfer and performs extremely high-speed processing as a 16-bit Has CPU3, so high-speed processing is required as Ilo, but as a CPU, if such high-speed processing is not required, it has the effect of being able to be configured at a low cost. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention. 1.21 is a 32-bit input/output device, 2 is the lower 16 bit data bus, 3 is a 16-bit bus processor, 4.22 is memory, 5 is a higher-level data control unit; 6 is a data selection section; 7 is the upper 16 bit data bus, 8 is a control signal generation unit; 9 is a data bus, 10 is the address bus, 20 indicates a 32-bit processor.

Claims (1)

[Claims] The lower 16-bit data bus (2) of the 32-bit input/output device (1) is connected to the 16-bit bus processor (3), the memory (4), and the upper 16-bit data bus (7). Upper data control unit that controls data (
5) and one input side of a data selection unit (6) that selects and outputs data input from two input sides, and the data bus (7) of the upper 16 bits is connected to
a 16-bit data bus (9) connected to the second terminal of the upper data control section (5) and the other input side of the data selection section (6), and on the output side of the data selection section (6); is connected to the memory (4) and inputs a signal indicating the first or second time, read, and write signals from the 16-bit bus processor (3) and a write signal from the 32-bit input/output device (1). and the upper data control unit (5
) and a control signal generator (8) that generates and outputs a control signal to the data selector (6), and when writing from the 16-bit bus processor (3) to the 32-bit input/output device (1), For the first time, data is transmitted from the data bus (2) of the lower 16 bits, and a signal indicating the first time and a write signal are sent to the control signal generation section (8), and the control signal generation section (8) Then, the upper data control unit (5) imports 2
At the time of the second write, a signal to send is sent and the data sent from the data bus (2) of the lower 16 bits is taken in, and at the time of the second write, the data bus (2) of the lower 16 bits is sent.
2) transmits data from the control signal generator (
A signal indicating the second time and a write signal are sent to 8), and the control signal generation unit (8) sends the second
The data from the lower 16 bits of the data bus (2) that has been captured for the first time is transmitted from the upper 16 bits of the data bus (7) by sending the write signal for the 3rd time.
When writing bit data and reading it from the 32-bit input/output device (1), the 32-bit data read from the lower 16-bit data bus (2) and the upper 16-bit data bus (7) , the data read from the lower 16 bit data bus (2) is read for the first time, and at this time, a signal indicating the first time and a read signal are sent to the control signal generation section (8),
The upper data control unit (5) from the control signal generation unit (8)
A signal is sent to the control signal generation section (8) to cause the data read from the data bus (7) of the upper 16 bits to be taken in once for the second reading. A signal indicating the second reading and a read signal are sent, and the control signal generating section (8) sends the second reading signal to the upper data control section (5), and the upper 16 bits of the data bus ( 7) is transmitted and read from the data bus (2) of the lower 16 bits, and when writing directly to the memory (4) from the 32-bit input/output device (1), the data of the lower 16 bits is read. Bus (2)
The next data is sent and written to the memory (4), at this time a write signal is sent to the control signal generation section (8), and the upper 16 bits are sent from the control signal generation section (8) to the data selection section (6). selects data from the data bus (7) and sends it to the memory (4) via the data bus (9) on the output side and writes the data, and the 16-bit bus processor (3) writes the data to the memory (4). When reading from the data bus (2) of the lower 16 bits,
1. A method for controlling a 32-bit input/output device for a 16-bit bus processor, characterized in that reading is performed via a 16-bit bus processor.