JPH03260774A - Mask data production system - Google Patents
Mask data production systemInfo
- Publication number
- JPH03260774A JPH03260774A JP2059170A JP5917090A JPH03260774A JP H03260774 A JPH03260774 A JP H03260774A JP 2059170 A JP2059170 A JP 2059170A JP 5917090 A JP5917090 A JP 5917090A JP H03260774 A JPH03260774 A JP H03260774A
- Authority
- JP
- Japan
- Prior art keywords
- area
- gnd
- pattern
- wiring
- designated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子機器に使用されるプリント基板(以下PW
Bと記す)またはセラミック基板のマスクデータ作成方
式に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a printed circuit board (hereinafter referred to as PW) used in electronic equipment.
(denoted as B) or a mask data creation method for a ceramic substrate.
従来のこの種のマスクデータノイズガード用GNDベタ
パターンはその外郭線をそのまま指定して作成している
。A conventional GND solid pattern for mask data noise guard of this type is created by specifying its outline as is.
上述した従来のマスクデータ作成方式ではGNDベタパ
ターンの外郭線を指定しなくてはならず、部品ビンやヴ
イアホール等のルスーホールランドとの逃げ領域及び他
の配線パターンとの逃げ領域の外郭線の人手指定が煩雑
という欠点があった。In the conventional mask data creation method described above, it is necessary to specify the outline of the GND solid pattern, and the outline of the escape area with loose hole lands such as component bins and via holes, and the escape area with other wiring patterns. The disadvantage was that the manual designation of personnel was complicated.
本発明の方式は、プリント基板やセラミック基板のマス
クデータ作成方式において、
所要のA領域を確保する手段と、
前記A領域内の配線の中で別のパターンから雑音保護を
したい配線を指定する手段と、前記A領域内でGND接
続しない部品ビン,ヴィアホール等の接続スルーホール
ランド部を指定する手段と、
前記指定された配線と前記指定した接続スルーホールラ
ンドに対し、一定のクリアランス値でB領域を確保する
手段と、
前記A領域から前記B領域を差し引いた領域をGNDベ
タパターン領域とし、その外郭線をトレースする手段と
、
前記GNDベタパターン領域をぬりつぶし用太幅パター
ンでぬりつぶす手段とを有する事を特徴とする。The method of the present invention is a mask data creation method for a printed circuit board or a ceramic board, and includes a means for securing a required area A, and a means for specifying a wiring for which noise protection is desired from another pattern among the wiring within the area A. and a means for specifying connection through-hole lands such as component bins and via holes that are not connected to GND within the A area, and B with a constant clearance value for the specified wiring and the specified connection through-hole land. means for securing an area; means for setting an area obtained by subtracting the B area from the A area as a GND solid pattern area and tracing its outline; and means for filling the GND solid pattern area with a thick pattern for coloring. It is characterized by having.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明のフローチャートであり、各処理の内容
は以下のようである。FIG. 1 is a flowchart of the present invention, and the contents of each process are as follows.
処理1・・・所要の領域を第2図のように設定し領域A
とする。Processing 1...Set the required area as shown in Figure 2 and select area A.
shall be.
処理2・・・領域A内の配線の中でGNDベタパターン
を用いて別のパターンから雑音保護したい配線を指定す
る。第3図にその例を示す。Process 2: A GND solid pattern is used among the wiring in area A to designate the wiring to be protected from noise from another pattern. An example is shown in FIG.
処理3・・・領域A内でGND接続しない部品ビン、V
IA等の接続スルーホールランド部を指定する。Processing 3: Parts bin, V that is not connected to GND in area A
Specify the connection through-hole land portion of IA, etc.
処理4・・・処理2で指定された配線と処理3で指定さ
れた接続スルーホールランドに対し、一定のクリアラン
ス値で領域を確保する。この領域を領域Bとする。第4
図に領域Bの例を示す。Process 4: Secure an area with a constant clearance value for the wiring specified in Process 2 and the connection through-hole land specified in Process 3. This area will be referred to as area B. Fourth
An example of region B is shown in the figure.
処理5・・・領域Aから領域Bを差し引いた領域をGN
Dベタパターン領域とし、その外郭線をトレースする。Process 5: GN the area obtained by subtracting area B from area A
Set it as the D solid pattern area and trace its outline.
第5図に得られたGNDベタパターン領域の例を示す。FIG. 5 shows an example of the obtained GND solid pattern area.
処理6・・・処理5で得たGNDベタパターン領域をぬ
りつぶし用太幅パターンでぬりつぶす。Process 6: Fill in the GND solid pattern area obtained in Process 5 with a thick pattern for filling.
処理7・・・GNDベタパターン領域を他にも作成する
ならば処理1へ戻り、作成しないならば処理8へ進む。Processing 7: If another GND solid pattern area is to be created, the process returns to Processing 1; if not, the process proceeds to Processing 8.
処理8・・・GNDベタパターン領域を外部ファイルへ
出力する。Process 8: Output the GND solid pattern area to an external file.
以上の処理を行い、GNDベタパターン領域を得る。第
6図は本処理実行後のマスクパターンの例である。The above processing is performed to obtain a GND solid pattern area. FIG. 6 is an example of a mask pattern after execution of this process.
以上説明した様に本発明は、GND領域の指定。 As explained above, the present invention can specify the GND area.
雑音保護したい配線の指定および特定スルーホールの指
定をすることにより雑音保護用GNDベタパターンを半
自動で作成することができる。By specifying the wiring to be protected against noise and specifying a specific through hole, a GND solid pattern for noise protection can be created semi-automatically.
第1図は本発明のフローチャート、第2図は領域Aを設
定した例を示す図、第3図は別のパターンから雑音保護
をしたい配線の例を示す図、第4図は領域Bを設定した
例を示す図、第5図は得られたGNDベタパターン領域
の例を示す図、第6図は本発明処理後のマスクパターン
の例を示す図である。Figure 1 is a flowchart of the present invention, Figure 2 is a diagram showing an example of setting area A, Figure 3 is a diagram showing an example of wiring for which noise protection is desired from another pattern, and Figure 4 is setting area B. FIG. 5 is a diagram showing an example of the obtained GND solid pattern area, and FIG. 6 is a diagram showing an example of the mask pattern after the process of the present invention.
Claims (1)
式において、 所要のA領域を確保する手段と、 前記A領域内の配線の中で別のパターンから雑音保護を
したい配線を指定する手段と、 前記A領域内でGND接続しない部品ピン,ヴィアホー
ル等の接続スルーホールランド部を指定する手段と、 前記指定された配線と前記指定した接続スルーホールラ
ンドに対し、一定のクリアランス値でB領域を確保する
手段と、 前記A領域から前記B領域を差し引いた領域をGNDベ
タパターン領域とし、その外郭線をトレースする手段と
、 前記GNDベタパターン領域をぬりつぶし用太幅パター
ンでぬりつぶす手段とを有する事を特徴とするマスクデ
ータ作成方式。[Scope of Claims] In a mask data creation method for a printed circuit board or a ceramic board, means for securing a required area A, and means for specifying a wiring for which noise protection is desired from another pattern among the wiring within the area A. and means for specifying connection through-hole lands such as component pins and via holes that are not connected to GND in the A area, and B with a constant clearance value for the specified wiring and the specified connection through-hole lands. means for securing an area; means for setting an area obtained by subtracting the B area from the A area as a GND solid pattern area and tracing its outline; and means for filling the GND solid pattern area with a thick pattern for coloring. A mask data creation method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059170A JPH03260774A (en) | 1990-03-09 | 1990-03-09 | Mask data production system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059170A JPH03260774A (en) | 1990-03-09 | 1990-03-09 | Mask data production system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03260774A true JPH03260774A (en) | 1991-11-20 |
Family
ID=13105639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2059170A Pending JPH03260774A (en) | 1990-03-09 | 1990-03-09 | Mask data production system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03260774A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63108466A (en) * | 1986-10-27 | 1988-05-13 | Fujitsu Ltd | Computer aided design system |
-
1990
- 1990-03-09 JP JP2059170A patent/JPH03260774A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63108466A (en) * | 1986-10-27 | 1988-05-13 | Fujitsu Ltd | Computer aided design system |
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