JPH03260850A - Data writing system for cache memory - Google Patents

Abstract

PURPOSE:To improve the cache hit rate in a main memory read state by writing the writing data into a cache memory as long as a matched state of tags is secured, a 1st valid bit and a write zone bit are set respectively even with no cache hit in a memory write state. CONSTITUTION:An access is applied to a directory memory 1 with an address signal 101 serving as a cache memory address to a main memory address. A comparator 5 compares the outputted data 104 with an address signal 106 serving as a tag part of the main memory address. When the coincidence is secured between the tag part and the data 104 in a memory write state with a block valid bit set respectively, the cache memory writing function is realized as long as a write zone bit is set even if a line valid bit is reset. Thus the cache hit rate is improved in a main memory read state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a cache memory data write method used in an information processing device equipped with a cache memory.

(Prior Art) Conventionally, cache memory mechanisms used in information processing devices do not use a block load method in which all data for one block of cache memory is transferred from main memory when a read miss occurs; A conventional cache memory operation in which only one word for an address is loaded from main memory will be described below.

In explaining this operation, the relationship between memory addresses and cache row addresses is shown in FIG. Here, it is assumed that a memory address is attached to each byte, and one word of memory access is composed of 4 bytes. Furthermore, one block of the cache memory is assumed to have four words, and addresses MA and CA in the figure are assumed to be addresses on a 16-byte boundary.

Therefore, for the cache memory, data from address MA to MA+CI becomes the same block and has the same tag data (MA).

First of all, Figure 3(a) shows the operation when a read mishit occurs.
Explain with reference to. In FIG. 3, P is the central processing unit (hereinafter referred to as processor), CA is the cache memory, MM is the main memory, MA is the main memory address, and CA is the main memory address.
indicates a cache memory address, ■ indicates a block valid bit (valid bit for the entire block), and LV indicates a line valid bit (valid bit for the corresponding word in the block).

When the processor P starts reading the memory using the main memory address MA, the tag part of the cache memory CM addressed by the cache memory address CA is compared with the tag data (MA), and initially they do not match. A read request is then issued to the main memory MM, one word of the data at the memory address MA is read out, and this data is set in the read buffer in the processor P and the address corresponding to the address CA in the cache memory CM.

At the same time, tag data (
MA) is set, and the block valid bit V and line valid bit LV corresponding to address CA are set (set to 11).

Next, the operation at the time of memory write using the memory address (MA+4H) will be explained with reference to FIG. 3(b).

When processor P starts writing memory, address C
A+4) Since the line valid bit LA of the cache memory CM for 1 is not set (because it is "0°"), a character miss hit occurs and data is written only to the main memory MM.At this time, H
Considering the case where all the zone bits representing the effective data portion in units of 1 byte are set, the write data sent from the processor P is written to the main memory MM as is.

When this write data is read out, it becomes as shown in FIG. 3(C).

That is, since the line valid bit LV of the CA+411 section of the cache memory CM is not set (the third
(see figure (b)), read the data from the main memory MM without setting it in the cache, and set this data in the processor P and cache memory CM in the same way as above,
Set line valid bit LV of CA+4H section of cache memory CM.

As mentioned above, conventionally, even if the tag part of the cache memory CM matches and the block valid bit v is set, if the line valid bit LV is not set, even if all the write zones are set, Since no cache write is performed, it is necessary to access the main memory MM when reading data from the same address again, which poses a problem in that the effectiveness of the cache memory is impaired.

(Problem to be solved by the invention) Conventionally, as shown in FIG. 3(b), cache memory C
Although the tag part of M matches and the block valid bit V is set, the line valid bit LV is not set, so the cache write is not performed even though all the write zones are set. , when reading data from the same address again, it is necessary to access the main memory MM, which is one factor that reduces the effectiveness of the cache memory.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a cache memory data write method that can improve the hit rate of a cache memory between a central processing unit and a main memory in an information processing device.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a method in which all write zone bits are set when writing to the main memory in an access mechanism section between a processing device having a cache memory and the main memory. a circuit that detects a tag match, a block valid bit set, and a line valid bit reset for the write address; and a circuit that outputs a cache memory write signal based on the output of the circuit. At the time of memory write, if the tag part of the address matches and the block valid bit is set, even if the line valid bit is reset, if the write zone bit is set, a cache memory write is executed. do. As a result, even if the main memory is not completely cached when writing to the main memory, the cache write can be performed depending on the cache directory, the state of valid bits, and the conditions of the write zone, and therefore the cache hit rate when reading the main memory can be improved.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of essential parts in an embodiment of the present invention.

In Figure 1, l is R constituting the directory memory.
AM (hereinafter referred to as directory memory), and the tag part TA of the memory address is used as a cache directory.
Hold G. The address 101 supplied to the directory memory 1 is address data without the lower 4 bits of the address CA part shown in FIG. Reference numeral 2 denotes a RAM (hereinafter referred to as block valid bit memory section) constituting a block valid bit memory section, which holds block valid bits V. The block valid pit memory section 2 is supplied with the same address 101 as the directory memory 1 (that is, the directory memory 1 is also supplied with 1 data for 16 byte addresses, like the block valid pit memory section 2). 3 and 4
are buffer gates, which are enabled for output by a signal 103 that becomes active when writing to the directory memory 1 and the block valid pit memory section 2, and output rewritten data for the directory memory 1 and the block valid pit memory section 2. 5 is a comparator and a directory memory! The output data 104 of the main memory address is compared with the lower part (10B) of the main memory address, and when a match is found, the output 113 is activated. Gates 6 and 7 perform a logical product of the write zone signals 108 to Ill and the memory write data sending timing signal 112, and activate the condition signal 102 supplied to the gate 11. Reference numeral 8 denotes a gate which performs the logical product of tag matching and block valid bit setting at the time of memory access, and activates the condition signal 114 supplied to gate 11. 9 is a RAM (hereinafter referred to as line valid bit memory section) that constitutes a line valid bit memory section; , hold ■. The address signal 115 supplied to the line valid pit memory section 9 is an address CA shown in FIG.
This is address data without the lower two bits of the part. Reference numeral 10 denotes a buffer gate, and its output is enabled by a signal l18 that becomes active when writing to the line valid pit memory section 9.
Output the rewritten data. 11, the output signal 114 of gate 8 and the output signal 102 of gate 7 are active,
This is a gate that performs a logical product of the fact that the output 117 of the line valid pit memory section 9 is inactive, and makes the output 119 active. 12 is the output 119 of It, and other cache memory write signals 1
21, 122, etc., and makes the output 120 active. Reference numeral 13 denotes a RAM (hereinafter referred to as cache word memory) constituting a cache word memory, which enters a write enable state when the output 120 of the gate 12 becomes active, and bus data 123 is written therein. The cache word memory 13 is supplied with the same address 115 as the line valid pit memory section 9 (that is, the line valid pit memory section 9 is also supplied with one data for a 4-byte address like the cache word memory 13).

FIGS. 2(a) to 2(e) are diagrams for explaining the operation of the above embodiment, respectively, in which P is a central processing unit (hereinafter referred to as a processor), CA is a cache memory, and MM
is main memory, MA is main memory address, CA is cache memory address, ■ is block valid bit, LV
indicates a line valid bit.

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 and 2.

First, the operation of reading one word due to a read miss will be explained with reference to FIG. 2(a).

Directory memory l is accessed by address signal 101 which is cache memory address CA for main memory address MA, and comparator 5 compares the output tag data 104 with address signal 108 which is the tag part (MA) of main memory address MA. do. Since no match has been found yet, one word of data is loaded from main memory MM to processor P via bus 123, and one word of data is loaded to cache word memory 13 addressed by address signal 115. and control signal 103
8 is activated, the tag data (MA) is written to the directory memory l via the signal line 104, the block valid bit VL of the block valid bit memory section 2 is set, and the line valid bit of the line valid pit memory section 9 is set. A bit corresponding to the word read from main memory MM is set in LV.

Next, FIG. 1(b) shows a case where the main memory address M A +4 II is subsequently written to the memory with all zone bits set.

For this memory address MA+4H, the output 104 of the directory memory l and the tag part (MA) of the address match, and the output 10 of the block valid pit memory part 2
Since gate 5 is active, the output 114 of gate (AND gate) 8 becomes active. Also, there is a timing signal 112 in which the data at the time of memory write becomes valid on the bus 123, and signals 108 to 111 representing zone bits.
Since all of the gates become active, the output of the gate (AND gate) 6.7 becomes active. In addition, since the line valid bit 117 for address MA+4H (CA+4H) is inactive, the outputs of the gate (AND gate) and the gate (OR gate) 12 are made active, and data is written to the main memory MM at the same time as the cache word memory 13. Write write data to. Then, with signal 11g active, address MA+41
1 Set the line valid bit LV for (CA+411).

Next, what happens when main memory address M A + 81+ is written without all zone bits being set is shown in Figure 1 (c
).

In this case, as explained in the previous example, the conditions such as tag matching and block valid bits are met, but the signals 108 to 111 representing zone bits are not all active, so the cache word memory 13 is No data is written, and data is written only to the main memory MM.

FIG. 1(d) shows the case where the memory is then read at the main memory address MA+4H.

Here, since the cache hits the address output from the processor P, data is read from the cache word memory 13 without accessing the main memory MM.

FIG. 1(e) shows the case where main memory MM address MA+811 is read. This operation is performed when line valid bit 1. Since V is not set, a read mishit operation will occur.

In this way, when writing memory, if the tag part of the address matches and the block valid bit V is set, even if the line valid bit LV is reset, if the write zone bit is set, the cache memory write will be executed. By realizing the function to execute main memory read, cache write can be performed depending on the state of cache directory and valid pits and write zone conditions even if the cache has not been completely cached at the time of main memory write. The catch rate will be improved.

[Effects of the Invention] As described in detail above, according to the present invention, when a cache read miss occurs, block loading is not performed, only one word corresponding to the read address is read from the main memory, and the CPU
and writes it to the cache memory, writes the tag to the cache directory as control information, and sets the first valid bit of the entire block and the second valid bit for the corresponding word in the block, and when writing through the memory. In a cache memory in which data is written using zone bits that indicate valid data in one word, there is a circuit that checks the zone bit at the time of memory write, a tag match for the write address, the setting of the first valid bit, and the second valid bit. It has a circuit that detects a bit reset and a circuit that outputs a cache memory write signal based on the detection output of the circuit, and when writing to memory, the tags match and the first valid bit is set even without a cache hit. , and if the write zone bit is set, the write data is written to the cache memory, so the main memory write n
Even if cache data is not completely cached to the cache, depending on the state of the cache directory and valid bits and the conditions of the write zone, cache write is possible, thereby improving the cache hit rate when reading from the main memory.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of essential parts in an embodiment of the present invention, Figures 2 (a) to (e) are diagrams for explaining the operation of the above embodiment, and Figure 3 ( a) to (c)
4 are diagrams for explaining memory access operations in the prior art, and FIG. 4 is a diagram showing the relationship between memory addresses and cache row addresses. l...RAM (directory memory) 2...R
AM (block valid bit memory section), 3゜4,
IO...Buffer gate, 5...Comparator, 6,7゜8.1■...Gate (AND gate), 9...RA
M (line valid bit memory section), 12...gate (OR gate), 13...RAM (cache word memory), P...central processing bag R (processor)
, CA...cache memory, MM...main memory,
MA...Main memory address, CA...Cache memory address, ■...Block valid bit, Lv
...Line valid bit.

Claims (1)

[Claims] When a cache read miss hits, block loading is not performed, only one word for the read address is read from main memory and written to the CPU and cache memory, and a tag is written to the cache directory as control information.
A cache that uses a method of setting the first valid bit of the entire block and the second valid bit of the corresponding word in the block, and writes data using a zone bit indicating valid data in one word during memory write-through. In the memory, there is a circuit that checks the zone bit at the time of memory write, a circuit that detects the tag match for the write address, the setting of the first valid bit, and the reset of the second valid bit, and the detection output of the circuit detects the cache memory. It is equipped with a circuit that outputs a write signal, and when writing to memory, even if there is no cache hit, if the tag matches, the first valid bit is set, and the write zone bit is set, the write data is written to the cache memory. A cache memory data write method characterized by writing.