JPH03260859A - Trace data recording system for inter-cpu communication - Google Patents

Abstract

PURPOSE:To easily isolate a fault occurrence area by using the data equal to that sent onto a bus as the trace data and leaving this trace data in a transmission system RAM. CONSTITUTION:The input side of a 2nd interface 60 is connected to the output side of a 1st interface 40 and the output side of the interface 60 is connected to a 2nd storage 50. When a CPU 11 performs the inter-CPU communication to a reception system 2, a direct memory access controller DMAC 31 sends the data on a 1st storage 20 to a bus via the interface 40 with an instruction of the CPU 11. Under such conditions, the interface 60 fetches the data equal to that sent to the bus via the output side of the interface 40 and writes it into the storage 50. Thus it is possible to keep the data equal to that sent to the system 2 as the trace data and then to effectively isolate a fault occurrence area.

Description

[Detailed Description of the Invention] [Summary] Regarding a trace data recording method for tracing the contents of a bus when a communication failure occurs between CPUs, it is possible to efficiently isolate the location where the failure occurs when a failure occurs in communication between CPUs. The purpose is to provide a trace data recording method for inter-CPU communication that can write the same data sent to the other CPU into its own storage device in order to perform data processing and inter-CPU communication. a first storage device that stores data; a direct memory access controller that sends data in the first storage device to a receiving system; a first interface that interfaces with the receiving system; and a first storage device that writes data to be sent. 2
In a transmission system consisting of a storage device, a second interface is provided for writing the same data transmitted to the reception system into the second storage device, and the data of the first storage device transmitted by the direct memory access controller is The data is configured to be input from the output side of the first interface to the second interface and written to the second storage device.

As devices become faster and more multifunctional, high-speed processing by CPUs is required.

For this purpose, we aim to increase speed by using multiple CPUs, but there are cases where the same data is required between these multiple CPUs. It has data of.

When a failure occurs during communication between such CPUs,
In order to know which CPU caused the failure, it is necessary to efficiently isolate the failure location, and a recording method is required that writes the same data sent to the other system as trace data to the storage device. There is.

[Industrial application field]

The present invention relates to a trace data recording method for tracing the contents of a bus when a communication failure occurs between CPUs.

With the recent development of communication equipment and electronic equipment, CP is widely used.
[Prior Art] FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating transmitted and received data in the conventional example.

The conventional transmitting system IA shown in FIG.
A random access memory (hereinafter referred to as RAM) 21 stores data to be sent to A, and a direct memory access controller (hereinafter referred to as D
(referred to as MAC) 31, a communication LSI 41A that interfaces with the reception system 2, and a RAM 51 that writes the transmission data in the RAM 21. The reception system 2A has the same configuration as the transmission system IA, and has a CPU 12, It is composed of RAM22, DMA C32, communication LSI 42A, and RAM52.

In this configuration, the communication LSIs 41A and 42A are connected through one transmission channel and one reception channel, respectively.

FIG. 5 shows the transmitted and received data in the conventional example shown in FIG. (3) is the data written to the RAM 51 by the receiving system in the communication LS
This is the received data written to the RAM 52 via the I 42A, and is the communication LSI 41 in the transmission system I.
Assume that data garbled occurs in A.

[Problem to be solved by the invention]

In the conventional example described above, even when data is garbled due to a malfunction of the communication LSI 41A, the CPU
Since the correct contents of RAM 21 written by II have been written, trace data indicating that processing was performed normally remains in RAM 51 even though a bug occurred on the sending system IA side.

The present invention provides communication between CPUs that can write the same data sent to the other CPU in its own storage device in order to efficiently isolate the location of the failure when a failure occurs. The purpose is to provide a continuous race data recording method.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the principle of this initiation.

1 in the principle block diagram of the present invention shown in FIG. 1 is a diagram for explaining a transmission system, 11 in the figure is a CPU that performs data processing and communication between CPUs, and 20 is a CPU II
31 is a direct memory access controller that is connected to the CPU 11 and transmits data in the first storage device 20 to the receiving system 2 according to instructions from the CPU II. It is.

Further, 40 is a first interface that is connected to the receiving system 2 and serves as an interface, 50 is a second storage device into which the transmitted data is written, and 60 is a second storage device which writes the same data transmitted to the receiving system 2. Second storage device 5
A second interface connected to the output side of the first interface 40 for writing to zero.

When the CPU II performs inter-CPU communication with the receiving system 2, it takes in the data of the first storage device 20 transmitted by the direct memory access controller 31 from the output side of the first interface 40 to the second interface 60, This problem is solved by configuring the data to be written to the second storage device 50.

[For production]

The input side of the second interface 60 is connected to the output side of the first interface 40, and the output side is connected to the second storage device 50.

In this configuration, the CPU II communicates with the receiving system 2 via the CP
When performing inter-U communication, the DMAC 31 sends the data in the first storage means 20 onto the bus via the first interface 40 according to instructions from the CPU II.

At this time, the second interface 60 takes in the same data sent out on the bus via the output side of the first interface 40 and writes it to the second storage device 50, thereby transmitting it to the receiving system 2. It becomes possible to leave the same data as trace data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating transmitted and received data in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the invention shown in FIG. 2 consists of a transmitting system 11 and a receiving system 2.

The transmission system 1 includes a CPU II that performs data processing and communication between CPUs, a DMAC 31 that transmits data to the other CPU 12, a RAM 21 as the first storage device explained in FIG. interface 40 and second interface 6
0, this is an example of a communication LSI 41 having two built-in transmitting and receiving channels.

The receiving system 2 also has the same configuration as the transmitting system 1, and C
PU12, RAM22, DMAC32, communication LSI4
2. Consists of RAM 52.

The communication LSI 41 converts parallel data into serial data, sets a communication partner according to instructions from the CPU II, and has two built-in transmission and reception channels.

The transmission channel of this communication LSI 41 is connected to the reception channel, and when performing communication between CPUs,
II, by setting the receiving destination to RAM 51 and receiving system 2 and transmitting data, it is possible to leave the same data sent on the bus as trace data in RAM 51, and when a bug occurs, By comparing the data received by the receiving system 2 with the trace data, it becomes easy to identify the location where the failure has occurred.

In FIG. 2, 1 is a transmitting system and 2 is a receiving system, but since l and 2 have the same configuration, it goes without saying that l can be a receiving system and 2 can be a transmitting system.

Figure 3 shows an example of transmitted and received data, where (1) is the transmitted data, (2) is the trace data written to the RAM 51, and (
3) is the reception data received by the reception system 2 and written into the RAM 52, and is the data received by the communication LSI 41 of the transmission system 1.
When garbled data occurs in the data, the trace data in (2) and the received data in (3) match, but they do not match the transmitted data (1). Therefore, a bug has occurred on the transmitting system l side, and if you further compare and analyze the contents of the transmitted data and trace data, you will find that the Dθ bit is missing. , the location of the failure can be easily identified.

[Effects of the Invention] According to the present invention as described above, the same data sent on the bus is stored in the RAM of the transmission system as trace data.
Therefore, when a bug occurs in inter-CPU communication, we have developed a trace data recording method for inter-CPU communication that allows you to easily isolate the location of the failure by comparing the trace data with the received data. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining transmitted and received data in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. FIG. 5 is a block diagram explaining an example, and FIG. 5 is a diagram explaining transmitted and received data in a conventional example. In the figure, LIA is a transmitting system, 2.2A is a receiving system, 1112 is a CPU, 20 is a first storage device, and 21, 22, 51, and 52 are RAMs. 31.32 is a DMAC1, 40 is a first interface, 41.42.41A and 42A are communication LSIs, 50 is a second storage device, and 60 is a second interface. Figure 1: Block diagram explaining the present invention in detail Figure 4: Block diagram explaining the conventional example Figure 4: (1) Transmission data (2) Trace data (3) Reception data Figure 5

Claims (1)

[Claims] A data recording method for tracing the contents of a bus in the event of an inter-CPU communication failure, comprising: a CPU (11) that performs data processing and inter-CPU communication;
a first storage device (20) storing transmission data;
The data in the first storage device (20) is received by a system (
2) a direct memory access controller (31) for transmitting data to the receiving system (2); a first interface (40) for interfacing with the receiving system (2); and a second storage device (50) for writing transmission data. In (1), a second interface (60) is provided for writing the same data transmitted to the receiving system (2) into the second storage device (50), and the CPU (11) System (2) and CP
When performing inter-U communication, the direct memory access controller (31) sends the first storage device (
20) to the first interface (40).
A trace data recording method for inter-CPU communication, characterized in that the data is captured from the output side of the CPU to the second interface (60), and the data is written to the second storage device (50).