JPH0326085A - Reception clock regenerating system - Google Patents

Abstract

PURPOSE:To obtain a stable reception clock with little jitter by performing phase comparison with a PLL circuit by using output corresponding to a center zero cross point i one cycle of an amplitude phase modulation signal after discriminating connection polarity. CONSTITUTION:The system is equipped with an amplitude limiting amplifier 30 to convert the amplitude phase modulation signal with data clock frequency to a logic level signal, a zero cross detection circuit 26 to generate the output at the rise and fall of the logic level signal, a window gate circuit 31 to select the passage of either the output corresponding to the center zero cross point in one cycle of the amplitude phase modulation signal or all the output out of the output of the zero cross detection circuit 26, and a PLL circuit 32 to compare the output of the zero cross detection circuit 26 in the neighborhood of the frequency of integer times the clock frequency or in the neighborhood of the same frequency synchronizing with the switching of the window gate circuit 31. The reception clock is generated by detecting the center zero cross point in one cycle of the amplitude phase modulation signal after the connection polarity is discriminated. In such a way, the stable reception clock with little jitter can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception clock recovery method for an amplitude phase modulation signal.

[Prior art]

An example of a communication device in which data is transmitted using such an amplitude-phase modulated signal is a still picture videophone.

This type of videophone is being put into practical use as a TTC standard videophone, and is described in detail in, for example, "Television Technology, September 1988 issue, pages 19 to 27." FIG. 1 is a diagram showing the structure of a videophone signal when transmitting a still image, and the signal is roughly divided into three parts: a videophone identification signal 11, control information 12, and image information 13.

The identification signal 11 called DT signal is 2 0 0 6 H
This is a two-frequency signal of Z and 1633 Hz, which is sent up to 400 milliseconds before the control information 12, and is used to switch the receiving device from the voice communication mode to the still image reception mode.

The control information 12 and image information 13 transmitted after the identification signal 11 are composed of amplitude-phase modulated signals.

The control information l2 is a special case waveform of an amplitude phase modulation signal with a data output frequency of 1748Hz, which is continuous, and the first phase P whose amplitude is maximum and only the phase differs by 180°.
It consists of a signal and a second phase S signal. The P signal and the S signal are each one period of a sine wave. The data clock synchronization signal DC starts with a clock regeneration signal CBI in which the P signal is continuous 16 times, and the P signal and S signal are alternately continuous 20 times.
, CB2, HWP, and SWP, and then there is a control signal 15 for controlling the gain of the receiving circuit, the image transmission mode on the transmitting side, etc.

Immediately after the control information 12, the image information 13 is sent with a continuous clock of pixels for one screen. Each pixel of an image is represented by a waveform that includes the amplitude of one cycle of a sine wave that changes between 16, 32, or 64 gradations from the white level to the black level, and two types of phases that differ by 180''. Specifically,
100 elements of a TV image is the average level point of the signal (0 level)
The control information device 2 for controlling the image information 13 simultaneously modulates the amplitude and phase of one waveform of a sine wave starting from Only the P signal and the S signal whose waveforms differ by 180° are used. In the following explanation, the waveforms of the signals shown in FIG. 1 may be specifically shown and explained, but signals of the same type will be explained with the same reference numerals as much as possible. (Issues) This type of videophone has the following issues.
This will be explained with reference to the waveform diagram in the figure. In FIG. 2, the horizontal axis represents a common time axis t, and the vertical axis represents the level of each signal in correspondence with the frame synchronization signal 14.

The amplitude phase modulated signal 20 transmitted from the transmitting device is first converted into a logic level signal 2l through a vibration limiting amplifier circuit in order to be A/D converted and processed by the receiving device. The waveform of the logic level signal 21 is similar to a known biphase signal 22 when digitally modulated, but since the amplitude phase modulated signal 20 includes a phase discontinuity portion 23, the waveform has a whisker-like abnormal portion 24. Therefore, the biphase signal 22
It is different from.

Videophone receiving equipment is connected to public telephone lines, but
Telephone lines can be connected either forward or backward. If one of them is connected as a normal connection and the other is connected in the opposite direction, for example, the waveform of the amplitude phase modulation signal 20 at the time of the normal connection will be inverted and received, so the waveform after digital conversion will also be the inverted logic level signal 25. It becomes like this.

In that case, image information! In step 1113, not only the white and black of the image are inverted, but also because the entire control information 12 cannot be read correctly at first, the mode is not switched to the still image reception mode, and the image cannot be received.

Therefore, in order to receive images, it is necessary to regenerate the reception clock for sampling to correctly read the control information device 2 and image information i 13, regardless of whether the telephone line and the receiving device are connected in the forward or reverse direction. be.

Furthermore, in order to A/D convert the image information 13 and correctly receive it as digital data, the receiving device as a whole must regenerate a receiving clock synchronized with the amplitude phase modulation signal in any case until reception is completed. is necessary.

The problem of the receiving clock regeneration method of the present invention is that it can handle forward and reverse connections of amplitude phase modulation signals, which are videophone signals that transmit still images, regardless of whether the connection between the receiving device and the telephone line is forward or reverse. The purpose of this method is to determine the polarity of each signal, that is, the polarity of the connection, and to reproduce a reception clock that is synchronized with each signal.

[Means to solve the problem]

The reception clock regeneration method of the present invention includes a means for converting an amplitude phase modulation signal of a data clock frequency into a logic level signal, a zero cross detection circuit that generates an output at the rise and fall of the logic level signal, and an output of the zero cross detection circuit. A wind gate circuit that selects either the output corresponding to the zero crossing point in the center of one cycle of the amplitude phase modulation signal or the passage of all outputs, and a wind gate circuit that selects an output corresponding to the zero crossing point in the center of one period of the amplitude phase modulation signal, and a wind gate circuit that selects an output corresponding to the zero crossing point in the center of one period of the amplitude phase modulation signal, and further a wind gate circuit that selects an output corresponding to the zero crossing point in the center of one period of the amplitude phase modulation signal, and a wind gate circuit that selects an output corresponding to the zero crossing point in the center of one period of the amplitude phase modulation signal, and a wind gate circuit that selects either the output corresponding to the zero crossing point in the center of one period of the amplitude phase modulation signal, or the passage of all outputs. A PLL circuit that compares the outputs of the zero-cross detection circuit near the frequency or near the same frequency, and further transfers the logic level signal using the output of the PLL5 circuit as a shift clock 2
The present invention is characterized by having a circuit section that determines the phase of a received clock using a shift register of bits or more.

〔Example〕

First, in order to facilitate understanding of the present invention, the waveform diagram of FIG. 3 will be explained. FIG. 3 shows the image clock and sampling clock obtained by the reception clock recovery method of the present invention in comparison with the amplitude phase modulation signal when the receiving device and the telephone line are connected in a normal manner and in a case in which they are connected in a reverse manner. The horizontal axis represents a common time axis t, and the vertical axis represents the level of each signal.

Amplitude phase modulation signal 20 of positive connection enters the receiving device and enters the A/D
In the case of conversion, an image clock 79 and a sampling clock 81 for A/D conversion are generated.

In addition, when the amplitude phase modulation signal 5o in the case of reverse connection enters the receiving device and is A/D converted, the image clock 80,
A sampling clock 82 for A/D conversion is generated.

As mentioned above, the P signal, S{ε signal, and image information l
The signal representing l pixels of 3 consists of a waveform of one period of a sine wave, and the amplitude is equal in the first half and the second half. Taking the rightmost P signal as an example, the amplitude phase modulation signal 20 of the positive connection and the amplitude phase change of the reverse connection! Comparing the J signal 5o, the P signal of signal 50 has a waveform in which the first half and the second half of signal 2o are swapped,
The relationship between the waveforms of the signals 20 and 50 is the same in other parts. In other words, the phase of the signal 50 is delayed by 18o6 with respect to the normally connected signal 2o.

Therefore, if the receiving clock is synchronized with the first half of one period of the normally connected signal 20, such as the image clock 79 and the sampling clock 8, then the reversely connected signal 5
In the case of 0, the image clock 80 and the sampling clock 82 synchronized with the second half of one period delayed by 18o are respectively A/
1] If the receiving clock is used for conversion, the same result as when digitally demodulating the signal 20 is obtained using the image clock 79 and sampling clock 81 synchronized with the normally connected signal 20.

The receiving clock regeneration method of the present invention determines the polarity of the amplitude phase modulation signal, which changes depending on the connection state between the receiving device and the telephone line, generates a correctly synchronized receiving clock, and generates a correctly synchronized receiving clock. The same digital demodulated output can be obtained regardless of whether the connection is positive or reversed.

Further, in the reception clock regeneration method of the present invention, after determining the connection polarity of the amplitude phase modulation signal based on the polarity of the logic level signal, the reception clock is generated by detecting the zero crossing point at the center of l period of the amplitude phase modulation signal. As a result, a stable reception clock with extremely low jitter can be obtained.

Hereinafter, explanation will be given with reference to FIG. 4, which is a circuit diagram showing an embodiment of the reception clock reproduction method of the present invention. FIG. 4 shows a receiving circuit reproducing circuit, in which the amplitude limiting amplifier circuit 30,
Zero cross detection circuit 26, wind gate circuit 31, P
It mainly consists of an LL circuit 32, a shift register 33, an exclusive OR circuit 34, a binary counter 35, a flip-flop circuit 36 for polarity determination, a clock switching circuit 37, and a start control circuit 38. As shown in the circuit diagram of FIG.
, and an inverter circuit 29, and generates an output 65A at the rising and falling times of the logic level signal 21 and logic level signal 25 from the amplitude limiting amplifier circuit 30, as will be explained later with reference to FIG.

The output side of the amplitude limiting amplifier circuit 30 is connected to a zero cross detection circuit 26 and a data input terminal D of a shift register 33 having 3 bits, and the zero cross detection circuit 26 is connected to a PLL circuit 32 via a wind gate circuit 31. P
The output side of the LL circuit 32 is also connected to the shift register 33. Adjacent 2-bit outputs of the shift register 33 are applied to an exclusive OR circuit 34. Exclusive OR circuit 34
The output side of is connected to an AND circuit 39 via an inverter circuit 43.
The output side of the AND circuit 39 is connected to the clock terminal CK of the flip-flop circuit 36, the binary counter 35, the two flip-flop circuits 40 of the start control circuit 38,
4l is connected to the reset terminal R, respectively.

The output side of the PLL circuit 32 is connected to a clock terminal CK of a binary counter 35 and an AND circuit 42. The output side of the amplitude limiting amplifier circuit 30 is connected to a data input terminal D of a flip-flop circuit 36.

The output sides of the binary counter 35 and the flip-flop circuit 36 are connected to a clock switching circuit 37, and the output side of the clock switching circuit 37 is connected to an AND circuit 42.

The PLL circuit 32 includes a phase comparator 44, a low-pass filter 45,
It is composed of a voltage controlled oscillator (VCO) 46, a binary counter 66, and a switch section 67, and the voltage controlled oscillator 46 has a frequency f of approximately 2 of the data clock frequency f of the amplitude phase modulation signal 20.
It oscillates at twice the frequency, 2f. data clock frequency f
, is 1748Hz. Before the connection polarity of the amplitude phase modulation signal is determined by the polarity of the logic level signal, the output 65A of the zero cross detection circuit 26 shown in FIG. compare.

In addition, after the connection polarity of the amplitude phase modulation signal is determined,
A phase comparator performs a phase comparison between the output 65B of the zero-crossing detection circuit 26 corresponding to the zero-crossing point 86 at the center of one period of the amplitude phase modulation signal and the output of the binary counter 66 having a frequency almost the same as the data clock frequency f. Do it at 44. Such switching operation is performed by the switch section 67.

The wind gate circuit 3l passes the output 65A, which is the entire output of the zero cross detection circuit 26, before the connection polarity of the amplitude phase modulation signal is determined, and after the determination, it passes one period of the amplitude phase modulation signal of the output 65A. Zero cross point 8 in the center of
Only the output 65B corresponding to 6 is passed. Such a switching operation is performed by a wind pulse signal 85 applied from the control circuit 48 to the wind gate circuit 31. The control circuit 48 also generates a signal for switching the switch section 67 of the PLL circuit 32.

The amplitude-limiting amplification circuit 30 is connected to the input terminal 49 of the reception clock regeneration circuit, for example, by inputting an amplitude/phase change signal! A J1 signal 20 is applied and is now converted to a logic level signal 21. A start signal 75 obtained by detecting the identification signal 11 from the terminal 51 is applied to the start control circuit 38 .

Note that 17 is an inverter circuit, and 18 is an AND circuit. Next, before explaining the overall operation of the Kurofuku signal reproducing circuit configured as described above, first, the operations of the PLL circuit 32, zero cross detection circuit 26, and wind gate circuit 31 will be explained with reference to the waveform diagram in FIG. explain. In FIG. 7, the horizontal axis represents a common time axis t, and the vertical axis represents the level of each signal or output.

In FIG. 7, the zero cross detection circuit 26 detects the rising edge of the logic level signal 21 obtained from the positive connected amplitude phase modulation signal 20, which is the input signal of the reception clock recovery circuit.
Generates an output of 65A at the falling edge. 63 is the output of the multivibrator 27 on one side, and 64 is the output of the multivibrator 27 to which the logic level signal 21 is applied via the inverter circuit 29. The outputs 63 and 64 are combined in the OR circuit 28 to produce an output of 65A. This output 6
5A is the same as the logic level signal 21 and the reversely connected logic level signal 25 (not shown), and the frequency is twice the data clock frequency f.

The wind gate circuit 3l passes the output 65A, which is the entire output of the zero-cross detection circuit 26, before the connection polarity of the amplitude phase modulation signal 20 is determined based on the polarity of the logic level signal 21, as will be explained later. The output of the zero cross detection circuit 26 is 65A, and the oscillator 4 has a frequency of 2f.
The outputs of 6 are directly compared in phase by a phase comparator 44. In the PLL circuit 32, phase comparison is performed at the rising edge of the output 65A, and as a result, the output of the oscillator 46 rises. The output 65A overlaps with one pulse in the x normal s portion 24 of the logic level signal 2t, and the pulse is missing in the discontinuous portion 23 where there is no abnormal portion 24, but it is pulled in regardless of the presence or absence of the abnormal portion 24 in the discontinuous portion 23. will be held.

The clock reproduction signal CB1 of the frame synchronization signal 14 is
No. P4g continues 16 times, but in a state where it continues approximately 10 times, regardless of whether the logic level signal is connected correctly or reversely, and regardless of the presence or absence of the whisker-like abnormal portion 24,
The oscillation output 47 of the PLL circuit 32 eventually enters a pulling state in which it is stably synchronized with the amplitude and phase modulation signals 20 and 50. In FIG. 7, the reversely connected amplitude and phase modulated signal 50 is shown by a dotted line.

After the connection polarity of the amplitude phase modulation signal is determined by the polarity of the logic level signal 2l, the wind game circuit 31 detects the zero cross at the center of one period of the amplitude phase modulation signal among the output 65A of the zero cross detection circuit 26. Output 65B corresponding to point 86 is passed. The frequency of this output 65B is the same as the data clock frequency f. In the PLL circuit 32, a phase comparator 44 performs a phase comparison between the output 65B and an output having approximately the same frequency as the data clock frequency f of the binary counter 66. Thereafter, until the image information 13 is completed, the output 65B as a result of passing from the output 65A of the zero cross detection circuit 26 through the wind gate circuit 31 is applied to the PLL circuit 32, so that the frequency 2f is continuous in phase and has no discontinuous portion. ，
The oscillation output 47 is maintained.

The output 65B of the zero-crossing detection circuit 26 corresponds to the zero-crossing point 86 at the center of one cycle of the amplitude-phase modulated signal, and its position is extremely stable even if the waveform of the amplitude-phase modulated signal is variously deformed. Therefore, if the output 65B is used to compare the phases in a PLL circuit after determining the phase of the amplitude phase modulation signal and a reception clock is generated, there is an advantage that an extremely stable reception clock with little jifter can be obtained.

Note that FIG. 8 is a block diagram showing another configuration of the PLL circuit.

The PLL circuit includes a voltage controlled oscillator 61 that oscillates at a frequency that is 2N times the clock frequency (N is an integer of 2 or more).
, an N-ary prescaler counter 60 to which the output of the voltage controlled oscillator 61 is added, a binary counter 68, and a switch unit 6.
9, by switching the switch section 69, the output of the prescaler counter 60 or the binary counter 68
The phase of the output of the zero-cross detection circuit 26 is compared with that of the output of the zero-cross detection circuit 26, and the oscillation output 47, which becomes the shift clock, can be obtained from the connection point between the prescaler counter 60 and the binary counter 68.

Next, the overall operation of the clock recovery circuit will be explained with reference to the waveform diagram of FIG. FIG. 5 shows the main signals and output waveforms of the reception clock recovery circuit of FIG. 4, where the horizontal axis represents the common time axis t, and the vertical axis represents the signal and output levels, respectively.

The amplitude phase modulated signal 20 in the case of positive connection from the input terminal 49 of the reception clock recovery circuit is converted into a logic level signal 2l by the amplitude limiting amplifier circuit 30. Before the connection polarity of the amplitude phase modulation signal 20 is determined, the PLL circuit 32
As mentioned above, the output 65 of the zero cross detection circuit 26
The phase comparison of A is approximately 2 of the data clock frequency f,
This is performed at twice the frequency 2f, and an oscillation output 47 synchronized with the frequency 2f is obtained.

Next, the logic level signal 2l is transferred to the shift register 33 using the oscillation output 47 as a shift clock. At this time, the level of the logic level signal 21 at the rising edge of the oscillation output 47 is transferred. Then, the outputs 71 and 72 of the adjacent second and third bits are passed through the exclusive OR circuit 34. Note that although the shift register 33 has 3 bits, it may have any number of bits as long as it has 2 or more bits. The reason why a 3-bit one was used is that an AND circuit 70 was added to detect that the P signal was transferred twice. The P signal is transferred twice and the adjacent 3-bit signal is output as the first bit output 7.
When rl O IJ including 3, AND circuit 70
produces an output. The existence of this AND circuit 70 ensures the operation of the start control circuit 38, which will be described later. The exclusive OR concave path 34 converts the frame synchronization signal l4 from the clock reproduction signal CBI to the data clock synchronization signal DC.
A change in the output 74 occurs for the first time when the signal moves to . The first change in this output 74 is at time t, when the second bit output 7l and the third bit output 72 match "0", and r
Changes from lJ to rOJ. The amplitude phase modulation signal 20 at time 1 is an S signal. Thereafter, the change from ``1'' to ``0'' is repeated while outputs corresponding to the P signal and S signal are alternately generated at the adjacent 2nd and 3rd bits. What should be noted here is that even if the amplitude phase modulation signal 20, which is the input signal to the regeneration circuit, is inverted due to the connection state between the telephone line and the receiving device, the output 74 is at the same time 1, and is the S signal. It is about change. Therefore, output 74
By detecting the first change in t and knowing the polarity of the logic level signal at the same time t, that is, whether it is positive or negative, the phase of the receiving clock is determined according to the input signal of the receiving device, which changes depending on the connection state. can. If the polarity is on the positive side, the connection polarity of the amplitude phase modulation signal which is the input signal is positive connection, that is, the amplitude phase modulation signal 20,
If it is on the negative side, it can be seen that the amplitude phase modulation signal 50 is obtained when the connection polarity is reversely connected.

Determining the phase of the receive clock only needs to be done once.
This is done by the start control circuit 38.

The start control circuit 38 is reset by the occurrence of a signal 76 which is initiated by the start word 75 applied to the terminal 51 by detecting the videophone identification signal l1 and which detects the first change in the output 74.

77 and 78 are the outputs of the flip-flop circuits 40 and 41, respectively. signal 76 detecting the first change in output 74;
rises at time t by the AND circuit 39, but stops falling as the start control circuit 38 is reset.

This signal 76 is connected to the reset terminal R of the binary counter 35,
It is applied to the clock terminal CK of the flip-flop circuit 36 for polarity determination.

The binary counter 35 counts the oscillation output 47 of the PLL circuit 32 with a frequency of 2f applied to the clock terminal CK to obtain the output 84 of the frequency loss f3, but it is re-centered only once by the signal 76 and the reproduction circuit is Synchronize correctly with the input signal. Then, synchronized image clocks 79 and 80 are obtained from the clock switching circuit 37 from the first half of one cycle of the input signal P signal.

On the other hand, in the flip-flop circuit 36, the binary counter 35
is sent by the logic level signal 2l at the time of reset,
The polarity of the S signal can be determined. Then, the clock switching circuit 37 is controlled by the output of the Frisop flop circuit 36 to pass either of the image clocks 79 and 80 having different iao' phases.

Image clocks 79 and 80 are the positive and negative outputs of binary counter 35, respectively.

Further, by passing the oscillation output 47 of the PLL circuit 32 through the AND circuit 42 with the output of the clock switching circuit 37, a sampling clock 81 or 82 can be obtained. The sampling clocks 81 and 82 are synchronized with the latter half of the "1" state of the image clocks 79 and 80, respectively.

By applying either of the sampling clocks 81 or 82 obtained by the reproduction circuit to the A/D converter 83, the waveform of the input signal to the A/D converter 83 is inverted depending on the connection state between the receiving device and the telephone line. even if the content is sampled and received correctly.

Image clocks 79 and 80 are used as synchronization signals for the entire receiving device.

The image clock and sampling clock finally obtained as the reception clock are shown in FIG. Further, in the reception clock regeneration method of the present invention, after the connection polarity of the amplitude phase modulation signal is determined, the wind gate circuit 3 selects the center of one period of the amplitude phase modulation signal from among the output 65A of the zero cross detection circuit 26. The output 65B corresponding to the zero cross point 86 is passed. The PLL circuit 32 uses its output 65B and the data clock frequency f. of the binary counter 66. Compare the phase with the output of approximately the same frequency as the output.

Thereafter, until the image information 13 is completed, the output 65B of the zero cross detection circuit 26 is applied to the PLL circuit 32, and the oscillation output 47 of the PLL circuit 32 with a continuous phase and a frequency of 2f without any discontinuous portion is maintained. As described above, the receiving clock regeneration method of the present invention uses a zero-cross detection circuit to obtain a pulse output with a frequency twice the data clock frequency from the logic level signal of the amplitude phase modulation signal of the videophone. The phase comparison of the pulse output is performed using the PI, L circuit using approximately twice the frequency. Then, by processing the logic level signal using the oscillation output of the PLX circuit with twice the frequency as a shift clock, the connection polarity of the amplitude phase modulation signal is determined, and the phase of the reception clock is centrated only once. Then, an image clock and a sampling clock can be generated as reception clocks corresponding to the connection polarity of the amplitude phase modulation signal.

In the embodiment, the phase comparison was performed using a frequency twice the data clock frequency, but other multiples may be used as long as the frequency is an integral multiple.

Therefore, even if the connection to the videophone receiving device ε telephone line is reversed and the amplitude phase modulation signal is inverted, the image clock and sampling clock are automatically switched, making it possible to receive the correct image signal. Become.

Furthermore, after determining the connection polarity of the amplitude phase modulation signal, the amplitude phase change 'l!' is output from the zero cross detection circuit. The phase comparison between the output corresponding to the zero-crossing point at the center of one period of the signal and the oscillation output with almost the same frequency as the data clock frequency is P.
This is done using an LL circuit.

The position of the output of the zero-crossing detection circuit corresponding to the zero-crossing point at the center of one period of the amplitude-phase modulated signal is extremely stable even if the waveform of the amplitude-phase modulated signal is variously deformed.

Therefore, after determining the polarity of the amplitude phase modulation signal, this output is used to compare the phases in a PLL circuit and a reception clock is generated, thereby making it possible to obtain an extremely stable reception clock with little jitter.

The present invention is applicable not only to still image videophones but also to a wide variety of transmission systems in which reverse connection between the line and the receiving device is inconvenient. The voltage controlled oscillator and phase comparator of the PLL circuit have a simple circuit structure and can be easily incorporated into an integrated circuit, making it easy to construct the entire circuit into one integrated circuit.

〔effect〕

The reception clock regeneration method of the present invention automatically switches the image clock and sampling clock to receive the correct image signal even if the connection between the receiving device and the line is reversed and the amplitude phase modulation signal is inverted. becomes possible.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a videophone signal when transmitting a still image, Figure 2 is a waveform diagram of a signal in a conventional receiving device, and Figure 3 is a waveform of a reception clock obtained by the reception clock recovery circuit of the present invention. 4 is a circuit diagram of a reception clock recovery circuit showing an embodiment of the reception clock recovery method of the present invention,
Figure 5 is a waveform diagram of the main signals and outputs in the circuit of Figure 4, Figure 6 is a circuit diagram of the zero cross detection circuit in Figure 4, Figure 7 is the zero cross detection circuit, wind gate circuit,
Signal waveform diagram for explaining the operation of the PLL circuit, No. 8
The figure is a block diagram showing another structure of the PLL circuit. 21, 50: Amplitude phase modulation signal 26: Zero cross detection circuit 31: Wind gate circuit 79, 80: Image clock 81, 82: Sampling clock 3
0: Amplitude-limiting amplifier 32: PLL circuit 33: Shift register 34: Exclusive OR circuit 35: Binary counter 36: Fringe flow controller

Claims (3)

[Claims] (1) means for converting an amplitude phase modulated signal at a data clock frequency into a logic level signal; a zero-cross detection circuit that produces an output at the rise and fall of the logic level signal;
One of the amplitude phase modulated signals in the output of the zero cross detection circuit
a wind gate circuit that selects either the output corresponding to the zero crossing point in the center of the period or the passage of all outputs;
Furthermore, a PLL circuit that compares the output of the zero-cross detection circuit near a frequency that is an integral multiple of the clock frequency or near the same frequency in synchronization with switching of the wind gate circuit;
A reception clock regeneration method further comprising a circuit section that determines the phase of the reception clock using a shift register of two or more bits that transfers the logic level signal using the output of the PLL circuit as a shift clock. (2) The PLL circuit consists of a voltage controlled oscillator that oscillates at a frequency close to twice the data clock frequency, a binary counter to which the output of the voltage controlled oscillator is added, and a switch section,
By switching the switch section, the phases of the output of the voltage controlled oscillator or the binary counter and the output of the zero cross detection circuit are compared, and an output serving as the shift clock is obtained from the connection point of the voltage controlled oscillator and the binary counter. A reception clock recovery method according to claim 1, which is configured to: (3) The PLL circuit has a clock frequency 2N times (N
consists of a voltage-controlled oscillator that oscillates near a frequency (an integer of 2 or more), an N-ary prescaler counter to which the output of the voltage-controlled oscillator is added, a binary counter, and a switch section.
By switching the switch section, the phases of the output of the prescaler counter or the binary counter and the output of the zero cross detection circuit are compared, and an output serving as the shift clock is obtained from the connection point of the prescaler counter and the binary counter. A reception clock recovery method according to claim 1.