JPH03260879A - Recognizing device - Google Patents

Abstract

PURPOSE:To enhance speed of recognition by respectively calculating the distances between the pattern feature data and input feature data, respectively adding the outputs of respective serially connected class selecting means, calculat ing series corresponding to the feature data of the input pattern and determining the number of the pattern in the decreasing order of the scores. CONSTITUTION:Distance calculating means 2-1 to 2-3 calculate the distances of the feature vector and the feature vector previously stored in a memory 11. According to the size of the calculated result, class selecting means 3-1 to 3-3, 4-1 to 4-3 and 5-1 to 5-3 execute rearrangement. According to the re arrangement, score calculating means 6-1 to 6-3 allocate the points for the unit of a mass from the class number of for the unit of the stored mass, and when the point is coincident with the class number for the unit of a character to be stored in the second memory, the allocation and accumulation of the high score is started from the class number close to the serially connected class selecting means. A score sort means 7 rearranges the characters in the order starting from the high score, and the character assigned the highest score is defined as the recognized result. Thus, the processing can be made at high speed by carrying out processing in parallel.

Description

[Detailed Description of the Invention] [Summary] Regarding a recognition device that performs parallel processing using a system link array, the objective is to provide a recognition device that parallelizes processing and speeds up processing, and classifies pattern feature data. A first memory that stores a number, and compares the stored value with the input value, and if it is smaller, it stores the value as it is and outputs the input value, and if it is larger, it outputs the stored value. a plurality of series-connected class selection means for storing inputted values; and feature data of the input pattern are commonly added to the first
a plurality of distance calculation means each calculating a distance between the feature data of the pattern stored in the memory of the input feature data and the input feature data, and adding the results corresponding to the first stage of the plurality of series-connected class selection means; a score calculation means which adds the outputs of the respective class selection means connected in series and obtains a score corresponding to the characteristic data of the input pattern; and a score calculation means which obtains the numbers of the patterns in descending order of the scores obtained by the score totaling means. It is configured to consist of a score sorting means.

[Industrial application field]

The present invention relates to a device for recognizing patterns of speech, characters, etc., and more particularly to a recognition device that performs parallel processing using a systolic array.

[Conventional technology]

With the development of computer systems, reading devices have been put into practical use that capture image data, cut out characters from the captured image data, and scan each character of the text of the read document. This reading device divides the dot data read by an image scanner, etc. into predetermined areas, and compares the characters (desk characters) within each division with the predetermined characters to find the most similar one. The distorted characters are output as a result. This predetermined data is generally stored in a dictionary memory, and the dictionary memory stores, for example, data characterizing each prescribed character. When a character to be recognized is input, the input character is similarly characterized and the distance from the predetermined characteristic data stored in the dictionary memory is determined.

The smallest character from this determined distance is output as the recognition result.

In the above-mentioned system, the distance between the obtained feature data and the feature data stored in advance for each character is determined sequentially for each character.

These feature data are numerical values of the features of each part of the character, and are stored in a matrix of two or more dimensions. When calculating the distance, the difference between the values of individual feature points is calculated and then squared and added. Then, the smaller one of the obtained additions is regarded as the input character and its code etc. are output.

[Problem to be solved by the invention] When trying to find the distance between the above-mentioned pre-stored feature and the feature of the input character and find the character etc. from that distance, it is difficult to find the distance between the pre-stored feature and the input character feature. It is necessary to find the distance to the feature in character units. This feature is not just a single numerical value, but is, for example, a matrix arranged in two or more dimensions, and the number of calculations required to determine the distance between each feature is large. Furthermore, since these distances are calculated on a character-by-character basis, there is a problem in that it takes a lot of time to calculate the distances.

Furthermore, since the minimum distance value is determined for each character, there is a problem in that it takes even more time.

An object of the present invention is to provide a recognition device that parallelizes processing and speeds up processing.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The first memory 1 is a memory that stores pattern characteristic data and class numbers.

Class selection means 3-1 to 3-3.4-1 to 4-3.5-
1 to 5-3 compare the memorized value with the input value, and if it is small, the memorized value is left as is and the input value is output, and when it is large, the memorized value is output and the input value is output. Remember. This class selection means 3-1 to 3-3.4-1
~4-3. 5-1 to 5-3 are connected in series to rearrange the input values in descending order and to store the class corresponding to the value. Distance calculation means 2-1 to 2-3 commonly add input feature data, calculate distances between the pattern feature data stored in the first memory and the input feature data, and send the distances to the class selection means. Add the results.

Score calculation means 6-1 to 6-3 are class selection means 3-1 to
The outputs of 5-1.3-2 to 5-2.3-3 to 5-3 are added to calculate the score corresponding to the characteristic data of the input pattern. For example, the score calculation means 6-1 to 6-3
is a second function that stores the class to which each character belongs.
It determines whether the class inputted by the class selection means is the class to which the character in question belongs, and if they match, it weights it in accordance with the order of the class selection means connected in series. and accumulates character by character. The score sorting means 7 obtains the numbers of the patterns in descending order of the scores obtained by the score calculation means 6-1 to 6-3.

For example, the score sorting means 7 has two inputs, takes in the value of the higher score added from the input, resets the previous stage sort cell to which the input is added, and transfers the taken score and the sort cell to be output to the next stage into a winning tank. More powerful than the bottom.

[For production]

Feature data of the input pattern, such as a feature vector, is added to the distance calculation means 2-1 to 2-3, and the distance calculation means 2-3
-1 to 2-3 are the feature vectors and the first
The distance from the feature vector stored in the memory 11 of the vector is calculated. Class selection means 3-1 to 3 depending on the size of the result
-3.4-1 to 4-3.5-1 to 5-3 are rearranged. For example, the rearrangement is performed in units of squares into which the pattern is divided, and the class corresponding to the value is stored. Then, the score calculation means 6-
1 to 6-3 similarly allocate scores in units of squares and determine whether they match the class numbers in units of characters stored in the second memory, and if they match, select the classes connected in series. Assign higher scores to those closest to the means and accumulate them. The score sorting means sorts the characters in descending order, and takes, for example, the character with the highest score as the recognition result.

Characters are recognized by dividing the feature vector into squares, dividing them into classes, calculating distances, and giving points to characters belonging to class 1, which has the smallest distance value, so the amount of distance calculation for each character is reduced. , processing can be sped up. Also,
Class selection means 2-1 to 5-3 and score calculation means 6-1 to
6-3 can be installed at the bottom of the tank using a systolic array, making it possible to further speed up the process.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

Information read by an image scanner or the like is stored in the image memory 10 as image data.

This image memory 10 has a storage capacity for one page read by an image scanner, and stores each dot of read information as binary data of white or black, that is, 0.1 data.

The image data stored in the image memory 10 is applied to a noise removal module 11 to remove noise generated during reading. For example, the noise removed by this noise removal module 11 is noise unrelated to character information, etc. For example, a 3 x 3 mask with a black center and 8 dots surrounding the center dot.
The dots are noises such as white, and the noise removal module 11 makes the dots in the center white. This noise removal module is provided in the character vl pre-recognition processing unit 12, but is not limited thereto; for example, the normalization module 16 described later
This process may be performed when storing each character in a file, or may be performed when thinning lines or forming line elements.

The image information from which noise has been removed by the noise removal module 11 is sent to the row histogram module 13, the column histogram module 14, and further to the readout control module 1.
Join 5. The row histogram module 13 is a module that projects the read information, for example, the content of the paper read by the above-mentioned image scanner, in the column direction in units of dots, and calculates the number of dots in the row for each dot unit.

That is, this is a process of determining how many black dots are present in each one-dot row (horizontal direction) for each one-dot row. Also, the column histogram 14 is a process of projecting in the column direction in the same way as the row histogram described above, and calculating the number of projected black dots.

The row histogram module 13 sequentially counts the dots of the tool (1 dot by 1 dot) and adds the data through the noise removal module 11 (reading of dots similar to raster scanning) from the image memory 10 in the row direction. (dot rows), and then calculate the number of black dots in each row. The number of black dots becomes the row histogram corresponding to each row. The column histogram 14 also has counters corresponding to the number of dots in one dot row.
Each time a dot is added to a row, the counter corresponding to the black dot is incremented. By performing the above-described operations for one page, the row histogram module 16 and the column histogram module 14 obtain so-called row histograms and column histograms representing the number of dots for each row position and column position, respectively. The result is then applied to the read control module 15.

The readout control module 15 sequentially determines the row and column positions from the row histogram and column histogram. For example, this position can be obtained by the period of the row histogram or the period of the column histogram.

The read control module 15 determines the row and column positions, but also performs the following processing. Image data, for example, information read from an image scanner, may have a tilt depending on the position of the paper and the like.

For this reason, the readout control module 15 sequentially changes the angle at which the histogram is obtained so that the column histogram and the row histogram take the maximum value, and obtains a correction angle.

Then, input the image information added from the above-mentioned noise removal module 11 again to obtain the final histogram,
From the point where the row histogram obtained by the corrected slope (the histogram takes the maximum value) changes from 0 to positive (possible to 0), read out one row of data corresponding to the slope for one period. The data is stored in a row buffer provided within the control module 15.

The read control module 15 further obtains the column histogram within the row of one row of data stored in the row buffer, cuts out the data from the position where the column histogram changes from 0 to positive, and outputs it to the normalization module 16. It is also output to the conversion table creation module 17.

This extracted data is data for a single character area.

The conversion table creation module 17 is a module that obtains conversion data for normalizing one character by the normalization module 16. It projects the conversion data in the column direction and the row direction on the one character area cut out by the readout control module 15, and The counters in the column and row directions are incremented dot by dot (row and column) from the column and row where the dot exists, and the value up to the final value within the area of one character is determined.

In the normalization module 16, the character is enlarged from the final values in the row and column directions of the dot cut out for one character and the size of the cut out one character to a character that exists over the entire area within the cutout area. For example 64X64
An enlargement process is performed to make the dot area into one character area. The column direction and row direction values of characters are converted to conversion table creation module 17.
If there are 48 dots (both columns and rows), processing is performed to convert the 48-dot character to 64 dots. In this process, data in a row or column at a specific position is repeated to make the same data and enlarge the characters. Furthermore, in the case of reduction, rows and columns at specific positions are repeatedly read out and ORed together to reduce them as the same row or example.

The normalization module 16 allows one character area, for example 64X
After one character has been enlarged within 64 dots, the thinning module 18 performs a process of thinning the character. In this thinning module 18, one dot (top, bottom, left and right) of the center dot (
3.times.3), one dot to the left, and two dots above from the center, for a total of 11 dots to perform thinning processing. This mask can also be formed using 9 dots of 3×3.

By controlling the center dot to be 0 when the pattern is predetermined by the mask described above, thinning of the area around one dot forming a character can be achieved in one process. By sequentially repeating thinning of this mask, a character can be formed by a one-dot line.

For example, 64×6 obtained by the thinning module 18
The 4-dot thinned character is added to the line segmentation module 19 and converted into line segments. In this line elementization module, when there are black dots in the vertical direction from the target dot, that is, the center dot, when there are black dots in the horizontal direction, when there are black dots in the upper right and lower left, and when there are black dots in the upper left and lower right, Each dot is represented by a total of four types of line elements. In addition, the above 4
If the line element belongs to more than one of the types, priority is given in the order of, for example, the vertical direction, then the horizontal direction, etc., and in which direction the line element exists is determined for each dot. Note that if the center is an O-dot, that is, white, it is assumed that no line exists.

In the line segmentation module 19, there are four directions: up and down, left and right, diagonally upward to the right, diagonally upward to the left, and five types, including the case where there is no line element, so the state is expressed as a 3-bit value for each dot. , a total of 3X64X64 information,
Add to feature vector module 20.

The feature vector module 20 divides the line segmentation information obtained by the line segmentation module 19 described above into units of 8 dots in the left, right, top, and bottom, and divides the divided areas into 1M areas (2× 2 areas) with a total of 16 dots as one vector module area, and count how many line elements exist in four directions: up and down, left and right, upper right, and upper left. do. A feature vector is calculated using a 16x16 dot area as one vector module area, but since this one vector module area is moved in units of 8 dots, there are 7 areas in each of the row and column directions, resulting in a total of 7 x 7 feature vectors. This is the area of

In the feature vectorization module 20, the number of directions is calculated for each area as described above, but when calculating this number, weighting is applied to each area, with the center being higher and the surrounding areas being lower as they move outward. There is. For example, each dot in the 4 x 4 area centered on the center is given a weight of 4, each of the two dots around it is given a weight of 3, each of the two dots around it is given a weight of 2, and then the two dots around it are given a weight of 4. Each dot is set to 1, weighting is performed, and a feature vector is determined.

This feature vector has specific characters to be recognized all made the same size by the normalization module 16, so
If they are the same character, they have almost the same feature vector,
The feature vector differs for each character. However, since there are modules that are very similar, in order to speed up the calculation process and improve the recognition rate, in the embodiment of the present invention, a dictionary is created in advance using a standard pattern of feature vectors, and each feature vector is Classification is performed within the transformed region, that is, the square, and the distance between the 20 class standard patterns and the added unknown input within each square is determined. That is, the distance between the feature vector in each square of the standard pattern and the feature vector in the square obtained by the special notice vector module 20 is determined for each square. Each of the squares is divided into classes (classes 1 to 20), and the distance ranking of the classes within each square is determined in descending order of distance to the fifth class.

The distance calculation module 21 stores this distance in the class dictionary 23-
1 (standard patterns are stored in class units). Note that when searching for individual candidate characters, the candidate dictionary 23-2 is used (at this time, the switch SW selects the candidate dictionary 23-2).

The top selection and score allocation module 22 determines the top five classes mentioned above and determines the score corresponding to each class for each square. That is, the top selection & score assignment module 22 determines the score to be given to each of the first to fifth classes in the class based on the distance obtained from the distance calculation module 21, and calculates the score of the characters belonging to each class. demand. For example, when the first distance is M (short distance), points are given to the class as 5 points, followed by 4 points, 3, 2.1, and so on. These are provided corresponding to squares 1 to 49, respectively. The processing results of the top selection score module 22 are added to the comprehensive evaluation module 24.

The comprehensive evaluation module 24 calculates the degree of matching between an input object, that is, an input character and its candidate, and has three types of operation: an associative matching mode, an exhaustive matching mode, and an individual matching mode.

The associative matching mode is a mode in which the score of a candidate is calculated from the mask corresponding to the candidate stored in the associative dictionary 23-3 and the class to which the candidate belongs.

As shown in Figure 2 (c), the associative dictionary has a candidate ID for each mask.
The class ID of the class to which the candidate belongs in the mask is stored, using the address as the address.

This data is Cd1m corresponding to the mask ID of each candidate.
It is obtained by clustering a set of dimensional subvectors according to their (weighted) distances, and only the results are stored in an associative dictionary.

Class dictionary 23-1 in the distance calculation module at the same time
is also created correspondingly.

Note that the associative dictionary 23-3 and the class dictionary 23-1 correspond to each other and have the same type. When storing two or more types of dictionaries in one memory, the specification of the dictionary to be used becomes the dictionary reference start position. (Divide this dictionary into candidate IDs,
Comprehensive evaluation can be performed for each in parallel, and if higher speed is required, it can be easily achieved).

The associative dictionary 23-3 is a table in which the class ID: K of the class to which candidate a belongs with mask m is written.
)=, then for candidate a (=1 to c cand), it is obtained as follows. Note that P (m, k) represents the score here. Based on this formula, the overall evaluation value V (a
).

The total matching mode and individual matching mode of the comprehensive evaluation module are modes in which calculations are made for each candidate.

For the complete matching mode, a=1 to c can, for the individual matching mode, J=1-ck ind, a=b(j),
Find the distance expressed as d (m, a). This value V (a) is the feature vector (weighted) distance between candidate a and the input target.

The top candidate selection module 25 selects and outputs a plurality of characters, for example, five characters determined from the top in each character correspondence.

The top five characters become the recognition result in the read image data.

All of the operations described above are performed by pipeline processing. That is, data for one page, for example, in the image memory 10 that stores image data is read out by pipeline processing, divided into lines by the control module 15, and outputted to the normalization module 16 in units of characters. The character wheel is subjected to the above-mentioned thinning, vA atomization, feature vectorization, and recognition processing.

The top selection module 25 ranks the candidates based on the overall evaluation value and selects the top five.If the input is in the associative total matching mode ((aZ V(a)I
a', a = I ~ c cand) If it is the individual integer unit mode ((j, v (aNj □ 1~c kind, a
= b (j)) (Comprehensive evaluation output of individual matching) 'f4/Ascending order: (Character association 2 Largest order, Others; Smallest order), and the output is the candidates ■D (or (input order) and its overall evaluation value.

FIG. 3 shows the constituent countries of the cell structure diagram Njll for performing class selection and exit according to the embodiment of the present invention. The standard patterns are stored in the class dictionary 23-1 of the vector dictionary 27 in the recognition processing unit 26, and are character feature patterns classified into 20 groups with a total of 49 squares as described in the feature vectorization module 20 above. are memorized by class. The standard pattern is, for example, a unit in which 2,965 IIS first-level kanji characters are classified and divided into classes 1 to 20 for each square. In other words, the characteristics of each character are divided into squares (49 squares), and the similar features in each square are divided into 20 minutes M (20 classes). For this reason, as will be described later, an associative dictionary 23-3 is required that stores classes in units of squares to which each character belongs. However, this dictionary only needs to store the class in units of squares to which each character belongs, and has a smaller capacity than a candidate dictionary that stores characteristics in units of characters.

In the embodiment of the present invention shown in FIG. 3, distance calculation cells calculate distances to unknown inputs in parallel for each cell. That is, from square 1 to square 49 (Ml to M49
), numbers 1 to 49 are provided in the distance calculation cells.

Square 4 for square 1.

The storage device that stores the standard patterns for 9 (20 classes each) is a memory, the output of the memory M1 is 1 for the distance calculation cell, the output of the memory M2 is 2 for the distance calculation cell, etc.
The output of memory M49 is added to distance calculation cell 49. In addition, unknown inputs for each cell are added to distance calculation cells Kl~ and 49, and the distances between the feature vector of the unknown input and the feature vector of the standard pattern are calculated in distance calculation cells 1 to 49, respectively. .

In the embodiment of the present invention, the feature vectorization module 2
The feature vectors obtained in 0 are 7 x 7, a total of 49 feature vectors, and the distance calculation cells 1 to 49 have 20 feature vectors.
Individual distances will be found for each class.

FIG. 4 is a circuit diagram of a distance calculation cell according to an embodiment of the present invention. Unknown input values and standard pattern values of feature vectors (weighted total values) in the vertical, horizontal, 45° and 135° directions from the standard pattern are added to the distance calculation cell.

Standard pattern data (added from memory Ml-M49) and unknown input data (feature vectorization module 2
) corresponds to each direction and is subtracted by SU
Join 1~SU4. Each subtracter SUI~SU
Input A of 4 contains the values of each direction of the standard pattern,
The values of unknown inputs in each direction are added to input B, and the subtracters SUI to SU4 output the differences between the values determined in each direction. This value is, for example, a 9-bit value,
The result of subtraction is also 9 bits. These subtractors S
The outputs of UI to SU4 are applied to input terminals A and B of multipliers MXI to MX4. Multipliers MXI to MX4 are circuits that multiply the values added to input A and input B, and are 18
Outputs the bit result. In the embodiment of the present invention shown in FIG. 4, the same value is added to input A and input B, so the output is eventually sent to subtracter 5UI-3.
It becomes the next power value of U4.

The outputs of the multipliers MXI to MX4 are sent to the adder SMI.

Join 3M2. The adders SMI and SM2 are circuits that add values applied to input terminals A and B, and the adder SMI adds the outputs of the multiplier MXI and the multiplier MX2. The adder SM2 adds the output of the multiplier MX4 to MX3 and outputs the result. Since the outputs of multipliers MXI to MX4 are 18 bits, the outputs of adders SMI and SM2 are 19 bits. The outputs of the adders SMI and SM2 are applied to input terminals A and B of an adder SM3. This adder SM3 also has an input terminal A.

These three adders SMI, SM2 . Multiplication by SM3 is calculator MX
, 1 to MX4 are added. To summarize the above-mentioned operations, the distance is obtained by multiplying and adding the difference between the values of the standard pattern and the unknown input in each direction.

As mentioned above, the memory for squares 1 to 49 (Ml to M
The value output from 49) and the unknown input are individually calculated in the distance calculation cells in steps 1 to 49, and the distance DX is determined and output. Although not shown, the class number is also added to the distance calculation cell by the control circuit when calculating each distance, and according to instructions from the control circuit, the memories M1 to M49 address the area corresponding to the class, and at the same time, the distance calculation cell is added to the distance calculation cell. calculates the distance and outputs it (DXI to DX49). At the same time, class numbers 1 to 49 are added to the distance calculation cell, and the distance calculation cell also outputs the class number.

The distance calculation cell 1 outputs the distance MDX1 and class number CL1 to the class selection cell CXII. Further, the output of the class selection cell CXII is sequentially outputted to the class selection cell CX12 and similarly to the class selection cell CX15.

Class selection cells CXII to CX15 are the same circuit, and have a register that stores the distance and a register that stores the class number.When the input distance value is smaller than the value of the register that stores the distance, The value and class number are stored, and the distance and class number stored so far are output to the next class selection cell. When the value is large, the register value is not changed and is output to the next class selection cell.

By this operation, the class selection cells CXII to CX15 are stored in order from the lowest value to the lowest value. Similarly, the class selection cells CX21 to CX25 for square 2 are also
The same applies to the class selection cells CX491 to CX495 for 9.

FIG. 5 is a processing block diagram of the above-mentioned class selection cell. The input distance af' is calculated by the function calculation circuit af.

Add to a f, , a f4, a f.

Further, the class number ag' is added to the function calculation circuits afg and afn.

The output of the functional arithmetic circuit af is applied to the register arn, and the output of the functional arithmetic circuit af- is applied to the registers ar,t. And, the output ad' of register ar is the function arithmetic circuit a f
t + a fa * a fn s register a
r.

The output an' is applied to the function calculation circuits af, , affi.

The function operation circuit af is the value ad stored in the register ar.
When the input distance @af' is smaller, the distance is 11 [af'
This is a function that outputs ad' at other times.

The function operation circuit affi outputs the input class number ag' if the input distance af' is smaller than the value ad' stored in the register ar, and otherwise outputs the class number an' stored in the register ar. do. If the input distance af' is in the register ar, the function calculation circuit jt
When the distance @ad' stored in d is small, this distance ad' is output, and at other times, the added distance af' is output. The function calculation circuit af converts the output ag into the added distance 11[a
When f' is smaller than what is stored in register ar, it is set as an'; otherwise, the input class number ag' is output.

The above functional operation circuits af, , af, , afr, a
The distance af' is added by the operation of fg, and if it is smaller than the previously memorized value ad' stored in the register ara, the new value af' is stored in the register ar4, and the output ad' of the register ara is subjected to an interval calculation. times IIIafr
outputs. The class number is also the same, register a
When comparing the value ad' stored in r with the input distance af' and storing a new value in the register ar4, the register arn stores the class number, and the function calculation circuit af
, outputs the value currently stored in register all.
do. Note that the outputs of the functional operation circuits aft and afe are provided with registers aff and at, which are used to shift sequentially in clock units when five stages of class selection cells are connected as shown in FIG. Although class selection cells CX11 to CX495 are not shown, each time a clock is applied, the registers are changed to function operation circuits aff, af, and so on.

Take in the output of af+s and afa.

FIG. 6 is a circuit diagram of a class selection cell according to an embodiment of the present invention. In the processing configuration diagram of FIG. 5, the respective function calculation circuits a ff + a fg , a fg
1afa calculates the difference between the input distance and the stored distance, but in the configuration of FIG. 6, the comparator CMP compares the stored value and the input. In other words, the value ad' stored in register FFI is stored in comparator CMP (
A-B) is applied to input terminal B, and input af' is applied to input terminal A. The comparator CMP is a circuit that calculates (value input to input terminal A - (value input to input terminal B)),
As mentioned above, the input distance Mar' added to input terminal A
When the distance ad' stored in the register FFI added to the input terminal B is large, 1 is output, and vice versa, the poem/number '0' is output. When the distance 11ad' stored in the register FFI is greater than the input distance af', 1 is sent from the comparator CMP.
is output (S), so 1 is added to the selection terminal S of the selection circuit MUX, and the selection circuit M U''X has its input terminal (
1) Select and output the input. That is, when the comparator CMP is l, the selection circuit MUX selects the input f' and registers F.
Add to FI.

Then, the selection circuit MUX2 selects the class number ag' and outputs it to the register FF2. In addition, the selection circuit MUX3. M
UX4 selects the outputs of registers FFI and FF2, and selects the outputs of registers FF3. Add to FF4. Incidentally, after the input, that is, the distance af' and the class number ag' are added, the registers FFI to FF4 take in the data selected by the above-described operation at the next clock.

On the other hand, the output of the comparator CMP is 0, that is, the input distance @af
is greater than or equal to the distance 11ad' stored in register FFI (S=
0), the selection circuit MUXI.

MUX2 selects the 0 input terminal. Therefore, register F
The outputs of FI and FF2 are passed through the selection circuit to the registers FFI and
Joins FF2. Further, the distance af' and its class number ag' inputted from the selection circuits MUX3 and MUX4 are selected and added to the registers F3 and F4. At this time, the clock CL
When K is added, registers FFI and FF2 store their respective stored values again, so the data does not change, and registers FF3 and FF4 store and output the input distance Mar' and its class number ag' (af , ag).

The class selection cells in FIG. 6 are provided in multiple stages (5 stages), and the distance values calculated in steps 1 to 49 and their class numbers are sequentially different in the distance calculation cells. At this time, each class selection cell is connected in series, so in the first class selection cell CXII to CX15, for example, the minimum distance and its class number to the class selection cell CXII are set to the next value to the class selection cell CX12. However, the fifth value from the minimum value and the class number are sequentially stored in the class selection cells CXII to CX15. Incidentally, at the initial time, although not shown, the maximum value is stored in the registers FFI to FF4.

By the above-described operation, the characteristics of each input character are added, and the distance calculation module 21 calculates the distance in units of squares using the class dictionary. Then, the higher rank selection module 22 selects the higher rank for each class. This higher rank selection module is constituted by the class selection cells shown in FIG. 6 described above, and the top five classes in each class are selected. In other words, the top five classes with the shortest distances for each of squares 1 to 49 of the upper selection module 22 are selected as the class selection cell CXll.
-CX495 is selected. The results of each class 1 to 5 in units of squares obtained in the top selection module 22 are further calculated into points for score calculation, and points are added for each rank and added to the comprehensive evaluation module 24.

FIG. 7 shows the constituent countries of the cell structure network that performs score calculation and sorting according to an embodiment of the present invention. The comprehensive module 24 is a module that performs score calculation and sorting. Associative dictionary 23
-3 stores a class number for each character corresponding to the class dictionary, and the comprehensive module 24 calculates a score for each character from this class number for each character. Then, the top five candidates are selected by the top candidate selection module 25 based on the characters with the highest scores. Score calculation cell MC1 for square 1 to score calculation cell MC49 for square 49 in Figure 7
The score sorting cells TSI to TS5 constitute this comprehensive evaluation module 24. The aforementioned recognition processing section 26
The associative dictionary 23-3 of the vector dictionary 27 corresponds to the numbers classified into classes by the class dictionary in the vector dictionary 27, and stores the class numbers for each character, for example, 2965 JIS first level Kanji characters, in units of squares. The score calculation cell MC1 for square 1 to the score calculation cell MC49 for square 49 are circuits that allocate points to the class to which each character belongs on a character-by-character basis. That is, a score of 5 is given to the class stored in the class selection cell CXII for square I. Also, class selection cell CX12 has a score of 4, class selection cell CX13 has a score of 3,
Score 2 for class selection cell 14, class selection cell CX15
is assigned a score of 1. And first, letter 1 in square 1
When the class number is added from the associative dictionary 23-3, the class number of the first character in that cell 1 is added to the class selection cell CXI.
Determine whether it matches the class number stored in I. If they match, the score for character 1 is set to 5. If they do not match, it is determined whether they match the class stored in the next class selection cell CX12. If they match, the score is 4. Similarly, if the class number does not match the class number stored in the class selection cell CX12, it is compared to see if it matches the class number stored in the class selection cell CX13, and if they match, the score is set to 3.

By doing the same, points are assigned to class selection cells CXII to CX15 when there is a class corresponding to the character stored in each class unit.

This process is executed for each square, that is, for squares 1 to 49, by score calculation cell MC1 for square 1 to score calculation cell MC49 for square 49, and score calculation cell M for square 49.
From C49, the scores of characters 1 to 2965 are output in character order.

Since the score calculation cell MC2 for square 2 is added to the result calculated by the score calculation cell MCI for square 1, the class number of each character outputted from the dictionary 23-3 is added with a delay of l operation processing for each square. In other words, the dictionary 23-3 in Fig. 7 is added character by character to the score calculation cell for each square in sequence, and as a result, the first character in the score calculation cell MCI for square 1 is the score for square 2. By adding to the calculation cell, the result and the score of the first character are added in the score calculation cell MC2 for square 2, and then added later in order,
As a result, the total score for each character is output from the score calculation cell MC49 for square 49.

FIG. 8 is a processing configuration diagram of a score calculation cell according to an embodiment of the present invention. As shown in FIG. 7, the class number is added to the score calculation cell MCn (n is 1 to 49) for each square.

That is, class selection cell Cnl−class selection cell Cn5
The class number calculated in is the score calculation cell MC for square n.
join n. This score calculation cell MCn has the class number bd of the square n added from the dictionary 23-1 as the class selection cell Cn.
It is determined whether it is equal to the class number bb5 added from l, and if they are equal, 5 is added to the result bP/ added from the previous cell. If they do not match, continue with the class selection cell Cn.
It is determined whether the class number bb4 added from the dictionary 23 is equal to the class number bd added from the dictionary 23. If they are equal, add 4 to bp' added from the previous score calculation cell. If not equal, add class number bb3 from class selection cell Cn3. Class number bd added from dictionary 23.
Determine if it matches. In this determination, if they match, 3 is added to the result bp' added from the previous stage. If they do not match, it is determined whether the class number bb2 added from the class selection cell Cn4 and the class number bd added from the dictionary 23 match, and if they match, 2 is added to the result bp' added from the previous stage. If they do not match, the class number bbl is added from the class selection cell CN5 and the class number b is added from the dictionary 23.
d and when they match, the result b added from the previous stage
Add 1 to p'. If they do not match, the previous result bp' is directly output (bp). Function bf executes the above cell and outputs it via buffer b7. That is, the output p of cell MCn is given by the following calculation formula.

fl,: bp=if bb+==bd then b
pl +5else if bb2. , bd th
en bp' +4else if bb3. , bd
then bp' +3else if bb4.
, bd then bp' +2else if b
b5. , bd then bp"+1else p' In FIG. 8, score calculation is expressed as a function. FIG. 9 is a further detailed circuit configuration diagram of the score calculation cell.

In FIG. 9, each circuit is composed of an arithmetic circuit. The class numbers bb5 to bbl added from the class selection cells Cnl to Cn5 (n is 1 to 49 as described above) are signals each consisting of 5 bits (20 classes are used, so 20 classes are expressed with 5 bits). The class number bd added from the dictionary 23 is added in common to each of the five exclusive logic OR games) EOR1 to EOR7. Furthermore, the class number bb5 added from the class selection cell Cn1 is commonly applied to the other input terminals of the exclusive OR gates EORI and EOR7.

The exclusive logic OR gate EOR6 has a class selection cell Cn.
Class number bb4 is added from 2. Furthermore, exclusive logic OR gates EOR2 and EOR5 have class number bb3, and exclusive logic OR gate EOR4 has class number b2 added from class selection cell Cn4.
The class number bbl is added from the class cell Cn5 to the other input of R3. Exclusive logic or game) EORI~EO
R7 is a circuit that compares the numbers bbl to bb5 added from each of these class selection cells Cn1 to Cn5 with the class number bd added from the dictionary 23 or not.

Exclusive logic or game consisting of 5 of these each) EOR
The 5-bit output of I~EOR7 is NOR2~
Join N0R6.

The aforementioned NOR gates N0RI-NOR3 are applied to the OR gate ORI, and the outputs of NOR4 and N0R5 are applied to OR2, and the outputs of NOR6 and N0R1 are applied to OR3.

When the class number added from the dictionary 23 matches the class number b5 added from the class selection cell Cnl, for example, the outputs of exclusive OR gates EOR1 and EOR7 go to L level for all 5 bits, and the outputs of NOR gates N0R1 and N0R7 go to H level. . Note that the other exclusive logic OR games) EOR2 to EOR6 differ in one or more bits, so each NOR game) NOR2 to N0R6
One or more bits of H level are applied to each input, and the outputs of these NOR gates N0R2 to N0R6 become L level. As a result, the outputs of NOR1 and NOR gate N0R7 become H level, so the outputs of NOR1 and NOR gate N0R7 become H level.
The outputs of OR1 and OR3 are at H level, and the output of OR gate OR2 is at L level.

When the class number b5 added from the class selection cell Cnl and the class number d added from the memory 23 match,
As mentioned above, OR gate OR1 and OR gate OR3 are H.
This value becomes 5 and is added to the adder circuit SUMI.

Furthermore, when the class number b4 added from the class selection cell Cn2 and the class number d added from the memory 23 match, the outputs of the exclusive OR gate EOR6 all go to L level, so the output of NOR6 (NOR6) becomes H and all others It becomes L. As a result, an or game consisting of 3 bits)
The output of OR3 to OR1 becomes a value representing 4. Furthermore, when bb3 added from class selection cell Cn3 and class number bd added from dictionary 23 match, the outputs of exclusive logic OR gate EOR2 and exclusive logic OR gate EOR5 become all 0, and this result is added to NOR gate N0R.
2. The output of N0R5 becomes H level, and the OR gate OR
It becomes a value representing 3 via I and OR2. Similarly, class number bb2 and dictionary 2 added from class selection cell Cn4
When the class number bd added from 3 matches, the output of the exclusive OR gate EOR4 becomes L level.

As a result, all 5 bits of NOR gate N0R4 are L.
level is added, and the output becomes H level. As a result, the outputs of OR3-O, R1 become a value representing 2. Further, when the class number bbl added from the class cell selection cell Cn5 and the class number d added from the dictionary 23 match, all 5 bits of the output of the exclusive logic OR game) EOR3 go to L level, and the output of the NOR gate NOR3 to which this result is added becomes H level becomes OR3~ORI
The output of is a value representing 1. That is, to summarize, when the class number bb5 added from the class selection cell Cnl and the class number bd output from the dictionary memory match, 5 is added, and the class number b added from the class selection cell Cn2 is 5.
When b4 matches, 4 matches the class number bb3 added from the class selection cell Cn3, 3, when it matches the class number bb2 added from the class selection cell Cn4, 2, and the class number b added from the class selection cell Cn5.
When it matches bl, 1 is output respectively (the above operation outputs the values of exclusive logic OR gate EOR1 and exclusive logic OR gates EOR7 and 4, which should each output a value of 5 for each bit. An exclusive logic OR gate that should output the value of the exclusive logic OR gate EOR6, 3) Exclusive logic OR gate that should output the value of EOR2, EOR5, 2 -) Exclusive logic OR gate EOR3 that should output the value of EOR4, 1, respectively. There is. Note that these seven exclusive logic OR gates EORI to EOR7 may be exclusive logic OR gates that compare 5 bits each if an encoder is provided.

The output of the value corresponding to each class number of the above-mentioned or game) OR3 to ○R1 is applied to the input terminal A of the adder SUMI. Also, @b is added to the B terminal of the adder SUMI from the previous stage.
p' is added. The adder SUM1 adds the values applied to the A terminal and the B terminal, and adds the 8-bit value added from the previous stage and the value obtained by the above-mentioned comparison result.

As mentioned above, the value applied to the A terminal is generated in correspondence with each class, so when a value corresponding to that class is added from the dictionary memory 23, the value corresponding to that class number is added by the adder SUMI. flip flop F
Store it in FI.

By providing 49 cells corresponding to squares 1 to 49 through the above-described operation, it is possible to obtain the values of 2965 characters, for example, according to JIS, in one character position, that is, the score.

Returning to Figure 7, the explanation will continue. By the above-described operation, the scores corresponding to the characters stored in the dictionary 23 are sequentially output from the score calculation cell MC49 for the square 49.

The result is added to the score sorting cell TSI.

Score sorting cells TSI to TS5 are circuits that store score values and character codes in descending order of scores, and sequentially store the value when the score added from score calculation cell MC49 for square 49 is higher than the value stored in score sorting cell TSI. However, when it is low, it is output directly to the next stage. Note that character numbers (codes) are also added to this score sorting cell, and the score sorting cells TSI to TS5 store the scores and codes in correspondence.

Class selection cells Cnl to Cn5 in FIG. 3 are sorted in descending order of value, that is, in descending order of distance.
The score sorting cells TSI to TS5 in the figure are sorted in descending order of scores.

FIG. 10 is a processing block diagram of a score sorting cell according to an embodiment of the present invention. Each cell TSI-TS5 has the configuration shown in FIG. 10, and when the added score is larger than the value stored in its own cell, it stores and updates the added score cell, and updates the currently stored value. Output to the next stage. Below, the score to be input is Cf', the kanji number (code) is Cg', the stored score is Cp, the stored kanji number Cn, the score to be sent to the next cell is Cf, the kanji number to be sent to the next score Let be Cg.

The score cf' is the function Cfn, Cf, , Crt, Cf,
join. Kanji number Cg' is added to functions Cfn, Cf. The output of the function C・f is the register Crn, the function Cf,
The output of is input to register Crp. The output cn' of the register Crn is input to the function Cff1°Cf, and the output cn' of the register Crn is
The output Cp' of is the function Cf, , Cf, , Cf, , Cr
join t. The function Cf outputs the input value when the input value Cf' is larger than the output Cp' of the register Crp, and otherwise outputs the Crp value Cp' of the register to which it is added. As a result, if the input value is larger than the value stored in the register Crp, that is, if the score is high, the value is output to the register to be updated, but otherwise it is not updated. Also, the function Cff1 is the function Cf
Under the same conditions as , that is, when the input value Cf' is larger than the value Cp' stored in register Crp,
The input Kanji number Cg' is output, otherwise the value stored in the register Crn, that is, the output Cn' is output.

As a result, the register Crp stores the Kanji number corresponding to the higher score. If the value input from the family cell is higher than the value to be memorized by the above operation, that value and its corresponding kanji number will be memorized, but if the score is small, the score and kanji number will be transferred to the next stage, and the score will be stored again. When is large, the memorized score and its kanji number must be output to the next stage. Functions Cff and Cf do this.

The function Cr t has the input score Cf' in the register Cr t.
When the value Cp' is larger than the stored value Cp', Cp' is output; otherwise, the input score Cf' is output. In addition, the function Cf outputs the value cn' stored in the register Crn when the input score Cf' is larger than the value Cp' stored in the register Crc, and otherwise outputs the kanji number C to be input.
Output g'. Note that these values are also stored in register Cr.
f.

They become inputs Cf and Cg to the next level via Crg.

Through the above operations, the largest value added to this cell is stored as a score, and the Kanji number corresponding to that score is further stored. By connecting these cells in five stages, five scores and five corresponding Kanji numbers are stored in each of the five cells.

FIG. 11 is a circuit diagram of a score sorting cell according to an embodiment of the present invention. Each of the functions in FIG. 10 mentioned above compares the input score Cf' with the value stored in the register Crp, but in the circuit configuration of FIG. There is. That is, comparator CM
This is done by PT.

When the score Cf' is input to the comparator CMPT, the selection circuit MUX
TI joins MUXT4. Kanji number Cg' is selected by selection circuit MUχT2. Join MUXT3.

Flip-flop (register) FFTI has a selection circuit M
The output of UXTI is added and its flip-flop FFT is
The output of l is Cp' which is applied to the other input of the selection circuit MUXTl, the A@ child of the comparator CMPT, and one terminal of the selection circuit MUXT4. The output of the selection circuit MUXT2 is applied to the flip-flop (register) FFT2, and its output n'
is applied to one terminal of the selection circuit MUXT2 and one terminal of the selection circuit MUXT3. Comparison output S of comparator CMFT is applied to selection circuits MUXT1 to MUXT4. The clock is input every time a comparison is made, and is input to each of the flip-flops FFT1 to FFT4.

When a certain score Cf' is input, the comparator CMPT
1 subtracts the value applied to the A and B terminals.

That is, perform A-B. This comparator sets the output S to 0 when the result is 0 or more (f'=p), and when the result is negative (f'
=p), S is set to 1.

The output S of the comparator CMPT1 is the selection circuit MUXT1
~ Joined MUXT4. In other words, the score c to be input
When f' is smaller than the value cp' stored in the flip-flop FFTl, the comparator CMPTI outputs 0. This O causes the selection circuits MUMT1 to MUXT4 to select and output the signal applied to the O terminal. That is, at this time, the selection circuit MUXT1 selects the output cp' of the flip-flop FFTl, so the result does not change.Similarly, the selection circuit MUXT2 also selects the output cp' of the flip-flop FFT1.
Since the output cn' of FT2 is selected, the flip-flop F
The output of FT2 also does not change.

Further, since the selection circuit MUXT3 selects the input Cg' applied to the 0 terminal, the FFT3 stores c g / and outputs cg. Also, in terms of scores, the selection circuit MU
Since the XT4 selects the point c f 1 added to the O terminal, the flip-flop FFT4 also stores the input point cf', and the output cf becomes the input cf'.

On the other hand, when the input score cf' is larger than the value Cp' stored in the flip-flop FFTl, the comparator CM
Since PT1 outputs l, at this time each selection circuit MU
XT1 to MUXT4 select one terminal input. That is, the selection circuit MUXT1 selects and outputs the input score cf'. This causes flip-flop FFTl to store the new value. Incidentally, at this time, before storing, the output cpl of the flip-flop FFTl is sent to the selection circuit MUXT4.
Since the selection circuit MUXT4 selects the output cpl of the flip-flop FFTl and adds it to the register FFT4, the flip-flop FFTl stores the new score Cf' by the clock. Also, the score cp' stored in the flip-flop FFTl is stored in the flip-flop FFT4, and its value is output. Similarly, the selection circuit MUXT2 selects the newly added input cg', and selects the input cg' from the flip-flop FFT.
2 stores the input Kanji number. Also, the value before being stored in the flip-flop FFT2 is stored in the selection circuit MUXT3.
Therefore, the selection circuit MUXT3 connects 1 to the S terminal.
When , the flip-flop FFT2 applied to one terminal
The output cn' of is selected and added to the flip-flop FFT3.

By the above operation, the values input by one clock are compared and judged based on the result, and if it should be stored, it is stored, that is, if it is large, it is stored, and if it is small, it is not stored and is not changed. It will be output to the next stage. Through the above operations, the score sorting cell stores five values and their Kanji numbers in descending order of score.

In the above-described embodiment of the present invention, five classes are selected for each square, and the class number of the first character in square 1 is selected, followed by the class number of the second character, and the result is further divided into squares 2. Following the score calculation cell MC2 for square 3, the score calculation cell MC3 for square 3, and so on, and MC49 are sequentially executed for each square.

FIG. 12 shows the constituent countries of the cell configuration circuit network for calculating the score according to the embodiment of the present invention. The dictionary 23' stores class numbers for each character and each cell, and the dictionary 23' stores the class numbers for each character and for each cell.
The class number for each character (the class number for each square to which the character belongs) is added. The first to fifth classes are commonly added to the score calculation cell MY1 for character 1 to score calculation cell MY2965 for character 2965, respectively, by the class selection cell described above.

At this time, the character score calculation cell MYI-MY2965 is compared with the class number added from the dictionary 23'.

Then, if it matches the class selection cell CYIIO class number, 5 points are given, and then the second class selection cell CY12
If it matches, give 4 points, etc. up to the 5th point. Five sets of class numbers are output in sorted order from the class selection cell for square 1, and the score calculation cell CYI for character 1 is output.
~When the score calculation cell CY2965 for character 2965 performs the calculation, the class selection cell CY21 in square 2~
CY25 results have been added (class selection cells CYII to C
Y495 has a shift register configuration in units of squares, and when the result of square 1 is output, the result of square 2 is stored in square 1 and shifted sequentially each time the calculation is completed). Scores for characters to which classes 1 to 49 belong are added. The dictionary 23' has a similar structure, and each character has a class number for square 1, a class number for square 2, a class number for square 49, and a score calculation cell for character 1 MYI to character 2965.
The point calculation cell MY2965 performs addition when it belongs to the corresponding class.

FIG. 14 is a processing block diagram of the aforementioned score calculation cell. The class numbers db5 to dbl are added to the function df of the score calculation cell MYn from the class selection cell CYII for square 1 to the class selection cell CY15 for square 1, respectively. The function df is a function that sets the output dp for six inputs as follows.

df, : dp = if db+==dd the
n dp' +5e se if db,==dd t
hen dp' +4e se if db,==dd
then dp' +3e se if dba==
dd then dp' +2e se if dbs
"=dd then dp' +1e se dp' Here, dp' is the output of the register dr. That is, the class number dd added from the dictionary 23' and the class selection cell C
When the class number dbl added from YII matches, 5 is added to dP' which is the output of the register. Also, when it is equal to b2, which is the output of class selection cell CY12, set 4,
Similarly, class selection cell CY13 to class selection cell CY1
If they match b3 to b5 output from 5, 3.2.1 is added to each. As a result, scores of 5 to 4 are added sequentially for each class. It should be noted that if they do not match, no addition is made and dp remains as is.

The output dp of this function dfp is added to the register dr, and after the first reset, the score for square 1 is added to the value dp' of the register dr (0 at reset), and the result is latched. .

Then, sequentially class selection cells CYII to CY495
will be shifted in units of 5 classes, and the above-mentioned scores will be added sequentially. There are class selection cells for squares 1 to 49, and it is possible to obtain the score for each character by a total of 49 calculations.

FIG. 15 is a circuit diagram of the aforementioned score calculation cell. Exclusive logic or game) EORI~EOR7, Noah Gate N
OR1~NOR? , ORI to OR3 have the same configuration as in FIG. 9, and compare the input dd with the class numbers db1 to db5 added from the class selection cells, respectively, and when they match, output a value corresponding to that class. In other words, when it matches the class number dbl added from the most similar class, add 5, then add 4 to the second class number db2,
3 is added to the input B of the adder SUM2 as a 3-bit signal for the class number db3, 2 for the class number db4, and 1 for the class number db5.

In the configuration diagram of the calculation cell shown in FIG. 9 mentioned above, the score for each next cell is added in sequence to the score added from the previous calculation cell, but in the example shown in FIG. 15, the score for the same character is Since the calculation is performed on a character-by-character basis, the flip-flop FF
2 is added to the A terminal of the adder SUM2 for accumulation. If we reduce it, the class number dd is added to each square of each character, and the class numbers dbl to db5 are similarly added to each square from each class selection cell, and when they are compared and matched, the corresponding value (weight) is added and accumulated for each character.

In the embodiment of the present invention, since there are squares 1 to 49, the calculation is accumulated a total of 49 times, and the score calculation cells MYI to MY2965 are output. By the above-described operations, calculations can be performed in units of squares or in units of characters. In particular, if the calculation is for each character, the class number added for each square is compared with the class number for each square of each character added from the dictionary 23', and when they match, the corresponding score is added. The number of times required is only 49, and the processing speed can be increased.

FIG. 16 is a block diagram of a cell structure circuit network that performs score calculation and sorting. In the embodiment shown in FIG. 7, since calculations are performed for each square, the number of characters to be recognized is 2.
It is necessary to perform calculations for 965 characters. Therefore, many calculations must be performed for the entire process. Also, in the configuration shown in Figure 12, each cell needs 49 calculations. The number of cells is as large as 2965, and the number of circuits configuring it increases.

In Figure 16, four score total cells are provided for each square 1, and the characters are divided into four: characters 1 to 741, characters 742 to 1482, characters 1483 to 2223, and characters 2224 to 2965. Each is calculated separately. In other words, there are 4 score calculation cells for square 1 (Mdll
-Md14), output the results to the score calculation cells (Md21 to Md24) for square 2, and similarly, sequentially calculate total squares 49 (Md31 to Md34 . . . Md491 to
The configuration is such that calculations are performed 49 times up to Md494).

In other words, the configuration shown in FIG. 7 is arranged in parallel with four sets, each dictionary is divided into four sets, and the processing is performed in parallel in units of 4&Il. In this case, since the score is output for four characters at the same time, the rank of each character output from each mass calculation cell 49 is determined. Therefore, the score calculation cell Md49 for square 49
In order to sort the scores output from 1, score sorting cells TT41 to TT45 are connected in series and added to cell TT41 at the input stage. Similarly, the score calculation cells MD492 to MD494 for square 49 are added to the input stage cells TT21 to TT41 of the series-connected score sorting cells TT31 to TT11, respectively. In other words, score sorting cells TTII to TT45 are each sorting cells connected in a 5-stage series, and each character is divided into 4
The scores of &l are added, and the scores up to the fifth score within the characters 4 & Il are sequentially sorted in the sorting cell. In the embodiment of the present invention shown in FIG. 16, five characters must be finally selected character by character, so first 2
Comparisons are made in units of pairs, the higher one is selected, and added to the next stage score sorting cell TU3.Finally, character candidates with higher scores of 5M or more are output as results.

Note that the score sorting cells TTII to TT45 also include character numbers corresponding to the scores, and the score sorting cells TTII to TT45 sequentially sort the character numbers and scores.

Also, score sorting cell I [TUl.

TU2. TU3 compares the scores and also outputs the character number to the next sorting cell if it is higher. By the above-described operation, characters can be parallelized to speed up the processing even in calculations in square units, and it is possible to compare, for example, four characters at a time.

When sorting the scores output from the character score calculation cells in the cell structure network of the embodiment of the present invention in FIG. 12 and the cell structure network in FIG. ), the results can be obtained by a sequential winning method. FIG. 17 is a block diagram of a cell conceptual circuit network for sorting scores according to an embodiment of the present invention. The score calculation cells are the score calculation cell MY1 for character 1 to the score calculation cell MY2915 for character 2915 shown in FIG. 12, and these cells MYI to MY
The scores obtained from 2915 are added to the score sorting cell SX in a winning configuration.

FIG. 18 is a processing block diagram of the score sorting cell SX for selecting candidates from each score calculation cell.

Results are added from the left child (score sort cell or score calculation cell on the left side of the previous stage) and the right child (score sort cell or score weight cell on the right side of the previous stage). In other words, the score epl input from the left child is the function efan ef,,ef,
1. Join ef, . Also, points added from the child on the right eP
r is a function e ffi, e f,.

ef rl + e f Join PP.

Also, the character code number enl input from the left child and right child
, enr are added to the function erfi. The output en of the function eflI is stored in the register ern, and the output e of that register ern is
n' is added to the left and right cells of the next stage, and the function ef,
Also join. Also, the output of the function ef is added to the register arp, and its output ep' is added to the next cell, and the functions efne fp, e fly, e fr
join r. The output erl of the function efrl becomes a reset signal for the left child of the previous stage, and the output 1rr of the interval number efrr becomes a reset signal of the right child of the previous stage. As shown in FIG. 18, each function ffi, f, , frl+
Lr is the following function.

ef, : ep = if ep'≠-1the,
n ep'else if epI>pr then
eP+else epr ef, : en = if ep'≠-1then
en'else if epl>p, then en
161se enr ef, 1: er = if ep'≠-1then
0else if epI>ep, then 1l
se 0 efrr: er = if ep'≠-1then
0else if eP+>Pr then 0el
se 1 If the above-mentioned function is further configured as a circuit, the circuit configuration of the score cell shown in FIG. 19 is obtained. The score epI added from the left child and the score epr added from the right child are the comparison circuit CM.
The comparator circuit CMP1 compares the data applied from the A terminal with the data applied from the B terminal (A-B) L, and when it is positive, the signal S is 1, and when it is negative or O. When the signal S is set to 0, the result is sent to the selection circuit MUXU.
I, add to MUXU2. The selection circuit is MUXUI, MU
XU2 selects the signal applied to one terminal when the applied signal S is 1, and selects the signal applied to the 0 terminal when the applied signal S is 0, and outputs it. The output of the selection circuit MUXU1 is the selection circuit MUXU
3, and the output of the selection circuit MUXU2 is the selection circuit MUX
Joins U4. For example, if the score eP+ is greater than the score ep, the output S of the comparison circuit CMP1 is 1, so
The selection circuit MUXU1 selects the character code eill, and the selection circuit MUXU2 selects the score ep1. That is, in the comparison circuit CMP1 and the selection circuits MUXUI and MUXU2, the larger one of the values added from the left and right sides (the left and right of the previous stage) is selected and added to the selection circuits MUXU3 and MUXU4. Calculations in embodiments of the invention use two's complement numbers. Therefore, when it is preliminarily reset, minus 1 is stored in the flip-flop FFUI (
(Score ep is minus 1) At this time, all 8 bits of output are 1, so the output of AND gate ANDU1 is 1, and the result is added to selection circuits MUXU3 and MUXU4.
selects the signal to which terminal 1 is applied. That is, the higher score selected by the selection circuits MUXUI and MUXU2 and its character number are selected, and the score is added to the flip-flop FFUI and the character number is added to the flip-flop FFU2. Also, when it is not minus 1, and gate A
Since the output of NDU1 is 0, the selection circuits MUXU3 and MUXU4 select the signal at the 0 terminal. Flip-flop FFU1. The output of FFU2 is MUXU4゜MUXU3
When the output of the AND gate ANDI is 0, the outputs of the flip-flops FFUI and FFU2 are selected. The output of the selection circuit MUXU3 is connected to the input of the flip-flop 1FFU2, and the output of the selection circuit MUXU4 is connected to the flip-flop FF via an OR gate (ORed on a bit-by-bit basis) to which a reset signal er is applied.
Join the UI. When the output of the above-mentioned AND gate ANDUI is 1, that is, when minus 1 is stored in the flip-flop FFUI, the selection circuit MUXU
4 selects the result selected by the selection circuit MUXU2 and stores it in the flip-flop FFUI. As a result, the value (score and character code) of the previous cell is imported, so the flip-flop of the previous cell must be reset.

To reset this, the output of the AND gate ANDUI is output from the AND gate ANDU2. In addition to ANDU3, the output S of the comparison circuit CMP1 is also connected to ANDU2 via inverter INVυ.
Join 3. Also, Antogame) ANDU2. ANDU3
A clock (system clock) is added to , and when the AND gate ANDUI is set to 1, the selected signal r1°rr becomes 1 and resets the flip-flop at the previous stage. That is, the score stored in the flip-flop FFUI is added to the score sorting cell of the next stage, and when that sorting cell is selected and stored, (R) from the next stage is added to the flip-flop FFUI by the OR gate.
) is stored. In other words, when the data is taken in, the previous flip-flop is reset. A system clock CLK is also added to this flip-flop FFUI, and the entire system operates with this system clock.

The case where the sort cell shown in FIG. 9 as described above has eight inputs shown in FIG. 2 will be explained. 1.3 in the first
, 2.9, 5, 8, and 7.6, the higher one is selected in the next clock, and the next stage mill takes in 3.9 and 8.7. The previous stage registers corresponding to cells 3, 9, 8.7 taken in at that time are cleared. That is, 1. -1.
2゜1.5. -1. The value of the register at the previous stage becomes -1.6. Further, in the next clock, 3.9 and 8°7 are compared and 9 and 8 are taken into the next stage. In other words, the first stage is unchanged and the second stage is 3-1. -1°7 and the third row is 9.
It becomes 8 (3). Also, since the cells that output 9 and 8 have been reset, they become l and 2 and 5 are output in the next clock.
is taken in. As a result, the first stage is 1. -1. -1
゜1, -1. -1. -1.6 and the second stage is 3.2゜5
．． 7. The third row is -1, 8, and the fourth row is 9 (4). Subsequently, 9 is taken in by the next clock. At the same time, 3.2 in the second stage is compared in the third stage, 3 is taken into the next stage, the value in the second stage becomes -1, and 9 is similarly taken in, so the value in the fourth stage becomes -1. becomes (5), and the next 6 times becomes 8. Similarly, -1 in the second stage changes, and 1 in the first stage, which is the previous stage, is stored in the second stage (6). Subsequently, by taking in 8, the final stage (fourth stage) in which this 8 is stored becomes -1.

At this time, -1 in the third row becomes 7 (7).

In other words, 7 is taken from the second stage, which is the previous stage, and 7 is taken from the third stage.
becomes. At this time, since 7 in the second stage has been taken in, it is reset and becomes -1. Subsequently, the fourth stage cell selects and takes in 7 with the next clock.

At the same time, 7 in the third row is set to -1. Similarly, -1 in the second stage takes in 6 (8). As described above, while sequentially corresponding to and capturing the clock, the previous stage is set to -1,
Since the comparison is made again, the higher color is selected in order, and finally the results of the score calculation cells can be obtained in the order of the higher colors. The above-mentioned scores are for sorting, that is, for selecting candidate characters.At the same time as the above-mentioned scores are taken in, character codes are also taken in, and the final result is to sequentially output character numbers. As described above, according to the present invention, the scores are obtained for each character, character group, or square, and the scores are arranged in descending order (character by character) and output in ascending order, so that candidate characters can be sequentially determined. Furthermore, since the processing is parallel processing or pipeline processing, it can be speeded up.

A plurality of top candidates can be obtained in the form of a code using the above-mentioned specific calculation and the top selection circuit. In summary, this method has the following multiple configurations.

■ A configuration that sequentially calculates and sorts the scores of characters in each square (see Figure 7).

■ A configuration that parallelizes the method in (■) and sorts the results of each parallel process (see Figure 16).

■ Structure IIi, in which a score calculation cell is provided for each character and the score is calculated sequentially for each square (see Figures 12 and 17).

■ A configuration that parallelizes the methods in ■ and sorts the results of each parallel process.

In the above-mentioned methods, the processing time, that is, the number of clocks for obtaining a sorting result, is different. Also, the number of cells to be used for score calculation and sorting is different. The number of cells and their time in these four types of systems will be explained below. Note that in the following, the type of character is K, the number of upper selections is C1, the number of divided characters when divided for parallel processing is S, and the character when divided into three is M.

In the method of ■ Number of cells = 49+C T i + se = K + 49 + C.

In the method of ■, it is divided into three, so the number of cells is ”
(49+C)XS+2 s Tt,,=M+49+C+logS+C. Since it is processed into S difference columns, TR from the 3 sorted
0 shall be selected by EE 5ORT. , which requires the last 25 rings in the second cell count mentioned above. That is, since the input is S, 2S TREE 5ORTs are required in addition to the (49C+C)×S sort cells provided in advance for each parallel processing unit.

In the method of ■ Number of cells = +2 = 3K.

Tim. =49+1ogK. For cell number 2, TREE 5 is used as described above.
Since ORT is required, this is the number required for this purpose.

In the method (2), the method (2) is processed in parallel, that is, M cells are divided into three groups and processed in parallel, so that the number of cells = (M+2M)XS=3MS T1□ = (49+1 ogM)XS+C. The above-mentioned methods (1) to (2) can be selected depending on the purpose. This can be selected depending on the situation, such as shortening the time for high-speed processing or reducing the number of cells to reduce costs. 13th
Table diagram of the number of divisions in the figure (in Figure 13, = 4
096), by changing the number of divisions S, M also changes in inverse proportion. logM at this time, 1
By determining ogMXS, M+1ogS, etc., you can select the cost and speed according to your purpose.As with 0 or more, you can set the target number of cells by changing the number of score calculation cells and top selection circuits to be processed in parallel. can. In other words, selection can be made depending on the scale of the system.

[Effects of the Invention] As described above, according to the present invention, in a device such as a character recognition device, results can be obtained at high speed in the order of high candidates, and for example, recognition candidates can be output at high speed even when the number of characters is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a system configuration diagram of an embodiment of the present invention, FIG. 3 is a configuration diagram of a cell structure circuit network for performing class selection in an embodiment of the present invention, and FIG. 4 is a circuit diagram of a distance calculation cell according to an embodiment of the present invention, FIG. 5 is a processing diagram of a class selection cell according to an embodiment of the present invention, and FIG. 6 is a circuit diagram of a class selection cell according to an embodiment of the present invention. , FIG. 7 is a block diagram of a cell structure circuit network that performs score calculation and sorting according to an embodiment of the present invention, FIG. 8 is a processing block diagram of a score calculation cell according to an embodiment of the present invention, and FIG. FIG. 10 is a processing configuration diagram of a score sorting cell according to an embodiment of the present invention; FIG. 11 is a circuit diagram of a score sorting cell according to an embodiment of the present invention; FIG. 12 is a circuit diagram of a score sorting cell according to an embodiment of the present invention. FIG. 13 is a table diagram of the number of divisions; FIG. 14 is a processing configuration diagram of a score calculation cell according to another embodiment of the present invention; FIG. A circuit configuration diagram of a score calculation cell according to another embodiment of the present invention. FIG. 16 is a configuration diagram of a cell structure circuit network that performs score calculation and sorting. FIG. 17 is a circuit diagram of a cell that performs score sorting according to an embodiment of the present invention. FIG. 18 is a diagram showing the processing configuration of the score sorting cell, FIG. 19 is a diagram showing the circuit configuration of the score sorting cell, and FIG. 20 is an explanatory diagram of the data flow in sorting. 1... Dictionary memory, 2-1.2-2.2-3... Distance calculation means, 3-1.
3-2.3-3 4-1.4-2.4-3 5-1.5-2.5-3... Class selection means, 6-1
．． 6-2.6-3...Score calculation means, 7...Score sorting means.

Claims (1)

[Scope of Claims] 1) A first memory (1) that stores pattern characteristic data and classification numbers, and compares the stored value with the input value, and if the stored value is smaller, stores the value as is. A plurality of series-connected class selection means (3-1 to 3-3, 4-1
4-3, 5-1 to 5-3) and the feature data of the input pattern are added in common, and the distance between the feature data of the pattern stored in the first memory (1) and the input feature data is calculated. The first stages (3-1, 4-) of the plurality of class selection means connected in series
a plurality of distance calculation means (2-1 to 2-3) that add results corresponding to 1 and 5-1), and each class selection means (3-1) connected in series.
5-1, 3-2 to 5-2, 3-3 to 5-3) are added to score calculation means (6-1 to 6-3) for calculating the score corresponding to the feature data of the input pattern. ), and score sorting means (7) for calculating the numbers of the patterns in descending order of the scores obtained by the score calculation means (6-1 to 6-3).
). 2) The recognition device according to claim 1, wherein the first memory (1) stores feature data classified into standard pattern units and codes of patterns belonging to the classes. 3) The recognition device according to claim 1, wherein the dictionary memory (1) stores classes in units of patterns. 4) The recognition device according to claim 2 or claim 3, wherein the class is a unit of squares obtained by dividing a pattern area. 5) The class number selected by the class selection means is added to the same score calculation means in units of serially connected class selection means, and the score calculation means is stored in a second memory that stores the class to which the character belongs on a character-by-character basis. Claim 1, wherein the class selection means determines whether the class inputted from the class selection means is the class to which the character belongs, and when they match, the class selection means performs weighting and accumulation according to the class selection means. The recognition device described. 6) The score sorting means 7 is composed of a plurality of sort cells connected in a winning configuration, and the sort cell has two inputs, and takes in the value with the higher score added from the input, and also the previous sort cell to which the input is added. 2. The recognition device according to claim 1, wherein the recognition device resets the acquired score and outputs the acquired score to the next stage. 7) The recognition device according to claim 5, wherein the score calculation means is provided for each character and sequentially accumulates the score in units of squares into which a pattern area of one character is divided.