JPH03260994A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To store storage data in a shift register into memory to a maximum and to effectively fetch the data by prohibiting the occurrence of a latch signal during a prescribed number of clocks after generating the latch signal last time even when a reset signal is inputted. CONSTITUTION:When the reset signal 13 is inputted, a counter 10 and an address generation circuit 12 are reset after eight clocks, and output Co is issued until the counter 10 is reset. In such the case, the output A of a reset control circuit 30 prohibits the occurrence of the latch signal 14 during two to seven clocks after the signal 13 is inputted. When six clocks are counted after a preceding signal 14 is generated at a time when the signal 13 is inputted, it is recognized that the write of preceding data on the memory is completed. Therefore, all the data in the shift register can be written on the memory by the next signal 13 is inputted. In such a way, cut off data can be effectively fetched.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device in which a memory includes a data serial/parallel conversion circuit and an address counter so as to be able to handle high-speed serial data.

2. Description of the Related Art In recent years, semiconductor memory devices have become popular at low cost, and V
Semiconductor storage devices with built-in serial/parallel conversion circuits and address generation circuits capable of handling high-speed, large-capacity data are increasingly being used in consumer video equipment such as TR.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a semiconductor memory device incorporating the conventional serial-to-parallel conversion circuit and address generation circuit described above will be described below with reference to the drawings, with reference to FIGS. 4 to 6.

As shown in Figure 4, D constitutes an 8-stage shift register.
Data stored in a flip-flop 1 (hereinafter abbreviated as DFF) is transferred to a latch 2 that collectively stores data of eight DFFIs.

The serial data input to DFF 1 is input to serial data input terminal 3, and its timing is based on clock C.
This is done using a clock signal that enters the input terminal 4 of LK. Transfer to the latch 2 is performed using a latch signal input to the input terminal 5 of the latch signal WS. The data stored in the latch 2 is stored in the memory self of the memory via the column decoder 6 of the memory. In FIG. 5, the clock input terminal 4 is the same as that in FIG. 4, and a counter 10 that counts the clock CLK of this clock signal and outputs a signal CO of 1 clock width every 8 clocks is connected to the clock input terminal 4. Vt7 which generates the latch signal WS of latch 2 in FIG.
8 generation circuit 11 and a memory address generation circuit 12 which increments the address every time the signal CO is received. 13 is an input terminal for a reset signal RESET for resetting the J-counter 10 and the address generation circuit 12 and for determining the start point of receiving input data;
4 is the output terminal of the latch signal WS of latch 2 in FIG.
5 is a memory address output terminal. Note that the above circuit is a synchronous circuit that operates at the rising edge of the clock CLK.

How serial data is written to the memory self in the semiconductor memory device configured as above will be explained with reference to FIG. 6 regarding the related operations of the constituent elements. first,
FIG. 6(a) shows the timing of the clock signal CLK, serial data Din, and latch signal WS,
Input data Di is synchronized with the rise of clock CLK.
n are sequentially taken into the DFFI. Latch signal WS is 8
The data of the past 8 clocks inputted every clock is stored in 8 latches 2 at once. FIG. 6(b) shows the state of data being taken into the shift register and latch 2 at each cycle time of the clock signal. WS also serves as a start signal for a memory write operation, and data in latch 2 begins to be written into the memory cell at the address at the time when WS was generated.

The data stored in these eight latches 2 is shown in FIG.
), the data does not change until the next WS is input, so it is only necessary to write the data into the memory self and complete the write operation until the next WS comes.

At this time, the cycle time required for memory writing is designed to be less than eight times the serial data cycle time (clock CLK cycle time).

When the address generation circuit receives the reset signal RESET, it is reset to address O, and from then on, the RESET signal is input again.
The address is incremented every 8 clocks until the address is input.

Problems to be Solved by the Invention However, in the above configuration, when RESET is input, the counter 10 is immediately reset.
Latch signal WS for latching the data written in shift register 1 before RESET is input
is not generated, and the input data written in the shift register 1 until RESET is input is not stored in the memory.

Keeping in mind the issue of intelligence, the present invention provides
The present invention aims to provide a semiconductor memory device having a function of capturing as much data as possible written in the shift register 1 before a reset signal is input.

Means for Solving the Problems In order to achieve the above object of the present invention, there is an n-stage shift register that stores serial data using a clock signal, and n pieces of data stored in this shift register are stored all at once. n latches, a latch control circuit that generates a latch signal that determines the timing of storage in the latches, a memory cell that sequentially transfers and stores data stored in the latches, and an internal address of the memory cell that is The device includes an address generation circuit that generates an address based on the timing of a latch signal, and a reset control circuit that controls the reset timing of this address generation circuit and the latch circuit. As a function of this reset control, when a reset signal is input to this reset control circuit, if m is the number of serial data stored in the shift register until this reset signal is input, the memory cycle time of the memory cell is When the condition of less than m times the data cycle time is satisfied, another second latch signal is generated after inputting the reset signal and before the normally generated first latch signal for data stored in the shift register. It has a means to make it happen.

Effects In the semiconductor memory device of the present invention having the above configuration, when a reset signal is input to the reset control circuit, the latch circuit and address generation circuit are not reset immediately, and the shift register has already been loaded by the time the reset signal is input. The number m of stored data is counted, and if the value of m times the serial data cycle time is larger than the memory cycle time of the memory cell, a latch signal other than a normal latch signal is generated. This is because the operation of sequentially storing serial data in the shift register at the timing of the clock signal and the operation of transferring the data already stored in the latch circuit and storing it in the memory cell are performed at the same time. When the above two operations are input, a condition is found under which the above two operations can be completed successively, and at that time, a latch signal is generated to ensure that the data in the intermediate state is also stored in the memory cell.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 and FIG. 4, which is a drawing of a serial-to-parallel conversion circuit for a semiconductor memory device, which is similar to the conventional example. This embodiment performs serial-parallel conversion in 8-bit units, and if, for example, six or more pieces of new data have been written in the shift register at the time the reset signals R and ESET are input, that data is transferred to the memory. It is designed so that it can be written inside the cell. In other words,
The cycle time for writing to memory is set to less than six times the serial cycle time for serial data.

That is, when the six pieces of data have been written, the writing of the data to the memory has been completed, and a latch signal for taking in these six pieces of data is then generated.

FIG. 1 is a block diagram of one embodiment of the present invention. As shown in FIG. 1, the clock signal CL is input from the clock input terminal 4.
A counter 10 which receives clock signal K and counts the clock CLK and outputs a signal CO of one clock width every 8 clocks, a memory address generation circuit 12 which increments the address by i every time the signal C○, and the counter 10 as a terminal.
and a reset signal RESE for resetting the address generation circuit 12 and determining the start point of input data capture.
Input terminal 13 of T and latch signal WS of latch 2 in FIG.
output terminal 14 and memory address output terminal 15, which are the same as those shown in FIG. In the present invention, RESET is input directly to the counter 10 and address generation circuit 12, whereas in the present invention, RESET is input directly to the reset control circuit 20. The reset control circuit 20 resets the counter 10 and the address generation circuit 12 after eight clocks when RESET is input, and stores the first eight data in eight latches 2 after RESET is input. A signal B is generated for generating the latch signal WS of the counter 10, and a signal A is generated for validating the output signal CO from the counter 10 for two clocks after RESET is input. Furthermore, the latch signal W for latch control is generated by generating the latch signal WS of the latch 2 shown in FIG.
The S generating circuit 21 is configured as follows.

Regarding the semiconductor memory device configured as described above, the related operations of its constituent elements will be described below. As shown in FIG. 2, when the reset I signal RESE7F is input, unlike the conventional example, the counter 10 and the address generation circuit 12 are not reset immediately, but are reset after a series/parallel unit bit. It is reset by a signal B for resetting the counter 10 and the address generation circuit 12 (after 8 clocks in the case of this embodiment). Signal B also serves as the timing for latching the first 8 bits of data after reset. On the other hand, since the counter 10 is not reset immediately even if RESET is input, the output CO of the counter 10 is always outputted once before the counter 10 is reset. Here, the output A of the reset control circuit 20 prohibits the generation of the latch signal WS from 2 clocks to 7 clocks after RESET is input. This is because when a WS occurs three or more clocks after RESET is input, the memory cycle time for writing to the memory self is set to about six times the serial data memo cycle, so it will take until the next WS occurs. This is because the time is less than 5 clocks, which is short and does not satisfy the memory write cycle time. Here, when RESET is input, the previous W
If 6 clocks have passed after the occurrence of S8, the writing of the previous data to the memory self has been completed, and the RESET
After the input, WS is generated and a memory write operation is performed, so the data written to the shift register will be written to the memory cell until RESET is input.

FIG. 3 shows a waveform diagram showing the operating state, and the time values indicate the number of clock cycles from the beginning for each clock frequency.

All waveforms are shown based on this clock cycle time, and the reset signal RESET is generated at the 10th clock cycle. At this time, since the serial data Din has passed 6 clocks or more since the latch signal WS generated before the reset signal RESET, the data AO to A7 that were captured in the latch are memory self, and at the same time, the shift register The data BO-86 taken in is latched by the latch signal WS generated immediately after the reset signal RESET.

As described above, according to this embodiment, the reset signal RESE
Even if T is input, if six clocks have passed since the previous occurrence of WS8, all the input data stored in the shift register before RESET is input can be stored in the memory.

In this embodiment, the serial-to-parallel conversion circuit is explained in 8-bit units, but serial-to-parallel conversion is not limited to 8-bit units, and it is also possible to write to the memory cell when RESET is input. The number of data is also the same as the previous W.
Needless to say, it is not limited to six clocks after the occurrence of S, and can take various values determined by the relationship between the memory cycle time to the memory cell and the serial data cycle time.

As is clear from the detailed description of the invention, the present invention allows even if a reset signal is input, the maximum amount of serial data input to the shift register can be written to the memory cells before the reset signal is input, which is different from conventional methods. It is possible to effectively import data that was previously truncated. In addition, especially when the units of serial/parallel conversion are increased in order to reduce current consumption or handle higher-speed serial data, that is, when the number of serial register stages increases, the proportion of data that is discarded can be reduced. This is particularly effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a serial-parallel conversion control circuit of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams showing the timing of the serial-parallel conversion control circuit of the same embodiment, respectively. 4 is a circuit diagram of a serial-to-parallel conversion circuit of a semiconductor memory circuit common to the present invention and a conventional example, FIG. 5 is a block diagram of a serial-to-parallel conversion control circuit of a conventional example, and FIG.
), (b) is a waveform diagram for explaining the operation timing of the serial-parallel conversion circuit, and FIG. 7 is a timing chart of the serial-parallel conversion control circuit. 3 4 1...D flip-flop constituting a shift register, 2...Latch, 7...Memory cell, 12...Address generation circuit, 2o.・・・
. . . Reset control circuit, 21 . . . Latch signal generation circuit.

Claims (2)

[Claims] (1) n shift registers that store serial data using a clock signal, and n shift registers that store serial data using clock signals;
a latch control circuit that generates a latch signal for storing data in the latches; a memory cell that sequentially stores the data stored in the latches; and a memory cell that sequentially stores data stored in the latches. an address generation circuit that generates an internal address according to the latch signal, and a reset control circuit that controls reset timing of the latch control circuit and the address generation circuit, and the reset control circuit includes an address that is input to the reset control circuit. If the number of serial data stored in the shift register is m before the reset signal is input, and the memory cycle time to the memory cell is less than m times the serial data cycle time, then the A semiconductor memory device comprising means for generating a second latch signal before generating a normal first latch signal for data stored in a shift register. (2) The semiconductor memory device according to claim 1, wherein the time from generation of the second latch signal to generation of the first latch signal is longer than the memory cycle time of the memory cell.