JPH0326178A - Signal processing circuit - Google Patents

Signal processing circuit

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Publication number
JPH0326178A
JPH0326178A JP1161455A JP16145589A JPH0326178A JP H0326178 A JPH0326178 A JP H0326178A JP 1161455 A JP1161455 A JP 1161455A JP 16145589 A JP16145589 A JP 16145589A JP H0326178 A JPH0326178 A JP H0326178A
Authority
JP
Japan
Prior art keywords
circuit
signal processing
signal
control
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1161455A
Other languages
Japanese (ja)
Inventor
Takeshi Kuwajima
桑島 健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1161455A priority Critical patent/JPH0326178A/en
Publication of JPH0326178A publication Critical patent/JPH0326178A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce a hardware scale and power consumption by detecting a mutual delay difference between chrominance signal and luminance signal circuits generated in a digital signal processing course with a digital signal processing means, generating a control signal and controlling a phase shifting circuit. CONSTITUTION:A phase shifting circuit 3 is provided between an analog chrominance signal processing circuit 1 to input analog chrominance signal components and an A-D converter 4, and simultaneously, a control circuit 8 to detect the mutual delay difference between digital chrominance signal and luminance signal processing circuits 6 and 7 is provided in a digital signal processing circuit 11. A mutual delay difference control output detected by the control circuit 8 is inputted through an interface circuit 14 to the control input point of the phase shifting circuit 3. The phase shifting circuit 3 is composed of, for example, a coil and a variable capacity element, and the capacity value of the variable capacity element is controlled by the control signal after smoothed. Thus, the compensating action of the delay difference can be executed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、信号処理回路に関し、特にアナログ信号処理
、及びディジタル信号処理を含む信号処理回路の遅延制
御に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit, and particularly to delay control of a signal processing circuit including analog signal processing and digital signal processing.

〔従来の技術〕[Conventional technology]

近年、画像処理のディジタル化は、特に急速に進んでお
り、それに伴い、家庭用映像磁気記録再生装置(以下V
TRという)やTV受像機等の民生用画像分野において
も、デイジタル信号処理が導入されてきている.ここで
VTRにおけるデイジタル信号処理の従来例について、
第4図により説明する. 第4図はVTRにおける再生信号処理系のブロック図を
示している.図において、アナログ色信号処理回路1は
、VTR磁気テープに記録され低域変換された色信号成
分を入力端子25から入力し、増幅,振幅制御,帯域制
限等を処理を行う.また、アナログ輝度信号処理回路2
は、VTR磁気テープに記録されたFM′lR調された
輝度信号戒分を端子26から入力し、増幅.fja幅制
御,帯域制限等の処理を行う.これらアナログ色信号処
理回路1及びアナログ輝度信号処理回路2の各出力は、
それぞれ予め定められたサンプリング周波数により動作
するA−D変換器4.5によってデイジタル信号に変換
される.デイジタル信号に変換された色信号戒分は、デ
イジタル色信号処理回路6により、色副搬送波信号に復
元されると共に、ノイズ戒分除去等が行なわれた後、遅
延調整回路1つ及び出力回路9を介して、D−A変換器
12に入力され、ここでアナログ色信号に変換され、再
生色信号として出力される. 一方、ディジタル信号に変換された輝度信号成分は、デ
ィジタル輝度信号処理回路7により、FM復調,ディエ
ンファシス処理、ノイズ戒分除去.ドロップアウト補償
処理等が行なわれた後、出力回1i′810を介してD
−A変換器l3に入力され、ここでアナログ輝度信号に
変換され、再生輝度信号として出力される。また、再生
色信号と再生輝度信号を、加算回路15により加算し、
複合信号(コンボジット信号)を得ている.〔発明が解
決しようとする課題〕 上述した従来例における輝度信号処理系は、色信号処理
系に対し処理工程が多く、特に高画質化のために、例え
ばメモリ回路を用いて輝度信号の相関関係を用いた処理
を行った場合、更に処理工程が増加する.このため相対
的に色信号処理が輝度信号処理系よりも時間的に早く処
理され、D−A変換器12.13における両信号のタイ
ミングを合わせるため、図に示す様に、色信号処理系に
対して、遅延調整回路19を必要とする.ディジタル信
号処理による遅延調整方法として、例えばシフトレジス
タ等が考えられるが、通常VTRにおいて、色信号処理
系に対しての量子化ビット数は、画質上8ビット以上必
要とするため、このようなシフトレジスタ回路規模は、
相当の大きさになる.また、かかる信号処理に要するハ
ードウェアのコストを低減させるため、ディジタル色信
号処理回路6,ディジタル輝度信号処理回路7,出力回
路9,10および遅延調整回路19により楕或されるデ
ィジタル信号処理回路11aの全部、或いは一部を半導
体集積回路により実現する場合、VTRでの画像信号帯
域上、サンプリング周波数は例えば色副搬送波周波数の
4倍、すなわち、約14.3MHZと高速動作となり、
遅延調整回路19での消費電力も大きくなり、回路規模
増大、及び消費電力増大両面で制約を受けるという欠点
があった. 本発明の目的は、画像信号処理における色信号と輝度信
号の様に、複数のアナログ信号をディジタル信号化し、
各々所望の処理を行った後、再びアナログ信号に復元す
る回路において、ディジタル信号処理過程で発生する相
互の処理時間差、すなわち相互の遅延差をディジタル信
号処理手段で検出して制御信号を生戒してインターフェ
ース回路を介して移相回路を制御信号し、ディジタル信
号処理過程での遅延差を予め移相回路にてアナログ処理
により補正をかける事によって、ハードウェア規模の低
減、及び消費電力の低減を可能とした信号処理回路を提
供することにある。
In recent years, the digitalization of image processing has progressed particularly rapidly, and with this, home video magnetic recording and reproducing devices (hereinafter referred to as V
Digital signal processing has also been introduced in the field of consumer images such as TR) and TV receivers. Here, regarding the conventional example of digital signal processing in VTR,
This will be explained using Figure 4. Figure 4 shows a block diagram of the reproduced signal processing system in a VTR. In the figure, an analog color signal processing circuit 1 inputs a color signal component recorded on a VTR magnetic tape and subjected to low frequency conversion from an input terminal 25, and performs processing such as amplification, amplitude control, and band limitation. In addition, the analog luminance signal processing circuit 2
inputs the FM'IR modulated luminance signal recorded on the VTR magnetic tape from the terminal 26 and amplifies it. Performs processing such as fja width control and bandwidth restriction. Each output of these analog color signal processing circuit 1 and analog luminance signal processing circuit 2 is as follows.
Each of the signals is converted into a digital signal by an A-D converter 4.5 operating at a predetermined sampling frequency. The color signal signal converted into a digital signal is restored to a color subcarrier signal by a digital color signal processing circuit 6, and after noise removal and the like are performed, it is sent to one delay adjustment circuit and an output circuit 9. is input to the D-A converter 12, where it is converted into an analog color signal and output as a reproduced color signal. On the other hand, the luminance signal component converted into a digital signal is subjected to FM demodulation, de-emphasis processing, noise elimination, and so on by a digital luminance signal processing circuit 7. After dropout compensation processing etc. are performed, D is output via the output circuit 1i'810.
-A converter l3, where it is converted into an analog luminance signal and output as a reproduced luminance signal. Further, the reproduced color signal and the reproduced luminance signal are added by an adder circuit 15,
A composite signal is obtained. [Problems to be Solved by the Invention] The luminance signal processing system in the conventional example described above has more processing steps than the color signal processing system. If processing is performed using , the processing steps will further increase. For this reason, the color signal processing system is relatively faster than the luminance signal processing system, and in order to match the timing of both signals in the D-A converters 12 and 13, the color signal processing system is processed as shown in the figure. In contrast, the delay adjustment circuit 19 is required. As a delay adjustment method using digital signal processing, for example, a shift register can be considered, but normally in a VTR, the number of quantization bits for the color signal processing system requires 8 bits or more for image quality. The register circuit scale is
It becomes quite large. In addition, in order to reduce the cost of the hardware required for such signal processing, a digital signal processing circuit 11a is configured by a digital color signal processing circuit 6, a digital luminance signal processing circuit 7, output circuits 9 and 10, and a delay adjustment circuit 19. When all or a part of the image signal is realized by a semiconductor integrated circuit, the sampling frequency is, for example, four times the color subcarrier frequency, or about 14.3 MHz, which is a high-speed operation due to the image signal band of the VTR.
The power consumption in the delay adjustment circuit 19 also increases, which has the drawback of being constrained by both an increase in circuit scale and an increase in power consumption. The purpose of the present invention is to convert a plurality of analog signals into digital signals, such as color signals and luminance signals in image signal processing,
After each desired process is performed, in the circuit that restores the analog signal again, the digital signal processing means detects the mutual processing time difference, that is, the mutual delay difference, which occurs in the digital signal processing process, and the control signal is A control signal is sent to the phase shift circuit via the interface circuit, and the delay difference in the digital signal processing process is corrected in advance by analog processing in the phase shift circuit, thereby reducing the hardware scale and power consumption. The object of the present invention is to provide a signal processing circuit that makes possible the following.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の信号処理回路は、第1のアナログ信号を入力す
る移相回路と、この移相回路の出力を入力しこのアナロ
グ信号をディジタル信号に変換する第1のA−D変換器
と、第2のアナログ信号をディジタル信号に変換する第
2のA−D変換器と、これら第1および第2の各A−D
変換器の出力をそれぞれ入力とする第1および第2のデ
ィジタル信号処理回路群と、これら第1および第2のデ
ィジタル信号処理回路群の各出力を入力して各ディジタ
ル信号をアナログ信号にそれぞれ変換する第1および第
2のD−A変換器と、前記第1,第2のディジタル信号
処理回路群の各々が要する信号処理時間の差分情報を生
戒する制御手段とを備え、この制御手段からの制御信号
が、インターフェース回路を介して前記移相回路の制御
入力に入力されてその信号移相が制御される事を特徴と
する. 〔実施例〕 次に、本発明について、図面を参照して説明する。
The signal processing circuit of the present invention includes a phase shift circuit that inputs a first analog signal, a first A-D converter that inputs the output of this phase shift circuit and converts the analog signal into a digital signal, and a second A-D converter that converts the second analog signal into a digital signal, and each of the first and second A-D converters;
First and second digital signal processing circuit groups each receiving the output of the converter, and converting each digital signal into an analog signal by inputting each output of the first and second digital signal processing circuit groups. a first and second D-A converter, and a control means for monitoring the difference information of the signal processing time required by each of the first and second digital signal processing circuit groups; The control signal is input to the control input of the phase shift circuit via an interface circuit to control the phase shift of the signal. [Example] Next, the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図であり、第
4図の従来例と同一の機能動作を行うものは、同一番号
を付してある.本実施例は、アナログ色信号成分が入力
されるアナログ色信号処理回路1とA−D変換器4との
間に移相回路3を設けると共に、ディジタル色信号処理
回路6とディジタル輝度信号処理回路7の相互の処理時
間差、すなわち相互の遅延差を検出する制御回路8をデ
ィジタル信号処理回路11の中に設けている.この制御
回路8によって検出された相互の遅延差制御出力をイン
ターフェース回#!14を介して、移相回路3の制御入
力点に入力し、移相回路3がディジタル信号処理回路1
1において発生する色信号、及び輝度信号の相互の処理
時間差を補償する様に動作させる. ここで制御回路8の動作期間は、外部からの制御信号3
0,例えば水平同期信号等により、所定のタイミング,
期間,制御回路8が制御出力を出す様にすれば良い.こ
の様にして、ディジタル信号処理過程で発生する色信号
、輝度信号処理における相互の処理時間差をアナログ移
相回路3によって補償する事が出来る. 第2図は第1図の制御回路8、インターフェース手段及
び移相回路16の具体構或例を示している.図において
、制御回路8は遅延差検出回路18,PWM変調回路1
7により構成され、遅延差検出回路18は、外部より入
力される制御信号30により動作し、ディジタル信号処
理回路11において発生する色信号、及び輝度信号の相
互の処理時間差を検出する。PWM変調回路17は、遅
延差検出回路18からの検出出力を、PWM信号に変換
した後、制御出力信号として出力する。
FIG. 1 is a block diagram showing one embodiment of the present invention, and parts that perform the same functions and operations as the conventional example shown in FIG. 4 are given the same numbers. In this embodiment, a phase shift circuit 3 is provided between an analog color signal processing circuit 1 to which analog color signal components are input and an A-D converter 4, and a digital color signal processing circuit 6 and a digital luminance signal processing circuit are provided. A control circuit 8 is provided in the digital signal processing circuit 11 for detecting the mutual processing time difference between the signals 7 and 7, that is, the mutual delay difference. The mutual delay difference control output detected by this control circuit 8 is interfaced #! 14 to the control input point of the phase shift circuit 3, and the phase shift circuit 3 is connected to the digital signal processing circuit 1.
The processing time difference between the chrominance signal and the luminance signal generated in 1 is compensated for. Here, the operation period of the control circuit 8 is determined by the control signal 3 from the outside.
0, for example, at a predetermined timing using a horizontal synchronization signal, etc.
The control circuit 8 may output a control output during the period. In this way, the analog phase shift circuit 3 can compensate for mutual processing time differences in color signal and luminance signal processing that occur during the digital signal processing process. FIG. 2 shows an example of a specific structure of the control circuit 8, interface means, and phase shift circuit 16 shown in FIG. In the figure, the control circuit 8 includes a delay difference detection circuit 18 and a PWM modulation circuit 1.
The delay difference detection circuit 18 is operated by a control signal 30 inputted from the outside, and detects the mutual processing time difference between the color signal and the luminance signal generated in the digital signal processing circuit 11. The PWM modulation circuit 17 converts the detection output from the delay difference detection circuit 18 into a PWM signal, and then outputs the signal as a control output signal.

PWM変調回路17からの制御出力を移相回路3に導く
インターフェース手段14として、平滑回路が用いられ
る,PWM変調を受けた制御出力を平滑化した後、移相
回路3の制御入力点に入力している.この移相回路3と
して、例えばコイルと可変容量素子により構或し、平滑
後の制御信号によって可変容量素子の容量値を制御する
事により、遅延差の補償動作を行なわせることができる
. 第3図は本発明の第2の実施例を示すブロック図である
。本実施例は、第1図に示したアナログ色信号処理回路
1及び移相回路3の機能を、同一の半導体集積回路基板
上に楕或したものである。
A smoothing circuit is used as the interface means 14 for guiding the control output from the PWM modulation circuit 17 to the phase shift circuit 3. After smoothing the control output subjected to PWM modulation, the smoothing circuit is input to the control input point of the phase shift circuit 3. ing. The phase shift circuit 3 may be composed of, for example, a coil and a variable capacitance element, and by controlling the capacitance value of the variable capacitance element using a smoothed control signal, it is possible to compensate for the delay difference. FIG. 3 is a block diagram showing a second embodiment of the invention. In this embodiment, the functions of the analog color signal processing circuit 1 and the phase shift circuit 3 shown in FIG. 1 are provided on the same semiconductor integrated circuit board.

図において、端子31より低域変換された色信号が入力
され,前記増幅器20、AGC回路21によって所定の
レベルまで増幅した後、振幅が一定レベルになる様制御
される.振幅が一定になった信号は、フィルタ22によ
り、所定の帯域に制限された後、ジャイレー夕回路23
により、移相調整が行われる.このジャイレータ3は端
子32より入力されるディジタル信号処理回路からの移
相制御信号を平滑回路14により平滑された制御信号に
よって制御される.また、ジャイレータ回路23からの
出力信号は端子33を介してA/D変換器4に入力され
る. この様に前置増幅器20,AGC回路21,フィルタ2
2により構或されるアナログ色信号処理回路と、ジャイ
レータ回路23に゜よる移相手段で構成されるアナログ
信号処理回路1aを同一半導体4A積回路基板上に構成
する事により、本発明の目的のためのハードウェアの規
模或いはコストをより低減する事が出来る. 〔発明の効果〕 以上説明したように、本発明は、複数のアナログ信号を
ディジタル化し、各々所望の処理を行った後、再びアナ
ログ信号に復元する回路において、ディジタル信号処理
過程で発生する相互の処理時間差をディジタル信号処理
手段で検出して制御信号を生威し、この制御信号により
インターフェース回路を介してディジタル信号処理過程
の前過程におかれた移相回路を制御し、ディジタル信号
処理過程での遅延差を予め移相回路にてアナログ処理に
より補正をする事によって、ハードウエア規模の低減、
及び消費電力の低減が可能となる.尚、本発明の一実施
例では、VTR信号処理回路により説明したが、本発明
は、かかる分野のみに限定されない、自由度の大きいも
のである事は言う迄もない.更に、本発明による信号処
理回路は、半導体集MrgI′#1により実現する事に
より、より顕著な効果が得られる.
In the figure, a low-frequency converted color signal is inputted from a terminal 31, and after being amplified to a predetermined level by the amplifier 20 and AGC circuit 21, the amplitude is controlled to be at a constant level. The signal whose amplitude has become constant is limited to a predetermined band by a filter 22, and then sent to a gyroscope circuit 23.
The phase shift adjustment is performed by . This gyrator 3 is controlled by a control signal obtained by smoothing a phase shift control signal from a digital signal processing circuit inputted from a terminal 32 by a smoothing circuit 14. Further, the output signal from the gyrator circuit 23 is input to the A/D converter 4 via the terminal 33. In this way, preamplifier 20, AGC circuit 21, filter 2
The object of the present invention can be achieved by configuring the analog color signal processing circuit 1a constituted by the analog color signal processing circuit 2 and the phase shift means 23 on the same semiconductor 4A integrated circuit board. The scale and cost of hardware for this purpose can be further reduced. [Effects of the Invention] As explained above, the present invention provides a circuit that digitizes a plurality of analog signals, performs desired processing on each signal, and then restores the analog signal. The processing time difference is detected by a digital signal processing means and a control signal is generated, and this control signal is used to control a phase shift circuit placed before the digital signal processing process via an interface circuit. By correcting the delay difference in advance using analog processing using a phase shift circuit, the hardware scale can be reduced.
This also makes it possible to reduce power consumption. Although one embodiment of the present invention has been explained using a VTR signal processing circuit, it goes without saying that the present invention is not limited to only this field and has a large degree of freedom. Furthermore, the signal processing circuit according to the present invention can achieve more significant effects by implementing it using the semiconductor integrated circuit MrgI'#1.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
本実施例の制御回路の部分を示すブロック図、第3図は
本発明の第2の実施例のアナログ信号処理回路部分を示
すブロック図、第4図は従来例の信号処理回路を示すブ
ロック図である。 1,1a・・・アナログ色信号処理回路、2・・アナロ
グ輝度信号処理回路、3・・・移相回路、4 5・・・
A−D変換器、6・・・ディジタル色信号処理回路、7
・・・ディジタル輝度信号処理回路、8・・・制御回路
、9,10・・・出力回路、11,lla・・・ディジ
タル信号処理回路、12.13・・・D−A変換器、1
4・・・インターフェース回路(平滑回路)、]5・・
加算回路、17・・・PWM変調回路、18・・遅延差
検出回路、1つ・・・遅延調整回路、20・・・前置増
幅器、21・・・AGC回路、22・・フィルタ、23
・・・ジャイレータ回路、25〜33・・・入出力端子
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a control circuit portion of this embodiment, and FIG. 3 is a block diagram showing an analog signal processing circuit portion of a second embodiment of the present invention. FIG. 4 is a block diagram showing a conventional signal processing circuit. 1, 1a... Analog color signal processing circuit, 2... Analog luminance signal processing circuit, 3... Phase shift circuit, 4 5...
A-D converter, 6...Digital color signal processing circuit, 7
...Digital luminance signal processing circuit, 8...Control circuit, 9,10...Output circuit, 11,lla...Digital signal processing circuit, 12.13...D-A converter, 1
4...Interface circuit (smoothing circuit), ]5...
Addition circuit, 17... PWM modulation circuit, 18... Delay difference detection circuit, one... Delay adjustment circuit, 20... Preamplifier, 21... AGC circuit, 22... Filter, 23
... Gyrator circuit, 25-33... Input/output terminal.

Claims (3)

【特許請求の範囲】[Claims] (1)第1のアナログ信号を入力する移相回路と、この
移相回路の出力を入力しこのアナログ信号をディジタル
信号に変換する第1のA−D変換器と、第2のアナログ
信号をディジタル信号に変換する第2のA−D変換器と
、これら第1および第2の各A−D変換器の出力をそれ
ぞれ入力とする第1および第2のディジタル信号処理回
路群と、これら第1および第2のディジタル信号処理回
路群の各出力を入力して各ディジタル信号をアナログ信
号にそれぞれ変換する第1および第2のD−A変換器と
、前記第1、第2のディジタル信号処理回路群の各々が
要する信号処理時間の差分情報を生成する制御手段とを
備え、この制御手段からの制御信号が、インターフェー
ス回路を介して前記移相回路の制御入力に入力されてそ
の信号移相が制御される事を特徴とする信号処理回路。
(1) A phase shift circuit that inputs a first analog signal, a first A-D converter that inputs the output of this phase shift circuit and converts the analog signal into a digital signal, and a second analog signal that converts the analog signal into a digital signal. a second A-D converter that converts into a digital signal, first and second digital signal processing circuit groups that receive the outputs of the first and second A-D converters, respectively; first and second D-A converters that input the respective outputs of the first and second digital signal processing circuit groups and convert each digital signal into an analog signal, and the first and second digital signal processing circuits; control means for generating difference information on the signal processing time required by each of the circuit groups, and a control signal from the control means is inputted to the control input of the phase shift circuit via an interface circuit to shift the signal phase. A signal processing circuit characterized by being controlled.
(2)制御手段が第1、第2のディジタル信号処理回路
群の信号処理時間の差分情報を生成してこれをPWM変
調して出力するものであり、インターフェース回路が平
滑手段からなる請求項(1)記載の信号処理回路。
(2) The control means generates difference information between the signal processing times of the first and second digital signal processing circuit groups, PWM-modulates it, and outputs it, and the interface circuit comprises a smoothing means ( 1) The signal processing circuit described above.
(3)移相回路が少くとも可変容量素子を含み、制御手
段からの制御信号によりその可変容量素子の容量値を制
御するものである請求項(1)および(2)記載の信号
処理回路。
(3) The signal processing circuit according to claims (1) and (2), wherein the phase shift circuit includes at least a variable capacitance element, and the capacitance value of the variable capacitance element is controlled by a control signal from the control means.
JP1161455A 1989-06-23 1989-06-23 Signal processing circuit Pending JPH0326178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1161455A JPH0326178A (en) 1989-06-23 1989-06-23 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1161455A JPH0326178A (en) 1989-06-23 1989-06-23 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPH0326178A true JPH0326178A (en) 1991-02-04

Family

ID=15735433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1161455A Pending JPH0326178A (en) 1989-06-23 1989-06-23 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPH0326178A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04319870A (en) * 1991-04-18 1992-11-10 Fujitsu General Ltd Dc level detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04319870A (en) * 1991-04-18 1992-11-10 Fujitsu General Ltd Dc level detecting circuit

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