JPH03263149A - Erroneous write preventing circuit for memory - Google Patents

Abstract

PURPOSE:To prevent the malfunction caused by a fault of a memory by inhibiting write of an E<2>PROM in the case operation to the E<2>PROM becomes unstable due to a voltage drop by operating a three-state buffer, and grounding its output. CONSTITUTION:When a power supply voltage exceeds a prescribed voltage, a power supply voltage monitoring circuit 4 controls a relay 7 and outputs an earth as a control signal to a control terminal 2 from an output terminal 5, and sets a three-state buffer 3 to a conducting state. On the other hand, when the power supply voltage is below the prescribed voltage, an earth is output to an output terminal 6 by the relay 7 and an output of the three-state buffer 3 is set to an earth state. Accordingly, when the power supply voltage exceeds the prescribed voltage, a write control signal is inputted to a write inhibit terminal 8 of an E<2>PROM 9, and when the power supply voltage is below the prescribed voltage, the write inhibit terminal 8 is also grounded and becomes a write inhibited state. In such a way, a fault of a write operation caused by a power source fluctuation of the E<2>PROM 9, etc., can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory write error prevention circuit, and particularly to a memory error write prevention circuit for preventing write operation failures due to power fluctuations in E2 PROM, which is an electrically erasable FROM. The present invention relates to a write protection circuit.

[Conventional technology]

Conventionally, this type of memory error write prevention circuit has E2
A write control signal to FROM was input from the I10 port to the inhibit terminal to inhibit writing.

[Problem to be solved by the invention]

The conventional memory error write prevention circuit described above is E2
Since the write control signal that is input to the inhibit terminal of PROM is input from the I10 port, if the power supply voltage drops temporarily, the operation of E2 FROM may become unstable, causing a malfunction when writing to the memory. There is sex. Furthermore, since the inhibit terminal cannot be controlled even when a live wire is inserted or removed, there is a possibility of a writing malfunction as well.

[Means to solve the problem]

The memory error write prevention circuit of the present invention includes a power supply voltage monitoring circuit that outputs a first or second control signal when the power supply voltage is above a certain voltage and when it is below a certain voltage, respectively; a relay that outputs a first or second earth signal according to the second control signal, and outputs a write control signal that is input from the outside while receiving the first earth signal that is input to the control terminal. and a three-state buffer that grounds the output of the write control signal while receiving the second ground signal, and controls supply of the write control signal to the inhibit terminal of the memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, the three-state buffer 3 connects the input terminal 1 to E2.
A write control signal to PROM9 is input, and
A control signal, which will be described later, is input to the control terminal 2. On the other hand, when the power supply voltage is above a certain voltage, the power supply voltage monitoring circuit 4 controls the relay 7 to output the ground voltage from the output terminal 5 to the control terminal 2 as a control signal, thereby making the three-state buffer 3 conductive. On the other hand, when the power supply voltage is below a certain voltage, the relay 7 outputs earth air to the output terminal 6 to ground the output of the three-state buffer 3.

Therefore, when the power supply voltage is above a certain voltage, E2PRO
A write control signal is input to the write inhibit terminal 8 of M9, and when the voltage is below a certain level, the write inhibit terminal 8 is also grounded and the write is prohibited.

〔Effect of the invention〕

As explained above, the present invention has a power supply voltage monitoring circuit and a relay that operates under the control of this monitoring circuit, thereby operating a three-state buffer or grounding this output to reduce voltage drop. by E2 PR
E2 PR when operation to OM becomes unstable
Writing to the OM is prohibited to prevent malfunctions due to memory failures.

Also, when inserting or removing live wires, E2 FROM
Since the inhibit terminal is fixed to the ground, it also has the effect of preventing erroneous writing.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Control terminal, 3... Three-state buffer, 4... Power supply voltage monitoring circuit, 5, 6
...Output terminal, 7...Relay, 8...Write inhibit terminal, 9-E" FROM.

Claims (1)

[Claims] a power supply voltage monitoring circuit that outputs a first or second control signal when the power supply voltage is above a certain voltage or below a certain voltage, respectively; A relay that outputs a geosignal, and a relay that outputs a write control signal input from the outside while receiving the first geosignal signal input to a control terminal, and outputs a write control signal input from the outside.
and a three-state buffer that grounds the output of the write control signal in a state where the ground signal is received, and controls supply of the write control signal to an inhibit terminal of the memory. prevention circuit.