JPH0326413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to the configuration of an interrupt request event queue control circuit used in, for example, a processor of a communication control device.

(Prior Art) Conventional queue control circuits of this type are configured using FIFO (first-in first-out) memory as the queue memory. However, when applying this to a device in which asynchronous interrupt requests occur sequentially from lines, and the frequency of occurrence increases in proportion to the increase in the number of lines, it is necessary to queue the interrupt request events. The FIFO memory capacity increases significantly as the number of lines increases, so it has the disadvantage of being expensive when accommodating a large number of lines.
For interrupt request events registered in FIFO,
If the event no longer needs to be processed, it is physically impossible to cancel the event, so it is necessary to check whether the event has been requested to be canceled when outputting the event from the FIFO. If this were to be done using hardware, there would be the disadvantage that it would further increase the amount of hardware and cause a decrease in performance.

(Object of the Invention) In order to solve these drawbacks, the present invention suppresses the increase in the amount of hardware in the queue control circuit, and also facilitates the processing of registering interrupt request events in queues, outputting them from queues, and invalidating them. The drawings will be described in detail below.

(Structure and operation of the invention) Figure 1 shows a control word (referred to as an interface command word) for notifying a processing request event.
It's called ICW. ), which consists of a 2-bit type identification code field A, a 4-bit processing request destination field B, an 8-bit interrupt factor code field C, and a 12-bit path number field D.

The type identification code field A indicates whether the ICW is for a processing request or a cancel request, and if it is for a processing request, it is registered in the queue. If it is for a cancellation request, it is already registered in the queue.
Among the ICWs, the processing request destination field B, which cancels the ICW corresponding to the cancellation type specified in that field, indicates the request destination for the processing of the ICW, and the queue to be registered can be identified by this field. Interrupt cause code field C is
This field indicates the factor that generated the ICW, and allows you to identify the type of processing request. Pass number field D indicates the line number etc. that generated the processing request.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, where 1 is an ICW holding register that holds ICW from an external circuit, and 2 is an ICW holding register that holds the correspondence between the processing request destination and the registered queue. It is a conversion circuit that can identify whether the processing request destination is undefined, addressed to another module, or to which group of queues within its own queue. 3 is a queue memory for queuing ICW, which is grouped into 8 queues and fixedly allocated. 4 outputs to external circuit
The ICW output register 5 is an address holding circuit that holds pointers for each of the eight queues on the memory 3, and consists of a reading 5-1 and a writing 5-2, each queue pointer being the read address of the ICW in the queue. and write address are held as a pair. 6 is a stack pointer register for temporarily holding a pointer when reading and writing the contents of the queue memory 3;
1 and 6-2 for writing, it has an incrementer, 7 is a cancel register that holds ICW for cancel, 8 is a comparator that compares the contents of ICW output register 4 and the contents of cancel register 7, and 9 is a cancel register. a control circuit; 10 is a queue control circuit that controls the address holding circuit 5 and ICW registration, output, etc.; 11 is a comparator that compares the values of the ICW read address and write address in the address holding circuit 5; 13 is an external circuit.

Next, the operation example shown in FIG. 2 will be explained.

When the ICW is output from the external circuit 12, the queue control unit 10 identifies the processing request destination field in the ICW using the conversion circuit 2, and if it is addressed to the local queue,
Latch the ICW in ICW holding register 1.

Figure 3 shows the relationship between the processing request destination and the registered queue.
Read RAM contents as RAM address.

The conversion circuit 2 needs to maintain the correspondence between the processing request destination and the registered queue, and at the time of initial setting, the
It is necessary to write the conversion code shown in (b).

Next, enter the ICW type identification code field A.
If it is a processing request type ICW, it checks whether the corresponding queue overflows or not. If it does not overflow, it returns an acknowledgment to the external circuit and addresses the queue pointer corresponding to the processing request destination. It is read from the holding circuit 5 and set in the stack pointer register 6. The queue memory 3 pointed to by the contents of the write address in the stack pointer register 6
The ICW held in the ICW holding register 1 is written, and the contents of the stack pointer register 6 are incremented and written to the address holding circuit 5.

Through the above processing, ICWs having the same processing request field value can be registered in the corresponding queues in the queue memory 3 in the order of occurrence. Further, as shown in FIG. 3, since the correspondence between the processing request destination and the registered queue can be changed by changing the contents of the conversion circuit 2, the correspondence between the processing request destination and the interrupt priority order can be changed arbitrarily. Note that if the registration request destination queue overflows, the registration operation is not performed, and the queue overflow flag of the corresponding processing request destination is set to "1" to generate a queue overflow interrupt to the external processor. The interrupt processing program running on the processor needs to recover the ICW that caused the interrupt.

In order to output the ICW registered in the queue memory 3 in order to issue an interrupt request to an external processor, the following operation is performed. An interrupt level corresponding to the interrupt level of the processor is set in advance for each queue in the queue memory 3.
If a valid ICW exists in the queue memory 3, a request is made to the processor for an interrupt of the highest priority level among the queues in which the valid ICW exists. When receiving an interrupt enable signal from the processor, the corresponding queue pointer is read from the address holding circuit 5 and set in the stack pointer register 6. The ICW is read from the location in the queue memory 3 pointed to by the contents of the read address of the stack pointer register 6, and set in the ICW output register 4, and the contents of the stack pointer register 6 are incremented and written to the address holding circuit 5. It's crowded. The control word set in ICW output register 4 is removed from queue memory 3. As a result of the above processing, the oldest registered ICW within the same queue is always read out.

Next, if the ICW output from the external circuit is a cancel type ICW, the cancel control circuit 9 applies the corresponding ICW based on the cancel ID specified in the type identification code field A of the ICW.
Disable it. Invalidation means rewriting the interrupt cause code in the ICW to a certain specific value, such as X'FF'.

The cancellation ID is ICW, as shown in Figure 1.
is specified by the type identification code field A.
The cancel type ICW latched in ICW holding register 1 is set in cancel register 7 unless cancel processing is in progress. The address holding circuit 5 causes the cancel register 7 to
The read address of the queue memory 3 corresponding to the ICW processing request destination is obtained, the ICW in the queue memory 3 pointed to by the read address is read out, and set in the ICW output register 4. The contents set in the cancel register 7 and the contents of the ICW output register 4 are compared according to the cancel ID, and if the comparison results are equal, the interrupt factor code of the ICW is rewritten to X'FF'.

Thereafter, the above operation is continued until the write address of the queue in the address holding circuit 5 matches.
If a cancel request is received during cancel processing, the cancel processing is not performed and an interrupt indicating that the cancel processing is busy is generated to the external processor.

(Effects) As explained above, according to the present invention, a processing request event is registered in a queue corresponding to a processing request destination within a processing request event, so that a plurality of mutually independent queues are stored in one queue memory. queues can be configured. Furthermore, since the correspondence between interrupt levels and processing request destinations can be easily changed by a program, flexible system design is possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a specific example of a control word (ICW) for notifying a processing request event, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
FIG. 6 is a diagram showing a specific example of the relationship between a processing request destination and a registration destination queue in the ICW. 1...ICW holding register, 2...Conversion circuit,
3...Queue memory, 4...ICW output register,
5... Address holding circuit, 6... Stack pointer register, 7... Cancel register, 8, 1
1...Comparator, 9...Cancel control circuit, 10
...Queue control circuit, 12, 13...External circuit.

Claims (1)

[Scope of Claims] 1. A register section that holds a control word consisting of a type identification code, a processing request destination, an interrupt cause code, and a path number as means for notifying an interrupt request event, and a register section that holds a control word consisting of a type identification code, a processing request destination, an interrupt cause code, and a path number, and a plurality of groups of the control words. a control word storage unit capable of storing the control word in the same manner as the control word storage unit; an address holding circuit that holds write addresses and read addresses of the control word storage unit as many as the number of groups in the control word; and a control word processing request destination. Correspondingly, when the control word whose type identification code indicates an interrupt request is input from an external circuit to the register section, the control word is inputs the processing request destination within to the conversion circuit, and if the output indicates a registration request in the self-control circuit and the corresponding group area of the storage section is not in an overflow state, returns an affirmative response to the external circuit. With,
The write address of the corresponding group area of the storage unit is obtained from the address holding circuit corresponding to the value of the processing request destination, and the control word is written to the position of the address, and the corresponding storage unit is in an overflow state. If this is the case, an overflow interrupt is generated to the external circuit without writing, and if the control word exists in the storage section, the control word is transferred from the address holding circuit to the external circuit according to the processing priority for each group set in advance. Find the read address of the storage section, read the control word corresponding to that address,
A queue control circuit characterized by making an interrupt request to an external circuit. 2. As a means for notifying an interrupt request event, there is a register section that holds a control word consisting of a type identification code, a processing request destination, an interrupt cause code, and a path number, and a register section that stores a plurality of control words in groups. an address holding circuit that holds the write addresses and read addresses of the control word storage for the number of groups in the control word; It consists of a conversion circuit for determining the group number in the storage unit, and in the case of a cancellation request for a control word whose type identification code is already stored in the control word storage unit, a cancel register is provided to distinguish the control word. , in a queue control circuit that holds the control word in its cancel register, the combination specified by the type identification code among the processing request destination, interrupt cause code, and path number of the control word held in the cancel register. 1. A queue control circuit, wherein the queue control circuit performs an invalidation process on all control words existing in the control word storage unit that match the cancel ID, using the cancel ID as the cancel ID.