JPH0326418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a fault indication system, and more particularly, to a fault indication system, and more particularly, to a fault indication system, and more particularly, to a switching system comprising a central control unit, main memory, input/output control unit, etc. connected to a common system bus. The present invention relates to a failure display system for each device such as a processing system or an information processing system.

Prior Art and Problems Conventionally, in the above-mentioned information processing systems, when a device included in the processing system encounters a failure or malfunctions, the faulty or malfunctioning device issues an interrupt to the central control unit. The central control device diagnoses the device that issued the interrupt request, and if a fault is detected, drives a fault visual display element of a separately provided fault display device corresponding to the affected device. For example, lighting an indicator lamp or light emitting diode (LED). In order to display that a certain device has a problem on the fault display device, the central control device receives an interrupt request, starts a diagnostic program to perform diagnosis according to the cause of the interrupt, and detects the fault. Processing must be performed to detect the device. For this reason, the conventional technology has the disadvantage that the processing load on the central control unit for displaying faults is considerably increased.

OBJECTS OF THE INVENTION The present invention eliminates the drawbacks of the prior art fault display methods described above, reduces the processing load on a central control unit for displaying faults on a device-by-device basis, and can be easily adapted to various situations. The purpose is to provide a highly flexible failure display method.

Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an overview of the connection configuration of an example of an information processing system embodying the present invention, FIG. The figure is an explanatory diagram of an example of a method of configuring addresses and commands for display control in an embodiment of the present invention.

In Figure 1, CC is the central control unit, MM ₀ ,
MM ₁ , MM ₂ , and MM ₃ are each a main memory device, and IOC ₀ , IOC ₁ , and IOC ₂ are each an input/output control device, such as a network control device of a switching system, a floppy disk driver, a typewriter, etc. With the control device such as, the above central control device CC
SB is the system bus,
ERD is a fault display device, DS is a fault display consisting of a device-compatible fault display element [lamp or light emitting diode (LED)], MJ is a warning device,
ES is a fault notification line group consisting of fault notification lines that notify each device of fault information, and WS is an operating signal line group consisting of lines that carry signals from each device indicating that it is in operation.

EMA and TF are an emergency control circuit and a clock disconnection detection circuit, that is, a failure detection circuit, provided in the central controller CC, respectively, and PED is a parity error detection circuit provided in the main memory device _MM0 , and the address bus and data bus an error detection circuit for detecting parity errors in data received through the
ED is an error detection circuit that detects command errors and parity errors, and when no fault or error is detected, it sends out "0" (low level signal, e.g. earth), and when an error is detected. sends out a temporary "1" (high level signal, eg +5V) in the form of a pulse.

Central control unit CC is normal, emergency control circuit EMA
and clock disconnection detection circuit TF are each “0”
When outputting 2
OR gate with two outputs as input OR ₁ is “0”
This output “0” is negated by the negation circuit IN ₁ , and becomes “1” to indicate that it is normal.
Notify the fault display device ERD via.

Similarly to the above, the parity error detection circuit provided in the main memory device MM ₀ and the error detection circuit ED provided in the input/output control device IOC ₀ output “0” when no error is detected. , are negated by the negation circuits IN ₂ and IN ₃ and become "1", and the fault notification lines corresponding to the main memory device MM ₀ and the input/output control device IOC ₀ (corresponding to the ES ) is carried to the fault display device ERD.

The other main memory devices MM ₁ , MM ₂ , MM ₃ are also provided with parity error detection circuits (PEDs) (not shown) in the same way as the main memory device MM ₀ , and the other input/output control devices IOC ₁ , IOC ₂ is also provided with an error detection circuit (ED) (not shown) in the same way as the input/output control device IOC ₀ , and its output is sent to the fault display device ERD via the fault notification line group ES via the negative circuit in the same way as above. carried.

As mentioned above, when the fault display device ERD receives a pulsed fault signal from each device via the fault notification line corresponding to the device, it retains this fault information and displays the fault signal corresponding to each device on the fault display device DS. Drives (ignites) the display element (display lamp or LED).

On the other hand, when an error is detected in each device,
An interrupt request is made to the central controller CC via the system bus SB. The central control unit CC that is interrupted by this interrupt request determines whether retry processing is necessary depending on the cause of the interruption, and if necessary, performs retry processing. When retry processing is not necessary, or when retry processing results in permanent error detection rather than temporary failure, the central controller CC
fault indicator ERD through system bus SB
The fault display device ERD sends an alarm sending command to
When this command is received and held, and at least one of the fault visual display elements corresponding to the device is activated and indicates a fault, the alarm device MJ is operated.

If the central controller CC recovers from the error as a result of retry processing and detects that the error or failure is temporary, the central controller CC sends a fault signal reset command to the fault indicator ERD via the system bus SB. is sent, and the fault visual display element in the fault indicator DS, which was being driven by the fault signal, is stopped and extinguished.

Furthermore, when the central control unit CC accesses each device through the system bus SB, if there is no response from the device, it is determined that the device is affected,
The system sends a fault signal set command for the device.
It is sent to the fault display device ERD through the bus SB and drives the corresponding fault visual display element.

In addition, when operating normally, each input/output control device IOC ₀ , IOC ₁ , and IOC ₂ sends an operating signal to the fault display device through the line in the operating signal line group WS.
Output to ERD. This operating signal is a signal in a format different from a continuous signal, for example, an intermittent signal,
This signal causes the corresponding fault visual display element (lamp or LED) to ignite (for example, flash) in a mode different from the fault display, to indicate that the corresponding device is in operation.

Next, the above fault display operation will be explained in detail with further reference to FIGS. 2 and 3.

Figure 2 shows the fault display device ERD shown in Figure 1.
FIG. 2 is a diagram showing an internal connection configuration and a connection relationship with the outside.

In Figure 2, SB is the system bus, ERD
As in FIG. 1, 1 indicates a fault display device, ES indicates a fault notification line group, WS indicates an operating signal line group, and MJ indicates a warning device.

The system bus SB includes, for example, a data bus DB consisting of 8 lines DB0 to DB7 for 8 data bits ₀ to ₇ , and 16 lines _AB0 for 16 bits of address data. ~AB Address bus AB consisting of ₁₅ , RW giving read/write instructions
It consists of a control bus CB consisting of a _φ2 line and a clock line.

In the fault display device ERD, COM is an address verification circuit, AG ₃ to _{AG 6} are AND gates, and E-
FF, CCR-FF, MMR-FF, IOCR-FF are D-type flip-flops, NAG ₀ to _{NAG 8} are NAND gates, CC-FF, MM ₀ -FF, MM ₁ -FF, MM ₂
−FF, IOC ₀ −FF, IOC ₁ −FF, IOC ₂ −FF are preset type flip-flops, OR ₂ , OR ₃ ,
OR ₄ and OR ₅ are OR gates, DS is a device compatible fault display section, and their D-CC, D-MM ₀ , D-
MM ₁ , D-MM ₂ , D-MM ₃ , D-IOC ₀ , D-
IOC ₁ and D-IOC ₂ are device-compatible failure visual display elements,
IN ₄ to IN ₁₁ are the drivers for the above fault visual display elements,
The PC is a photocoupler.

If all the devices with visual fault display elements are normal, all the flip-flops of the fault display device ERD are in the reset state, and the fault signal holding flip-flops such as flip-flops CC-FF, MM ₀ -FF~, etc. Output terminal Q is in a state of outputting "0" (low level), and output terminal Q of flip-flop E-FF for alarm sending is "0".
, flip-flop CCR-FF for display reset,
In MMR-FF and IOCR-FF, their output terminals output "1".

Each driver IN ₄ ~ IN ₁₁ has a corresponding fault signal holding flip-flop CC-FF, MM ₀ -FF~, IOC ₀
-FF~ receives the output "0" from the output terminal Q and outputs "1" (high level), which is output to the fault visual display elements D-CC, D-MM composed of light emitting diodes (LEDs). ₀ , D-MM ₁ , D-MM ₂ , D
-MM ₃ , D-IOC ₀ , D-IOC ₁ , D-IOC ₂ are input to one terminal, but +5V (high level) is input to the other terminal of the above fault visual display element via a resistor.
is being input, so none of them emit light and no failure is displayed (displays during input/output operations will be described later).

Now, suppose that a failure occurs in some device, for example, the main memory device _MM0 , and a parity error is detected in its parity error detection circuit PED. In this case, the output of the circuit PED is temporarily converted from "0" to "1", and a pulse-like fault signal is sent out. This signal is sent to the fault signal holding flip-flop corresponding to the main memory device _MM0 of the fault display device ERD via the line E- _MM0 in the fault notification line group ES.
Given to the preset input terminal P of MM ₀ -FF,
Since the input of terminal P temporarily becomes low level, flip-flop _MM0 -FF is set, and at that time, the signal input to data input terminal D (high level +5V is input) is latched and output. The same signal “1” (high level) from terminal Q
Send out. Therefore, the driver _IN5 outputs "0" and drives the fault visual display element D- _MM0 corresponding to the main memory device _MM0 .

On the other hand, input/output control devices IOC ₀ , IOC ₁ , IOC ₂
The operating signals (intermittent signals) are the lines W-IOC ₀ , W-IOC ₁ , W in the operating signal line group WS, respectively
- From IOC ₂ , drivers IN ₉ , IN ₁₀ , IN ₁₁ are reached via OR gates OR ₃ , OR ₄ , OR ₅ and are intermittently driven to drive fault visual display elements D-IOC ₀ , respectively.
The D-IOC ₁ and D-IOC ₂ are operated in a mode different from the fault display mode (for example, blinking) to display an in-operation display.

The fault display device ERD is controlled from the central controller CC via the system bus SB, such as new fault display control, display erasure, alarm sending, etc., as follows.

FIG. 3 is an explanatory diagram of a method for configuring address data sent from the central controller CC to the address bus and commands sent to the data bus in the above case.

When the central controller CC detects a device failure (such as when no response is obtained even though the central controller CC has accessed it), the address data 1000 is sent as shown in Figure 3A. is assembled into an address register and sent to the address bus AB (FIG. 2), and a fault display command indicating the device to display the fault is assembled into a data register and sent to the data bus DB (FIG. 2). In addition, in order to stop the drive (extinguish) of the faulty visible display element while it is being driven, enter the address data as shown in Figure 3B.
Assemble 1001 into an address register and write the address.
A display stop command is sent to the bus AB (FIG. 2) and a display stop command indicating a faulty visual display element or a group of elements to be stopped (extinguished) is assembled in a data register and sent to the data bus DB (FIG. 2).

I will explain in more detail.

The 16-bit address register (not shown) of the central controller CC is set to 2 as shown in AR in Figure 3A.
1000 as address data with evolved hex code
Assemble. On the other hand, DR in FIG. 3A shows the contents of the 8-bit data register of the central controller CC, and each cell is assigned to each device CC, MM ₀ , MM ₁ , MM ₂ ,
Corresponding to MM ₃ , IOC ₀ , IOC ₁ , IOC ₂ , for example, in the case of a display command that attempts to drive the failure visual display element D-MM ₁ of the main memory device MM ₁ , the central control unit
Set " ₁ " in the position (DB ₂ ) corresponding to MM 1 and "0" in other positions of data register DR (not shown in Figs. 1 and 2) of CC, and issue the above display command. Assemble.

The contents of registers AR and DR are sent to system bus SB. That is, address data 0001 0000 0000 0000 with the content shown by AR in FIG. 3A is sent to each line AB ₁₅ to _{AB 0} of address bus AB.
Data 00000100 (1 only for DB ₂ ) indicating a display command is sent to each line DB ₇ to DB ₀ of the data bus DB.

As shown in Figure 2, the address bus AB line
Data 0001 0000 0000 000 is input to the address verification circuit COM via AB ₁₅ to AB ₁ (excluding AB ₀ ),
It is compared with the identification data set in advance in the address verification circuit COM, and when they match, the data sent to lines DB ₇ to _{DB 0} of the data bus DB is for this fault display device ERD. and outputs “1”. If they do not match, the output does not become "1" and remains "0". At this time, " ₀ " is sent to the remaining line AB0 of address bus AB. “0” is sent to line RW of control bus CB. Therefore, and gate AG ₁
is conductive to the signal on clock line _φ2 of control bus CB, but the AND gate
_AG2 receives "0" from line _AB0 , so its output is "0".

A clock is sent to clock line _φ2 of control bus CB, and if it becomes “1”, it is an AND gate.
AG ₁ outputs “1” and therefore NAND gate
One of the inputs of NAG ₀ to NAG ₇ becomes "1".

At this time, among the lines DB ₀ to _{DB 7} of the data bus DB, "1" is input from DB ₂ and "0" is input from the other lines, and each becomes the other input of the NAND gates NAG ₀ to NAG ₇ . . This allows Nando Gate
Although the output of NAG ₂ changes to "0", the outputs of the other NAND gates NAG ₀ , NAG ₁ , NAG ₃ to _{NAG 7} continue to hold "1" and do not change. When the clock line φ ₂ in the control bus CB goes to “0” and the output to other buses (address bus AB, data bus DB, control bus CB) disappears, the NAND gate NAG ₂ The output returns to "1".

Flip-flop CC-FF, MM ₀ -FF, MM ₂
-FF, MM ₃ -FF, IOC ₀ -FF to IOC ₃ -FF do not change their states and are in the reset state, and the output of their output terminal Q is "0", but the flip-flop MM ₁ -FF is As mentioned above, the input to the clock input terminal C changes from "1" to "0" to "1", so it is set, and the output terminal Q outputs "1" and holds it.

Therefore, only the fault visual display element D-MM ₁ in the fault indicator DS is driven (ignited) and continues to do so.
Even if another device is affected, the same display as above can be made under the control of the central controller CC.

To stop driving (extinguish) the fault visual display element of the fault indicator DS, or to control the alarm device MJ to issue an alarm when there is a display on the fault indicator DS, the procedure is as follows.

In this case, as shown in FIG. 3B, 1001 (binary hexadecimal code representation) is assembled as address data in the address register AR (not shown in FIGS. 1 and 2).

One of the main memory devices MM ₀ to MM ₃ , e.g.
It is assumed that MM ₁ is faulty, the flip-flop MM ₁ -FF is set, and its output drives the fault visual display element D-MM ₁ of the fault indicator DS.

DR in Figure 3B is the central controller in this case.
Indicates the contents of the CC 8-bit data register,
When stopping the drive of the above failure visual display element D-MM ₁ (extinguishing), write 00100000 to cells DB ₇ to DB ₀ of this data register DR [cells MMR corresponding to main memory devices MM ₀ to MM _3] as a command. Set “1” only in (DB ₅ ) and “0” in all other cells]
Assemble data in the form of .

Then, the contents of these registers AR and BR are sent to the system bus SB. In other words, the address
The contents 0001 0000 0000 0001 shown by AR in Figure 3B are sent to each line AB ₁₅ to AB ₀ of the bus AB, and the data 00100000 as the above command is sent to each line DB ₇ to _{DB 0} of the data bus DB. and "0" is sent to the RW line of the control bus CB.

In the fault display device ERD, the data 0001 0000 0000 is sent to the address verification circuit COM via the lines AB ₁₅ to _{AB 1} (excluding AB ₀ ) of the address bus AB.
000 is input and compared with the identification data set in advance in the address verification circuit COM. When they match, the data sent to lines DB ₇ to _{DB 0} of the data bus DB at this time is for this fault display device ERD. , and outputs "1". If they do not match, the output does not become "1" but remains "0". At this time, the remaining lines AB ₀ of data bus AB
Unlike the above, "1" is sent to . Therefore, the AND gate _AG1 becomes non-conductive with respect to the signal input to the AND gate _AG1 from the clock line _φ2 of the control bus CB, and the clock line _φ2
Its output remains "0" regardless of the Therefore, NAND gates NAG ₀ to NAG ₇ are non-conductive, and all their outputs hold "1".

The AND gate AG ₂ receives the output “1” from the address verification circuit COM mentioned above and the “1” from the line AB ₀ .
Since "1", which is the negation of "0" on line RW, is input, its output becomes "1", and this output "1" is input to AND gates AG ₃ to AG ₆ , and the above AND gate AG ₃ is conductive to clock _φ2 ,
AND gates AG ₄ -AG ₆ become conductive to signals from lines DB ₄ -DB ₆ of data bus DB, respectively.

As mentioned above, at this time, only line DB ₅ of lines DB ₇ to _{DB 0} of data bus DB is set to “1”.
is sent, and "0" is sent to the other lines _DB7 to _DB6 and _DB4 to _DB0 .

Therefore, only the output of AND gate AG ₅ is “1”
Therefore, "1" is input to the data/input terminal D of the flip-flop MMR-FF.

In this state, the clock signal on line _φ2 is applied to each clock input terminal C of the flip-flops CCR-FF, MMR-FF, and IOCR-FF.
“1” from line DB ₅ of bus DB to data input terminal D
Only the flip-flop MMR-FF to which is input is set, and the output of its output terminal changes from "1" to "0" and is held.

This output “1” is the flip-flop MM ₀ −
This is applied to the reset terminals R of FF, MM ₁ -FF, MM ₂ -FF, and MM ₃ -FF, and all of these flip-flops, including those that are set, are reset. In this case flip-flop MM ₁ −FF
Since this has been set, this is also reset, and the failure visual display element D- _MM1 is stopped (extinguished).

The failure display elements for the central controller CC and the input/output controllers IOC ₀ to IOC ₂ can be controlled to stop driving (extinguish) in the same manner as described above.
As can be easily understood from the above, it is also possible to configure the failure visual display elements corresponding to each device to perform extinguishing control one by one.
It is also possible to collectively control devices with the same attributes (for example, main storage devices) to turn off the failure visual display elements corresponding to the devices.

Next, the operation of the alarm device MJ will be explained. For example, if the main memory MM ₁ is affected, the corresponding flip-flop MM ₁ −FF is
is set, "1" is output from its output terminal Q, and the corresponding fault visual display element D-MM ₁
is being driven.

On the other hand, if the central controller CC determines that the above failure is not temporary, it assembles 0001 0000 0000 0001 into the address register AR as address data, as shown in FIG.
Assemble the data that has "1" in the cell E (DB ₇ ) and all "0" in the other cells as an alarm command in the register DR, and set the above address data as the address.
The data of the above command is sent to the lines AB ₁₅ to AB ₀ of the bus AB, the data of the above command is sent to the lines DB ₇ to DB ₀ of the data bus DB, and "0" is sent to the RW line of the control bus CB.

In the fault indicator ERD, upon reception of the above signal, a "1" on line DB ₇ of the data bus DB is input to the data input terminal D of the flip-flop E-FF, and on the other hand, as described above, the AND gate AG ₃ is in a conductive state with respect to the clock _φ2 , so when the clock _φ2 is input, the flip-flop E-FF is set, and the output of its output terminal Q becomes "1" and maintains this state.

The signal "1" from the output terminal Q of the flip-flop E-FF becomes one input of the NAND gate NAG ₈ , and the flip-flop MM ₁ -FF
The signal “1” from the output terminal Q of the flip-flop ( _MM1 -FF is indicating a fault, so the output of its output terminal Q is latched at “1”) is output from the OR gate _OR2. It becomes the other input of NAND gate NAG ₈ .

Therefore, the output of NAND gate NAG ₈ is “0”
Then, the light emitting diode of the photocoupler PC emits light, and output is applied to the alarm device MJ, causing it to operate.
issue an alarm. After receiving this alert, the maintenance personnel can check the fault indicator DS.

This alarm can be issued provided that at least one of the devices is affected and that the fault is not a temporary disturbance. The maintenance person can reset the flip-flop E-FF by operating means not shown, and can stop the alarm from the alarm device MJ.

The present invention is not limited to the above-described embodiments, and various modifications are possible.

Effects of the Invention Since the present invention is configured as described above, in an information processing system in which a central control unit, a main storage unit, an input/output control unit, etc. are connected to a common system bus, When a fault display device is provided on a common system bus to display faults in each of the above devices, each of the above devices has a fault notification line (ES) between it and the fault display device. When a fault is detected by the device itself, the fault is notified to the fault display device via the fault notification line and the fault is displayed. According to the present invention, it is no longer necessary for the central controller to issue an interrupt request, detect a fault based on the interrupt request, and then control the fault display to the fault display device via the system bus. This has the effect of significantly reducing the processing load on the central control unit. This is particularly effective for detecting affected devices in systems where each device is housed in a package. Furthermore, the present invention has the advantage of not burdening maintenance personnel in the event of a temporary failure.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of the connection configuration of an example of a processing system implementing the present invention, FIG. 2 is a connection configuration diagram of a fault display device configured according to the present invention in FIG. The figure is an explanatory diagram showing an example of a method of configuring address data and commands for controlling the fault display device to be sent onto the system bus in the above-described embodiment of the present invention. CC...Central control unit, MM ₀ , MM ₁ , MM ₃ ,
MM ₃ ...Main memory, IOC ₀ , IOC ₁ , IOC ₂ ...I/O control unit, SB...System bus, ERD...
...Fault display device, DS...Fault indicator, MJ...Alarm device, ES...Fault notification line group, EMA...Emergency control circuit, TF...Clock disconnection detection circuit, PED...
Parity error detection circuit, ED...error detection circuit, AB...address bus, DB...data bus
Bus, CB...Control bus, COM...Address verification circuit, AG ₁ to AG ₆ ...AND gate, OR ₁ to OR ₅ ...OR gate, NAG ₀ to
NAG ₈ ……Nand Gate, E-FF, CCR-
FF, MMR−FF, IOCR−FF, CC−FF, MM ₀
−FF, MM ₁ −FF, MM ₂ −FF, MM ₃ −FF,
IOC ₀ −FF, IOC ₁ −FF, IOC ₂ −FF...Flip-flop, IN ₁ , IN ₂ ...NOT circuit, IN ₃ ~ IN ₁₁ ...
...driver, D-CC, D-MM ₀ , D-MM ₁ ,
D- _MM2 , D- _MM3 , D- _IOC0 , D- _IOC1 ,
D-IOC ₂ ...Fault visual display element, PC...Photocoupler.

Claims (1)

[Claims] 1 A central control unit, a main storage device controlled by the central control unit, devices such as an input/output control device, and a fault display device equipped with a fault visual display element corresponding to each of the above devices are connected to a system bus. Connected by
The fault indicator includes means for enabling the central controller to drive a fault visual indicator corresponding to the affected device via the system bus;
Each of the above devices has an individual fault notification line connected to the fault display device, and a fault detected in each device notifies the fault display device of the fault through the fault notification wire, and The fault visual display device corresponding to the fault device is driven, and the fault display device is further equipped with an alarm device, and the system controller is connected to the fault display device by the central control device.
A fault display system characterized in that the fault display device receives and latches an alarm sending command sent via a bus, and drives the alarm device only when at least one fault information is latched. .