JPH03265123A - Formation of crystalline semiconductor film - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming a crystalline semiconductor layer, and in particular to improving the crystallinity and crystal grain size of polycrystals to form a high-performance thin film transistor (TPT). The present invention relates to a method for forming a crystalline semiconductor film suitable for.

[Conventional technology] Conventionally, there has been a technology to deposit a polycrystalline silicon film on a glass substrate by LPCVD method or the like and use it to form TPT, but recently there has been a strong demand for higher performance of TPT. Therefore, it is desired to improve the quality of polycrystalline silicon itself. For example, in a recent conference presentation, silicon was ion-implanted at a high dose into a polycrystalline silicon film to make it completely amorphous, and then annealed at about 600°C for a long time to grow in a solid phase, resulting in large-grain polycrystals. There are known examples of obtaining .

[Problem to be solved by the invention] In such a method, considering the crystallization process, it is found that
During annealing after completely becoming amorphous by Si ion implantation, crystal nuclei are generated at a low density, grow in a solid phase, and where they collide with each other, grain boundaries are formed and the crystal grain size decreases. Determined.

However, this solid-phase grown crystal grain contains many twin boundaries, which are usually called puntrik, and other defects. Generally, crystal nuclei tend to occur mainly at the upper or lower interface of the semiconductor silicon layer, and at that time, it is thought that they are largely influenced by the underlying amorphous glass substrate etc. during the initial stretching process. Depending on the interface conditions between the upper and lower interfaces, it is assumed that many stacking faults and the like are likely to occur in the initial growth stage.

In addition, the crystal grain size is determined by the density of crystal nuclei,
It is thought that the density of nuclei generated is greatly influenced by the state of the interface with the base substrate as well as the dependence on the ion implantation amount. Therefore, it is difficult to control the particle size with good reproducibility unless the interface state is maintained well.

[Means for Solving the Problems] The method for forming a crystalline semiconductor layer of the present invention provides a method for forming a crystalline semiconductor layer during a sputtering process in which a semiconductor film is deposited on a substrate while applying a relative potential between a plasma and a substrate. By controlling the ion collision energy incident on the substrate side, an amorphous semiconductor layer, a crystalline semiconductor layer, and an amorphous semiconductor layer are sequentially deposited on the substrate, and then the substrate is annealed. By doing so, the amorphous semiconductor layer is crystallized by causing nuclei to grow from the vicinity of the crystalline semiconductor layer.

A polycrystalline semiconductor film having high quality crystallinity and controlled grain size is obtained.

[Action Co. The operation of the present invention will be explained below along with the detailed configuration.

In the present invention, sputtering is performed by applying a relative potential between the plasma and the substrate, and the means for doing so will first be explained.

FIG. 1 is a configuration diagram of an apparatus for performing sputtering while applying a relative potential when the substrate is an insulator.

A substrate 1 is installed in a sputtering chamber 2,
A target 3 made of a wafer (for example, a Si wafer) is fixed at a position facing it. This target 3
An RF power of 100 MHz is applied from an RF power source 4, and a DC bias of 0 to 400 V is applied from a DC power source 5 via a low pass filter 6. On the other hand, RF power of 13.56 MH is also applied to the insulating substrate 1 from the R'F power supply 7 via the low bus filter 8.

When RF power is applied to the target in this configuration to generate plasma, a self-bias is generally generated on the substrate surface, but by applying RF power to the substrate side, this self-bias, that is, the plasma potential The relative potential to the substrate potential can be changed. This amount of change is determined by various conditions such as the plasma state and the electrode area, but generally a voltage proportional to the square root of the RF power on the base 1 side is applied.

In this way, even if the substrate is an insulator, by applying RF power to the substrate, it is possible to change the self-bias of the substrate surface, and as a result, ions accelerated by the relative potential of the plasma Collision energy is incident on the controlled substrate 1.

In the present invention, by changing this collision energy during sputtering, amorphous, crystalline,
Amorphous and sequentially deposited.

FIG. 2 shows that the crystallinity of the deposited film changes as the relative potential changes. This is Appl p
hy Lett Vol 153 No, 5 p364
(1988), Si sputter deposition was performed on a Si substrate. As is clear from this figure, for example, if the target bias is -200V
In this case, the first step is -5 to -10V, the second step is +5 to -5V, and the third step is -5 to -10V.
If you control 10V and relative potential (substrate bias voltage),
Semiconductor layers can be deposited in the order of amorphous, crystalline, and amorphous. Note that the thickness of the layer can be adjusted to any desired thickness by adjusting the deposition time. The reason why the crystallinity differs when the relative potential is different is as follows:
In the third step, since the substantial ion collision energy is large, it becomes amorphous due to the damage effect, while the second step
It is presumed that this is because the step provides just the right amount of energy to crystallize the silicon atoms.

As described above, the present invention enables the formation of a crystalline semiconductor layer by changing the collision energy of ions flying into the film during the deposition of the semiconductor film on an amorphous substrate. An amorphous semiconductor layer sandwiched therebetween can be formed.

Furthermore, in the present invention, annealing is performed after the deposition of such an amorphous semiconductor layer sandwiched between crystalline semiconductor layers is completed. When annealing is performed, solid phase growth occurs from the interposed crystalline layer, and the amorphous layer changes to a crystalline layer. In this way, since crystal growth occurs from the crystalline layer, unlike the prior art, it is possible to eliminate the influence of the interface state with the underlying substrate.

It should be noted that the density of nuclei generated when solid phase growth occurs, as well as the grain size of the solid phase grown crystals, can be changed mainly by the collision energy in the second step.

For example, as mentioned above, when the target bias is 1200V, if the effective relative potential is selected to be in the range of 110V to 15V as shown in Figure 2, a crystalline layer will be deposited. Furthermore, when the relative potential is changed within the range of -10V to -5V, the crystal grain size of the crystalline layer also changes. It was confirmed that by changing this relative potential, the final crystal grain size after annealing changes. This is thought to be because the density of crystal nuclei generated changes due to changes in self-bias, that is, ion collision energy.

The above explanation shows the case where the substrate is an insulating material, but if the substrate is a conductive material, it is possible to change the self-bias by applying DC bias from a DC power source instead of RF power to the substrate. .

Further, in the above explanation, silicon was used as a representative example of the semiconductor material, but it is obvious that the present invention can also be applied to other semiconductor materials such as Ge. At this time, how to control the relative potential can be determined by obtaining a graph such as the one shown in FIG. 2 in advance through experiments or the like.

[Example] A 5i02 substrate was used as the substrate, and Si was used as the target.
A wafer was used and an apparatus shown in FIG. 1 was used. In the apparatus shown in FIG.
After evacuation to a vacuum pressure of Torr, the 5i02 substrate 1 was heated to 350T. After that, argon (Ar
) Gas is introduced into the chamber and the gas pressure is 8X10-'
TorrRF power is 40W, target bias -2
St sputtering was performed with the setting set to 00V and a substantial Si02 surface bias of -15V.

In this first step, sputtered Si was deposited on the surface of the 5i02 substrate in an amorphous structure at a rate of 10.lambda./min. 500λ a- for 5 minutes as the first step
After depositing 5t, a second step is to deposit a substantial 510
2 Deposition was performed for 15 seconds with the substrate bias varied to -5V.

Then, in the third step, the conditions were returned to the same as those in the first step, and the deposition was continued for 5 minutes.
A film was formed on a 5i02 substrate.

In this way, 1000 pieces of amorphous silicon were deposited.
When the i02 substrate was annealed (heat treated) at 600° C. for 100 hours, polycrystalline grains with a crystal grain size of about 2 μm and very few defects were obtained.

During this polycrystalization, the cross section of the semiconductor layer is subjected to TE.
M observation revealed that crystal nuclei were mainly generated and growing from the center of the film.

[Effects of the Invention] As described above, according to the present invention, it is possible to eliminate the influence of the interface state with the base without using any special process, and it is possible to form large-grain polycrystalline semiconductor films with high reproducibility. Since it can be easily obtained and the crystallinity of the polycrystalline grains is good, it is possible to form a polycrystalline semiconductor film that is extremely useful when applied to TPT.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a sputtering chamber for explaining a method according to an embodiment of the present invention. FIG. 2 is a graph diagram showing an example of film forming conditions. 1...5i02 board, 2...Sputtering chamberer 3...Target, 4.7...RF power supply, 6
゜8...Low bass filter 5...DC power supply. Fig.

Claims (1)

[Claims] During the sputtering process in which a semiconductor film is deposited on the substrate while applying a relative potential between the plasma and the substrate, the collision energy of ions incident on the substrate is controlled by controlling the relative potential. A semiconductor layer, a crystalline semiconductor layer, and an amorphous semiconductor layer are sequentially deposited on the substrate, and then the substrate is annealed to grow the amorphous semiconductor layer from the vicinity of the crystalline semiconductor layer. 1. A method for forming a crystalline semiconductor film, comprising crystallizing.