JPH03265145A - Manufacture of vertical type mos transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS transistor on a SO substrate.

[Summary of the Invention] On a high concentration first conductivity type silicon substrate, a low concentration second conductivity type silicon substrate is formed.
A conductive silicon epitaxial layer is formed, and a highly concentrated first conductive silicon epitaxial layer is formed thereon.A thermal oxide film is formed on the surface, and a silicon nitride film is deposited, followed by a photolithography process and anisotropic process. By sexual etching,
The interior of the highly doped silicon substrate of the first conductivity type is removed, leaving a portion that will become an element formation region.

Thereafter, a base thermal oxide film is formed again, a silicon nitride film is deposited, and only the silicon nitride film on the flat portion of the substrate and the base thermal oxide film are removed by anisotropic etching. After performing isotropic etching on the exposed flat part of the substrate,
Thermal oxidation is performed to form a silicon island that is thicker than the substrate, consisting of a highly concentrated silicon epitaxial layer of the first conductive type, a lightly concentrated silicon epitaxial layer of the second conductive type, and a part of the highly concentrated silicon substrate of the first conductive type. In step 6, a vertical MO5I-land disk is formed in the silicon island obtained by separating it by a thermal oxide film.

[Conventional technology]

Hitherto, horizontal MOS transistors formed on SO substrates have been known.

[Problems to be Solved by the Invention] However, SOI substrates obtained by various methods have problems such as deterioration of crystallinity and non-uniformity of the thickness of the element formation layer depending on the manufacturing method. The resulting deterioration of MO5I-transistor characteristics, non-uniformity within the same substrate, etc. are appearing. Furthermore, it has recently been pointed out that if the thickness of the element formation layer on the SO substrate, especially the channel part, is made extremely thin so that the entire channel part can be depleted, the performance characteristics of MOS transistors can be dramatically improved. However, it is extremely difficult to form such a thin element forming layer over the entire surface of the substrate. Furthermore, although it is meaningful to miniaturize elements, lateral MOS transistors have the drawback of being limited by photolithography technology.

Therefore, an object of the present invention is to form an element formation region with a uniform thickness over the entire surface of a substrate, and to form MOS transistors with high density that fully bring out the features of the SOI structure.

[Means for Solving the Problems] In order to solve the above problems, the present invention forms a low concentration silicon epitaxial layer of a second conductivity type on a high concentration silicon substrate of a first conductivity type, A highly concentrated silicon epitaxial layer of the first conductivity type is formed, and the silicon island consisting of the three layers is separated by an oxide film thicker than the substrate by photolithography, etching, and oxidation steps, and a vertical MOS transistor is formed in this silicon island. It's Chino.

[Operation 1] According to the method for manufacturing a vertical MO5I-transistor of the present invention, an MO5I-transistor that fully brings out the features of the SOI structure can be formed at high density over the entire surface of the substrate.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 1(a) to 1(g) are cross-sectional views in the order of steps of a method for manufacturing a vertical MOS transistor according to the present invention.

First, a silicon epitaxial layer 2 of a second conductivity type with a low concentration is formed on a silicon substrate 1 of a high concentration first conductivity type with a thickness of, for example, 200 nm.
A silicon epitaxial layer 3 of the first conductivity type with a high concentration of, for example, 5000A is formed (see Fig. 1).
A)), 2 and 3 can be formed by normal epitaxial method, but by using MLE (molecular layer eviction) technology, the film thickness can be formed with high precision and impurity diffusion can be minimized. It is possible to keep it to a minimum.

Next, a highly concentrated silicon epitaxial layer 3 of the first conductivity type is formed.
After forming about 500 layers of thermal oxide film 4 on the surface, about 1500 layers of silicon nitride film 5 is deposited.

After applying a resist to the surface and performing necessary patterning by a photolithography process, etching is performed by anisotropic etching such as RIE to reach the inside of the highly concentrated first conductive type silicon substrate l, and the resist is removed ( 1st
As shown in Figure (b)), the patterning width determines the thickness of the channel part of the rectangular transistor obtained through later steps, so the patterning width is fine enough to completely deplete the channel part using normal photolithography and etching techniques. If a desired channel thickness cannot be obtained, a thermal oxidation step and a step of removing the formed thermal oxide film with hydrofluoric acid or the like are added to adjust the channel thickness to the required thickness.

Next, a base oxide film 6 is formed by thermal oxidation, and a silicon nitride film 5 is further deposited (FIG. 1(C)).

Thereafter, etching is performed by anisotropic etching until the surface of the highly-concentrated first conductive type silicon substrate 1 is exposed (
Figure 1(d)). Next, using a hydrofluoric acid-nitric acid etchant, the highly concentrated first conductive type silicon substrate 1 is heated to
Human etching (Fig. 1 (e)), followed by normal LOC
When a thick oxide film 7 is formed by a method called O3 oxidation, the silicon island 9, which will become an element formation region, is separated from the high concentration first conductivity type silicon substrate 1 (FIG. 1(f)).
After removing the silicon nitride film 5 and the underlying oxide M6, oxidize the gate by thermal oxidation! Zero-order polycrystalline silicon is deposited to form a gate electrode 10, and planarized if necessary to form a gate electrode 11 (FIG. 1(g)). After this, although not shown, a necessary interlayer insulating film is formed and wiring is made of aluminum or the like to form an integrated circuit. In the above embodiment, a portion 8 of a highly doped first conduction type silicon substrate separated by a thick oxide film 7 and a highly doped first conduction type silicon epitaxial layer 3 are used as a pair of sources and drains, and a low concentration A vertical MOS transistor is formed using the silicon epitaxial layer 2 of the second conductivity type as a channel. The channel length is 2000 nm, and if it is formed to a thickness that allows complete depletion of the channel part, it will have dramatically superior characteristics compared to conventional MOS transistors formed on silicon substrates.
A MO5I transistor with OI structure is obtained.

[Effects of the Invention] As described above, according to the method of the present invention, the conventional S
Even without using a QI substrate, a MOS transistor having an SOi structure can be formed on a normal silicon substrate by a normal semiconductor process. Furthermore, since it is a vertical MOS transistor, the area occupied on the substrate is smaller than that of a conventional horizontal MOS transistor.
It is several minutes lower than that of an S transistor, and on one substrate,
More MOS transistors can be formed, which can greatly contribute to cost reduction. In addition, the control of the channel length (gate length), which was limited by photolithography and etching techniques in conventional lateral MOS transistors, can be controlled by the thickness of the epitaxial layer that forms the channel section with the vertical structure. By using MLE technology, etc., it is possible to achieve higher precision, and the channel length can be easily controlled to less than 0.25 LLm, which was considered to be the limit in the past. According to the method, MOS on a normal substrate
This has the advantage that an SOI-structured MOS transistor (MOS transistor) having superior performance characteristics compared to a transistor can be formed over the entire surface of the substrate at a high integration density using a normal process.

[Brief explanation of drawings]

FIGS. 1(a) to 1(g) are cross-sectional views in the order of steps of a method for manufacturing a vertical MOS transistor according to the present invention. l...High concentration first conduction type silicon substrate 2...Low concentration second conduction type silicon epitaxial layer 3...High concentration first conduction type silicon epitaxial layer 4...Thermal oxide film Silicon nitride film, underlying thermal oxide film, thick oxide film, part of high concentration first conduction type silicon substrate 9...silicon island 10...gate oxide film 11...gate electrode or higher

Claims (1)

[Claims] A low concentration second conduction type silicon substrate is placed on a high concentration first conduction type silicon substrate.
forming a conduction type silicon epitaxial layer, and forming a high concentration first conduction type silicon epitaxial layer on the low concentration second conduction type silicon epitaxial layer; A process of forming a thermal oxide film on the silicon epitaxial layer and depositing a silicon nitride film on the thermal oxide film, applying a resist on the silicon nitride film and forming a necessary pattern by photolithography, and then depositing the high concentration film on the silicon epitaxial layer. etching vertically by anisotropic etching so as to reach the inside of the first conductivity type silicon substrate; and after removing the resist, the exposed side surfaces of the high concentration first conductivity type silicon epitaxial layer; forming a base thermal oxide film on the side surface of the low concentration second conductivity type silicon epitaxial layer and on the high concentration first conductivity type silicon substrate; and forming a base thermal oxide film on the base thermal oxide film. a step of depositing a nitride film; a step of removing the silicon nitride film and the underlying oxide film deposited in the horizontal direction on the highly concentrated silicon substrate of the first conductivity type by anisotropic etching; and exposing the silicon nitride film. A step of partially removing the high concentration first conductivity type silicon substrate by isotropic etching and thermal oxidation is performed to form the high concentration first conductivity type silicon epitaxial layer and the low concentration second conductivity type silicon substrate. separating a silicon island consisting of a silicon epitaxial layer of The high concentration first conduction type silicon epitaxial layer in the silicon island and a part of the high concentration first conduction type silicon substrate are used as a pair of sources and drains, and the low concentration second conduction type silicon is used as a pair of sources and drains. A vertical type M characterized by having a step of forming a vertical MOS transistor using an epitaxial layer as a channel.
A method for manufacturing an OS transistor.