JPH03265154A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To surely form a dielectric buried layer inside a substrate by forming a dielectric layer on a substrate surface which is equivalent to a recessed region when forming both semiconductor substrates before a junction process of first and second semiconductor substrates. CONSTITUTION:A recessed part 2 is formed on a part of a mirror surface 1a of a first semiconductor substrate 1. A groove 3 whose values of both width and depth are larger than those of the recessed part 2 is formed along an area near a boundary with the mirror surface 1a of the recessed part 2. An Si nitride film 4 is formed on a surface having the recessed part 2 and the groove 3 of the substrate 1 to expose a surface of the recessed part 2 and the groove 3. A heat oxidation Si layer 5 is formed only on a surface of the recessed part 2 and groove 3 exposed by heat treatment to remove the film 4. Thereafter, mirror surfaces 1a, 6a of two sheets of first substrate 1 and second substrate 6 are adhered mutually. Accordingly, it is possible to enable sure formation of the buried layer 5 inside the substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor substrate, and more particularly to a method of selectively forming a dielectric buried layer inside a substrate by direct substrate bonding technology.

[Conventional technology]

Dielectric isolation methods have been attracting attention as an element isolation method in semiconductor integrated circuits, and various methods have been proposed to form a dielectric buried layer inside a substrate in order to isolate an element region from a substrate region.

One of them is, for example, the one shown in Japanese Patent Application Laid-Open No. 61-42154. This involves forming a groove opening to the end surface of the substrate on the surface of the mirror-polished first semiconductor substrate, and also forming a groove on the surface of the first semiconductor substrate or the mirror-polished second semiconductor substrate to be bonded thereto. These first. A shallow recess is formed that communicates with the groove when the second semiconductor substrate is bonded to the first semiconductor substrate. The polished surfaces of the second semiconductor substrates are brought into close contact with each other, and the bonded substrate is then exposed to an oxidizing gas atmosphere to form an oxide film embedded in the recess.

[Problem to be solved by the invention]

However, when the present inventors actually manufactured a dielectric isolation substrate using the method described above, there was a problem that depending on the shape of the recess, it was not possible to satisfactorily embed the oxide film. As a result of repeated experimental considerations,
This is number 1. In the process of directly bonding the second semiconductor substrate, the hydrogen bonding force at the interface is strong at the time when the substrate surface is hydrophilically treated and brought into close contact. If the recess becomes small, the recess cannot be maintained, and as shown in FIG.
It was discovered that the surface of the recess is bonded to the surface of the other substrate, making it impossible to form an oxide film in the recess region when filling the oxide film after the bonding process. It has been confirmed that this phenomenon occurs more often when the recesses are formed to a size that is normally used as an element isolation region, such as less than Å or B of the recesses larger than a few squares.

In order to avoid this problem, for example, Japanese Patent Laid-Open No. 61-598
It is also conceivable to use the method proposed in Japanese Patent No. 53 or Japanese Patent Application Laid-Open No. 62-24641. The former is the 6th
As shown in the figure, a thermally oxidized silicon layer 20 is formed on the surface of the substrate 21.
After selectively forming and planarizing the surface, another substrate 22
The dielectric layer 23 is embedded inside the substrate by directly bonding the dielectric layer 23 to the substrate. On the other hand, in the latter method, as shown in FIG. 7, a thermally oxidized silicon layer 32 is formed on the surface of a substrate 31 having a recess 30 on the surface, and then a dielectric layer 33 such as polycrystalline silicon is deposited to form a dielectric layer 33 other than the recess 3o. After planarizing the substrate surface until it is exposed, a dielectric layer 35 is buried inside the substrate by directly bonding it to another base Fi 34.

However, although these methods can avoid the above-mentioned problems, in the planarization process before substrate bonding, the substrate surface is mixed with silicon 5 thermally oxidized silicon or polycrystalline silicon and a different material. Even if methods such as lap-boring and selective etching are used, it is difficult to obtain the flatness and two-sided roughness required for direct bonding.
Furthermore, even if bonded substrates are obtained, there is a problem in that electrical characteristics at the bonded interface deteriorate due to microvoids and the like generated during bonding.

The present invention has been made in view of the above-mentioned circumstances, and is a method for selectively embedding a dielectric layer inside a substrate using substrate direct bonding technology. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that can reliably form a dielectric buried layer inside the substrate while maintaining the same.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor substrate according to the present invention includes: a semiconductor substrate in which a dielectric buried layer is formed by directly bonding the polished surfaces of first and second semiconductor substrates that have been mirror-polished; A method for manufacturing the first semiconductor substrate, comprising: forming a recess in the polished surface of the first semiconductor substrate; When the second semiconductor substrate is bonded, a step of forming a groove deeper than the recess that is open in the end surface of the substrate and communicates with the recess, and then directly bonding the polished surfaces of the first and second semiconductor substrates. In a method for manufacturing a semiconductor substrate including a bonding step of forming a bonded substrate, at least, before the bonding step,
The method is characterized in that it includes a step of forming a dielectric layer on the substrate surface corresponding to the recessed region when the first and second semiconductor substrates are bonded.

[Operations/Effects] Therefore, according to the present invention, when the first and second semiconductor substrates are bonded in the bonding step, the surface of the substrate corresponding to at least the recessed region formed in the first semiconductor substrate is Even if the concave region is bonded without maintaining the concave portion due to hydrogen bonding during the bonding process as in the conventional method, since a dielectric layer has been formed in advance in a step before the process,
This dielectric layer ensures that a dielectric buried layer is formed inside the substrate.

In addition, since the bonding surface during the bonding process does not require a flattening process that involves dissimilar materials, the flatness and roughness of one surface can maintain the original mirror-polished surface, and the electrical properties at the bonding interface are reduced. There's nothing to do.

As described above, according to the present invention, there is an excellent effect that a dielectric buried layer can be reliably formed inside a substrate while maintaining the flatness and surface roughness of the surface of the substrate to be directly bonded.

[Example〕 Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIGS. 1(a) to 1(g) show cross-sectional views in each manufacturing process of a semiconductor substrate according to a first embodiment of the present invention.

First, as shown in FIG. 1(a), a part of the mirror surface 1a of the first semiconductor substrate 1 whose at least one surface has been mirror-polished is subjected to chemical etching or reactive ion etching (hereinafter referred to as RIE).
selectively etched to a depth of 0.2~
A recess 2 of 2 μm is formed.

Next, as shown in FIG. 1(b), a groove 3 is opened at the edge of the substrate along the vicinity of the boundary between the recess 2 and the mirror surface 1a, and has a width and depth larger than the depth of the recess 2. is formed by dicing, chemical etching, or RIE.The shape of the groove 3 is determined by taking into account the shape of the recess 2, the substrate size, etc. In this example, 31
Using a nch wafer, the recess 2 has a width of 6 mm and a depth of 0.8.
A stripe shape with a width of 3 μm is formed by chemical etching.
0μm.

A striped groove having a depth of 10 μm is formed therein.

Next, as shown in FIG. 1(C), the recess 2 of the first semiconductor substrate l,
A silicon nitride film 4 is formed on the surface having the groove 3, and the recess 2. is formed by a normal photo process. The surface of groove 3 is exposed.

Furthermore, as shown in FIG. 1(d), a thermally oxidized silicon layer 5 is formed only on the surfaces of the recesses 2 and grooves 3 exposed as described above by heat treatment, and then the nitride film 4 is removed. The thickness of the thermally oxidized silicon layer 5 formed in the step shown in FIG. In order to enable direct bonding to another substrate in the process described later, it is necessary to form the layer so that it does not protrude beyond the surface of the mirror surface 1a of the first semiconductor substrate 1, leaving a depth h below the surface of the mirror surface 1a. do. In this example, the thickness of the thermally oxidized silicon layer 5 was 0.35 μm.

Then, this first semiconductor substrate processing and the second semiconductor substrate 6 whose at least one surface is mirror-polished are subjected to, for example, trichlene boiling, acetone ultrasonic cleaning, and NH.

:H20□ :H20=I : Removal of organic matter with I:4 mixed solution, HCI : HzOz 2HzO=i
: Thorough cleaning is performed by sequentially removing metal contamination with a 1:4 mixed solution and washing with pure water. After that, H
After removing the natural oxide film with a mixed solution of F:H,○-1:50, it is immersed in an acidic solution such as a mixed solution of H,S○, :H,02=3:l, or subjected to thermal oxidation or An oxide layer of about 10 to 30 A is formed on the surface of the substrate by oxygen plasma irradiation or the like to make it hydrophilic and then washed with pure water.

Next, after drying with dry nitrogen or the like to control the amount of moisture adsorbed on the substrate surface, the mirror surfaces 1a and 6a of the two substrates 1.6 are brought into close contact with each other as shown in FIG. 1(e). As a result, the two substrates 1.6 are bonded together through hydrogen bonds between the silanol groups formed on the surfaces and the water molecules adsorbed on the surfaces. Saramuko, this glued board] and 6 to 10T
Dry in vacuum below orr. At this time, substrate 1
In order to compensate for the warpage of 6 and 6, a load of 30 g/d or more may be applied. After this, substrates 1 and 6
11 in an inert gas atmosphere such as nitrogen, argon, etc.
By applying heat treatment at 00°C or more for 1 hour or more,
A dehydration reduction reaction occurs on the adhesive surface and silicon (Si)
) and oxygen (0) (Si-○-3i), and 0 further diffuses into the substrate to form bonds between Si atoms (Si-3i).
i) is completed, the two substrates 1 and 6 are directly bonded, and a bonded substrate 10 is formed.

Here, in the step shown in FIG. 1(e), as described above, the surface of the recess 2 is joined to the surface 6a of the second semiconductor substrate 6 by hydrogen bonding force without maintaining the recess 2. However, since this hydrogen bonding is performed via the thermally oxidized silicon layer 5, the thermally oxidized silicon layer 5 can be reliably buried inside the bonding substrate 10. Also, the first
In the process shown in Figure (d), the thermally oxidized silicon layer 5 is formed without protruding beyond the mirror surface 1a, so that the flatness and surface roughness of the bonding surface can be maintained at the desired value, and direct bonding technology is A bonded substrate can be obtained satisfactorily using this method.

Then, as shown in FIG. 1(f), the obtained bonded substrate 1
Polishing or etching is performed until grooves 3 are opened in the main surface 1b of the substrate.

After that, as shown in FIG. 1, the groove 3 is filled with a filler 7 such as silicon oxide by, for example, the SOG (spin-on-glass) method, and the deposits on the main surface Ib of the substrate are removed by, for example, lap polishing or RIE. By removing and planarizing, a semiconductor substrate 10 having an element isolation region 10A that is completely electrically isolated from other regions by the filling layer 7 and the thermally oxidized silicon layer 5 is obtained. By forming elements, a desired semiconductor device is obtained.

Note that the silicon oxide 7 serving as the filling material may be other than silicate glass, nitride, etc., and the filling method may also be CVD, sputtering, vapor deposition, etc.

In FIG. 2, for example, an N substrate is used as the first semiconductor substrate 1, and a second
3 is a cross-sectional view of a semiconductor device obtained by the above manufacturing method using an N' substrate as the semiconductor substrate 6. FIG. A vertical power transistor 8 and a logic circuit section 9 for controlling the transistor 8 are mounted on a single-chip semiconductor substrate 10.

Here, the logic circuit portion 9 is formed in the element bone M region 10A, and is insulated from the transistor 8 by the thermally oxidized silicon layer 5 and the filler layer 7, so that it has excellent isolation voltage.

Next, a second embodiment of the present invention will be described using FIGS. 3(a) to 3(C).

In the first embodiment described above, if the depth h of the surface of the thermally oxidized silicon layer 5 formed in the step of FIG. 1(d) from the surface 1a of the first semiconductor substrate 1 is large, the depth h as shown in FIG. 1(e) Even if the first semiconductor substrate 1 and the second semiconductor substrate 6 are directly bonded in the same manner as in the process shown in FIG. 6a
are not bonded, and a cavity remains inside the bonded substrate 10.

Note that the depth h at this time is the shape (depth, width) of the recess 2,
Although it depends on the thickness of the thermally oxidized silicon layer 5, it was confirmed that cavities remained when the thickness was 0.5 μm or more.

In this case, by adding the step shown in Part 3), a thermally oxidized silicon layer can be buried inside the bonding substrate 10. That is, the integrated substrate 10 as shown in FIG. 3(a) is dried, for example. Wet 02
．． 900 in an oxidizing atmosphere such as H2102 mixed combustion gas
A heat treatment is performed at a temperature of at least .degree. C. for one hour or more to oxidize the surface of the cavity inside the substrate 10 through the groove 3, and bury the thermally oxidized silicon layer 11 including the thermally oxidized silicon layer 5. However, in the oxidation step shown in FIG. 3(b), the cavity consisting of the above-mentioned recess 2 formed between the surface of the thermally oxidized silicon layer 5 and the second semiconductor substrate surface 6a is formed by growing from both surfaces. The oxidation time is set so that it is completely buried and filled with thermally oxidized silicon.

As a result of the above steps, the thermally oxidized silicon layer 11 is buried and filled inside the semiconductor substrate as a dielectric buried layer.

After that, as shown in FIG. 3(C), the bonded substrate 1
Rough polishing (lapping) is performed from the main surface 1b side of the groove 3 until the thickness from the bonding surface becomes 30 μm or less, and then selective polishing is performed until the thermally oxidized silicon layer 11 at the bottom of the groove 3 is exposed. This selective polishing can be carried out using, for example, an amine solution (
By using a flat plate pad made of piperazine) and polyester and allowing the thermally oxidized silicon layer II to function as an etching stopper, the element isolation region 10A surrounded by the oxide film can be formed with good controllability in its layer thickness. Also, Figure 3 0
)) Since the inner wall of the groove 3 is also covered with an oxide film, there is no need to fill the cavity left inside the groove 3 with an insulator or a dielectric material such as polycrystalline silicon, which simplifies the process. .

Note that in the various embodiments described above, the thermally oxidized silicon layer 5
was formed selectively on the inner wall of the recess 2 and groove 3 provided on the mirror surface la side of the first semiconductor substrate 1, but as in the third embodiment shown in FIG. Alternatively, a thermally oxidized silicon layer 5' may be formed.

Further, the groove 3 and the recess 2 only have to communicate with each other when two semiconductor substrates are bonded together, and the order in which they are formed is not limited to the above-mentioned embodiment. There is no problem in forming it. Furthermore, the selectively formed thermally oxidized silicon layers 5 and 5' only need to be formed at positions corresponding to the recesses 2 when bonding the substrates, and they may be formed on any semiconductor substrate. It is.

[Brief explanation of drawings]

1(a) to (cloudy) are cross-sectional views in the order of manufacturing steps of a semiconductor substrate to which the first embodiment of the present invention is applied; FIG. 2 is a cross-sectional view of a semiconductor device manufactured according to the first embodiment of the present invention; FIG. (a)～
(C) is a sectional view in the order of the manufacturing process of a semiconductor substrate explaining the second embodiment of the present invention, and FIG. 4 is a sectional view in the order of the manufacturing process of the semiconductor substrate according to the third manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... First semiconductor substrate, 2... Recessed part, 3... Groove,
5°5'... thermally oxidized silicon layer 56... second semiconductor substrate 10... bonding substrate, 11... thermally oxidized silicon layer.

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor substrate in which a dielectric buried layer is formed by directly bonding the polished surfaces of a first and second semiconductor substrate that have been mirror-polished, the polishing of the first semiconductor substrate a step of forming a recess in the surface; a step of forming a groove deeper than the recess that opens in the end surface of the substrate and communicates with the recess when the first and second semiconductor substrates are bonded; A method for manufacturing a semiconductor substrate including a bonding step of directly bonding polished surfaces of second semiconductor substrates to form a bonded substrate, at least when bonding the first and second semiconductor substrates before the bonding step. A method for manufacturing a semiconductor substrate, comprising the step of forming a dielectric layer on a surface of the substrate corresponding to the recessed region. (2) Manufacturing the semiconductor substrate according to claim 1, wherein the dielectric layer is formed on the surface of the recessed portion of the first semiconductor substrate, leaving a height difference from the polished surface of the first semiconductor substrate. Method. (3) After the bonding step, the bonding substrate is exposed to an oxidizing gas atmosphere and the oxidizing gas is supplied along the groove to fill the recess with an oxide film. The method for manufacturing a semiconductor substrate according to claim 1 or 2.