JPH032672U - - Google Patents
Info
- Publication number
- JPH032672U JPH032672U JP6214489U JP6214489U JPH032672U JP H032672 U JPH032672 U JP H032672U JP 6214489 U JP6214489 U JP 6214489U JP 6214489 U JP6214489 U JP 6214489U JP H032672 U JPH032672 U JP H032672U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- masking
- layer
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000873 masking effect Effects 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 4
- 229910052799 carbon Inorganic materials 0.000 claims 4
- 239000000463 material Substances 0.000 claims 4
- 239000011347 resin Substances 0.000 claims 4
- 229920005989 resin Polymers 0.000 claims 4
- 238000004080 punching Methods 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図、第２図は本案の第１実施例を示す平面
図と側断面図、第３図は本案の第２の実施例を示
す断面図、第４図は本案の第３の実施例を示す平
面図、第５図、第６図は本案の第４の実施例を示
す平面図と断面図である。
１０……プリント基板、１００……半田デイツ
プ面、１１……半田ランド、２０……マスキング
層、２１……穴部、２２……穴部、２３……半抜
き片、２０１……開始マーク、２５……凹部、２
０′……密着性の悪い層。
Figures 1 and 2 are a plan view and side sectional view showing a first embodiment of the present invention, Figure 3 is a sectional view showing a second embodiment of the present invention, and Figure 4 is a third embodiment of the present invention. FIGS. 5 and 6 are a plan view and a sectional view showing a fourth embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Printed circuit board, 100... Solder dip surface, 11... Solder land, 20... Masking layer, 21... Hole part, 22... Hole part, 23... Half punched piece, 201... Start mark, 25... recess, 2
0'...Layer with poor adhesion.
Claims (1)
カーボン接点、表面実装部品の半田ランド等を保
護するためのマスキング樹脂又はマスキングテー
プより成る層が形成されたプリント基板において
、 前記マスキングの層の端縁部と対応する基材の
１〜数個所に１部が前記端縁部から外側に表われ
た穴部を貫通形成したことを特徴とするプリント
基板。 (2) 半田デイツプ面に形成されたメツキ端子、
カーボン接点、表面実装部品の半田ランド等を保
護するためマスキング樹脂又はマスキングテープ
より成る層が形成されたプリント基板において、 前記マスキングの層の端縁部と対応する基材の
１〜数個所に半抜き加工による穴部を形成し、該
穴部に半抜き片を残して前記マスキング層側に押
し出し可能にしたことを特徴とするプリント基板
。 (3) 半田デイツプ面に形成されたメツキ端子、
カーボン接点、表面実装部品の半田ランド等を保
護するためのマスキング樹脂又はマスキングテー
プより成る層が形成されたプリント基板において
、 前記マスキングの層に剥離開始位置を示す開始
マークを一体的に突出させて形成したことを特徴
とするプリント基板。 (4) 開始マークがマスキング層の端縁部近傍に
形成され、この開始マークと対応する基材の部分
に貫通孔又は凹部を形成したことを特徴とする請
求項(3)に記載のプリント基板。 (5) 半田デイツプ面に形成されたメツキ端子、
カーボン接点、表面実装部品の半田ランド等を保
護するためのマスキング樹脂又はマスキングテー
プより成る層が形成されたプリント基板において
、 前記マスキングの層の端縁部と対応する基材の
１〜数個所に凹部を形成したことを特徴とするプ
リント基板。[Scope of claims for utility model registration] (1) Plated terminals formed on the solder dip surface;
In a printed circuit board on which a layer made of masking resin or masking tape is formed to protect carbon contacts, solder lands of surface mount components, etc., one to several places on the base material corresponding to the edge of the masking layer are provided. 1. A printed circuit board, characterized in that one part of the printed circuit board has a hole extending outward from the edge. (2) Plated terminals formed on the solder dip surface;
In a printed circuit board on which a layer of masking resin or masking tape is formed to protect carbon contacts, solder lands of surface mount components, etc., half-layers are applied to one or several places on the base material corresponding to the edge of the masking layer. A printed circuit board characterized in that a hole is formed by punching, and a half-blank piece is left in the hole so that it can be extruded to the masking layer side. (3) Plated terminals formed on the solder dip surface,
In a printed circuit board on which a layer of masking resin or masking tape is formed to protect carbon contacts, solder lands of surface mount components, etc., a start mark indicating a peeling start position is integrally projected on the masking layer. A printed circuit board characterized by forming. (4) The printed circuit board according to claim (3), wherein the start mark is formed near the edge of the masking layer, and a through hole or a recess is formed in the part of the base material corresponding to the start mark. . (5) Plated terminals formed on the solder dip surface,
In a printed circuit board on which a layer made of masking resin or masking tape is formed to protect carbon contacts, solder lands of surface mount components, etc., one to several places on the base material corresponding to the edge of the masking layer are provided. A printed circuit board characterized by forming a recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6214489U JPH032672U (en) | 1989-05-29 | 1989-05-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6214489U JPH032672U (en) | 1989-05-29 | 1989-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH032672U true JPH032672U (en) | 1991-01-11 |
Family
ID=31591027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6214489U Pending JPH032672U (en) | 1989-05-29 | 1989-05-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH032672U (en) |
-
1989
- 1989-05-29 JP JP6214489U patent/JPH032672U/ja active Pending
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