JPH0326769B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a distance measuring device used, for example, as a distance measuring device for a camera equipped with an automatic focusing device, and more specifically, the present invention relates to a distance measuring device that is arranged at a predetermined interval and receives images in the distance measuring direction. The present invention relates to an improvement in a distance measuring device which has two light receiving means each consisting of a plurality of light receiving elements and which determines the distance to a distance measuring object from the correlation of the outputs of the light receiving means. [Prior Art] As the conventional distance measuring device as described above, those shown in FIGS. 1 to 3 are known. Figure 1 is a schematic plan view of the configuration of the device that projects an image in the ranging direction onto a pair of photodetector arrays, and Figure 2 detects the phase where the arrangement patterns of the photodetector outputs of the pair of photodetector arrays most match. FIG. 3 is a block circuit diagram for digitizing the output of the light receiving element. In FIG. 1, images in the distance measurement direction I are projected by lenses 1 and 2, respectively, onto a pair of light-receiving element arrays 3 and 4 arranged side by side with a certain distance d between them. Here, the constant distance d is the distance between the light-receiving elements in the light-receiving element rows 3 and 4 onto which the image of the distance-measuring object T is projected when the distance-measuring object T is at an infinite distance. Then, a distance measurement target T located at a distance l from lenses 1 and 2
When the distance x between the light-receiving element on which the image of
The distance l is determined by l=d×f/x. f is the focal length at which the lenses 1 and 2 form an infinite image on the light receiving element rows 3 and 4. However, distance x
is determined by the detection circuit shown in FIG. In FIG. 2, 3 and 4 are light-receiving element rows similar to those in FIG. 1, and 5 and 6 are light-receiving element rows 3,
4 is a binarization circuit array that binarizes the output at a predetermined logic level; 7 and 8 are shift registers; 9 is a coincidence detection circuit array; 10 is a counter; and 11 is a judgment control circuit. The analog output of each light-receiving element in the light-receiving element rows 3 and 4 is digitally converted to "0" or "1" at an appropriate threshold level by the respective binarization circuits in the binarization circuit rows 5 and 6. and written into shift registers 7 and 8. The output of each bit of the shift registers 7 and 8 is a combination of comparing the outputs of the light-receiving elements of the light-receiving element rows 3 and 4 onto which images at infinity are projected and the outputs of the corresponding light-receiving elements in the order of arrangement. It is input to the match detection circuit array 9. Each circuit in the match detection circuit array 9 is as follows:
If the two inputs from shift registers 7 and 8 are the same, "1" is output, and if they are different, "0" is output. The counter 10 counts the output "1" from the match detection circuit array 9 and outputs the number to the judgment control circuit 11. The judgment control circuit 11 is
After memorizing this number, shift register 7 or 8
is shifted by 1 bit, and the output number of the counter 10 after the shift is stored again. Furthermore, after repeating the shifting of the shift registers 7 and 8 and the storage of the output number of the counter 10 a predetermined number of times, the judgment control circuit 11 determines the maximum value among the stored output numbers of the counter 10. . The state in which the maximum number of outputs is obtained is the state in which the arrangement patterns of the light receiving element outputs of the light receiving element rows 3 and 4 are the most consistent, and the number of shifts until this maximum number of outputs is obtained is as shown in Figure 1. Corresponds to distance x. In other words, when calculating the distance l to the distance measurement target T using this number of shifts,
Instead of the constant distance d between the pair of light receiving element rows 3 and 4, a value obtained by dividing the distance d by the arrangement pitch of the light receiving elements of the light receiving element rows 3 and 4 may be used. but,
In the case of a distance measuring device of an automatic focusing device, it is not necessary to calculate the distance l one by one.If the focusing lens is moved in the optical axis direction corresponding to the number of shifts mentioned above, the optical axis direction of the focusing lens is This means that the distance l has been found based on the position. Note that, as can be seen from the above explanation in FIG. 2, the registers to which the digital outputs of the binarization circuit arrays 5 and 6 are written need not both be shift registers, but at least one of them must be a shift register. Good to have. Further, a circuit as shown in FIG. 3 is used for each of the binarization circuits in the binarization circuit arrays 5 and 6. In FIG. 3, 12 is a photodiode which is a light-receiving element constituting the light-receiving element rows 3 and 4 in FIGS. 1 and 2; 13 and 14 are switching transistors;
15 is a capacitor, 16 is an inverter, V _D is a drive voltage for photodiode 12, and G and C are operating signals for switching transistors 13 and 14, respectively. In this binarization circuit, switching transistors 13 and 14 are turned off and a driving voltage is applied to photodiode 12 to perform image projection, and then switching transistor 14 is temporarily turned off by actuation signal C. After turning on the capacitor 15 and discharging the capacitor 15, the operation signal C is further turned on.
The capacitor 15 is charged by turning off the switching transistor 14 with the activation signal G, then turning on the switching transistor 13 with the activation signal G, and after a certain period of time has passed, the switching transistor 13 is further turned on with the activation signal G. is turned off, and during that time, if the charging voltage of the capacitor 15, which is carried out by a current approximately proportional to the intensity of light received by the photodiode 12, exceeds the threshold voltage of the inverter 16, the output of the inverter 16 becomes " Reversed from “1” to “0”,
If the charging voltage has not reached the threshold voltage, the output of the inverter 16 remains "1", thereby converting the output of the photodiode 12 into a binary value. In this case, if the time from turning on to turning off the switching transistor 13 is too long, all the capacitors 15 will be charged above the threshold voltage; on the other hand, if the time is too short, all the capacitors will be charged Since the charging voltages of all capacitors 15 do not reach the threshold voltage, and the array patterns of the binary outputs of the light receiving element arrays 3 and 4 match in all phases, the distance x information will no longer be available. Therefore, the time from when the switching transistor 13 is turned on to when it is turned off is the same as that of the light receiving element array 3,
It is necessary to set the amount of light received by the entire light receiving element No. 4 in consideration, but this type of control has the disadvantage that it is generally complicated. Furthermore, in the conventional distance measuring device as described above, if relatively different noise is superimposed on the output of one or both of the light receiving element rows 3 or 4, erroneous ranging information may be obtained. There is also the disadvantage that distance measurement information may not be obtained at all. FIG. 4 shows an example of such a case. A in Fig. 4 is a curved waveform that approximates the output array pattern when no noise is superimposed on the outputs of the light-receiving element arrays 3 and 4, or when noise is superimposed with relatively no difference even if superimposed. B shows the case where noise is superimposed on the trapezoid as shown by the relative hatching on the output of the light-receiving element array 3.
Similarly, C shows the case where noise is superimposed on the triangle. The vertical axis of the figure is the output of the constituent light receiving elements, that is, the strength of the charging current or the charging voltage of the capacitor 15 in FIG. 3, and the dashed line is the threshold level. In the case of A, the light receiving element rows 3 and 4
A conversion array pattern of approximately the same light receiving element output can be obtained for which matching phase can be obtained, but in the case of B and C,
Either no coincident phase is determined, or an incorrect coincident phase is determined. In order to eliminate the above-mentioned drawbacks, the present inventors first decided to change the output of the light-receiving elements to the output of the light-receiving element array instead of the output arrangement pattern of the light-receiving element array as shown in FIG. We have invented a distance measuring device that converts the output of the maximum light-receiving element as a reference into a rank number with a predetermined output difference as a step, and determines the matching phase of the converted rank number array pattern. The invention was previously filed in Japanese Patent Application No. 80416/1983. According to this, even if the output array pattern of a pair of light-receiving element arrays has noise superimposed on one side as shown in B and C in Figure 4, the noise is removed by the conversion array pattern, so the noise is reduced. This provides the advantage that matching phases can be detected without being affected. However, even in this distance measuring device, when the output difference between each light receiving element in the light receiving element array is less than a predetermined output difference, the rank number uniformly becomes the highest rank number and a matching phase is not detected. A problem arises. [Object of the Invention] The present invention provides a measurement system that converts even when the output difference between each light receiving element in a light receiving element row is small, into a rank number array pattern with a difference between the light receiving elements, and detects an accurate coincident phase. The present invention provides a range device. [Structure of the Invention] The present invention includes a light receiving means in which two sets of light receiving element rows each including a plurality of light receiving elements are arranged at a predetermined interval;
a plurality of comparison means provided corresponding to each of the plurality of light-receiving elements, which compares whether or not the amount of light received by the light-receiving element reaches a predetermined value, and outputs a signal when the amount of light received by the light-receiving element reaches a predetermined value; and the comparison means peak detecting means for detecting a peak signal by detecting that at least one of the outputs of the peak signal has reached the predetermined value; and a pulse generator for generating a plurality of clock pulses at predetermined time intervals based on the output of the peak detecting means. means, a plurality of counter means, and a plurality of gate means for determining the outputs of the plurality of comparison means in synchronization with the output clock pulses of the pulse generation means and causing the plurality of counter means to count the determination results. By outputting the count values counted by each of the plurality of counter means as quantization information, the quantization information output for one of the light receiving element arrays and the other light receiving element arrays are combined. In a distance measuring device that measures the distance to a target by comparing the quantized information outputted for one and detecting a match, the total output from the comparing means is synchronized with the first output clock pulse. A reset means is provided for outputting a reset signal for resetting the comparison means and the counter means when the same signal is output, and the time interval of the clock pulses generated at the predetermined time interval is adjusted based on the reset signal. 1/n (n>1),
A distance measuring device characterized by performing distance detection again;
It is in. [Example] The present invention will be described below based on the example shown in FIGS. 5 to 7. Fig. 5 is a circuit diagram showing an example of the conversion circuit of the distance measuring device of the present invention, Fig. 6 is a graph showing the relationship between the output arrangement pattern of the light receiving element array and the arrangement pattern of the conversion output, and Fig. 7 is the main part of the detection circuit. This is an operation flowchart. In FIG. 5, 121 to 123 are photodiodes, 131 to 133 and 141 to 143 are switching transistors, 151 to 153 are capacitors, 161 to 163 are inverters, V _D is the drive voltage of the photodiodes, and G and C are switches. The configuration thereof is the same as that of the circuit shown in FIG. 3, except that the activation signal C operates the switching transistors 141 to 143 via the OR gate 17. Note that although the figure only shows the circuit portions corresponding to the three light receiving elements in the light receiving element array,
Needless to say, the number of light-receiving elements is parallel to each other. R is a reset signal that generates only one "0" pulse at the same timing when the operating signal C turns on the switching transistors 141 to 143, and φ is a clock that generates "0" one after another at fixed or different time intervals. It's a signal. This conversion circuit, prior to starting the conversion operation,
The switching transistor 14 is activated by the activation signal C.
1 to 143 are turned on and capacitors 151 to 15
3 discharge is performed, and at the same time, the reset signal R
The "0" pulse is directly applied to the R terminal of the serial-in-parallel out shift register 18, and via the inverter 19 and the NOR gate 20 to the R terminals of the flip-flops 21, 22, the binary counter 23, and the 2-bit binary counters 24-26. each input and resets all of their Q outputs to "0". In this state, Q ₀ ~
Q ₂ output “0” and binary counter 23 Q ₀ ~ _{Q 2}
The outputs of the OR gates 27 to 29 which respectively input the output "0" are "0", the output of the NAND gate 34 is "1", and the Q0 to _Q3 outputs of the serial-in-parallel out shift register 18 are " ₀ ". 0” and the Q ₁ to _{Q 4} outputs “0” of the binary counter 23 are respectively input to the OR gate 30.
The output of .about.33 is also "0", therefore the output of NAND gate 35 is also "1". Furthermore, the output of the AND gate 36 inputting all the Q outputs "0, 0" of the 2-bit binary counters 24 to 26 is "0", and the output of the AND gate 36 is "0".
The output of the inverter 38 which is input to the terminal of the flip-flop 21 is "1", and the output of the NAND gate 37 inputting them is "1".
Inverter 39 and NAND gate 40 to C terminal of
The input of the clock signal φ via the NAND gate 40 is blocked by the "0" of the Q output of the flip-flop 21, which has been reset. The NOR gates 41-43 which input the outputs of the inverters 161-163 are also closed by the output "1" of the NAND gate 34, and the output is "0". From this state, the switching transistor 1 is further activated by the activation signal C via the OR gate 17.
41 to 143 are turned off, and then the switching transistors 131 to 133 are turned on by the operating signal G, and the charging current of the output of the photodiodes 121 to 123, which are projecting images in the distance measurement direction, flows into the capacitors 151 to 153. When this happens, conversion of the light receiving element output begins. That is, when capacitors 151 to 153 are charged and any one of the outputs of inverters 161 to 163 is inverted to "0", the output of NAND gate 37 is inverted to "1", and therefore the output of inverter 38 is inverted to "1". The output is inverted to "0", the Q output of the flip-flop 21 is set to "1", and the clock signal φ is inputted to the C terminal of the binary counter 23 via the inverter 39 and the NAND gate 40. Thereby the binary counter 23
counts the “0” pulses of the clock signal φ as shown in the binary counter output table in Table 1,

【table】

[Table] When all Q ₀ to Q ₂ outputs become “1”, the output of NAND gate 34 is inverted to “0”, and then
When the outputs of _Q1 to _Q4 all become "1", the output of the NAND gate 35 is inverted to "0". Until then, the Q output of flip-flop 22 is “0”
During this period, the output of the NAND gate 34 becomes "0" three times. Therefore, if the output of the inverters 161-163 is inverted from "1" to "0" when the output of the NAND gate 34 becomes "0" three times, the output of the NAND gate 41-43 becomes "0" each time.
is “1” in the 2-bit binary counters 24 to 26.
Outputs a rising pulse. The 2-bit binary counters 24-26 thereby count the number of rising pulses up to a maximum of three. If the outputs of all inverters 161-163 are inverted between the time the output of any one of the inverters 161-163 is inverted to "0" and the time 7 pulses of the clock signal φ are input to the binary counter 23, the outputs of all inverters 161-163 are If it is inverted to “0”, the total count number of the 2-bit binary counters 24 to 26 is 3, that is,
Q output becomes "1, 1". In that case, the converted output pattern of the light-receiving element output becomes flat and a matching phase is not detected (see the sixth section described below).
(If the converted output pattern shown in Figure B is obtained) or an erroneous coincident phase will be detected. On the other hand, any of the remaining inverters 161 to 1
If the output of the clock signal φ does not invert to "0" within the 7th pulse of the clock signal φ, but inverts to "0" between the 8th pulse and the 15th pulse, the output of the clock signal φ
The bit binary counters 24 to 26 output 2, that is, "1, 0", and when the pulse is inverted from the 16th pulse to the 23rd pulse without being inverted yet, the corresponding 2-bit binary counters 24 to 26 output 1, that is, "0". .
counts 30 pulses, all Q ₁ to Q ₄ outputs become “1”, and the output of NAND gate 35 becomes “0”
By inverting the Q output of the flip-flop 22 to "1", the NOR gate 4
1-43 are closed, and the count numbers of 2-bit binary counters 24-26 are fixed. In this way, if the outputs of the 2-bit binary counters 24 to 26 do not all become 3, that is, "1, 1", there are irregularities in the conversion output pattern, so it is difficult to effectively determine the coincident phase between the photodetector arrays. It will be done. This is the case when the conversion output pattern shown in Figure 6C is obtained, and therefore the determination of ``Are all the converted values the highest values?'' in the flowchart of Figure 7, which will be described later, becomes ``No''. , in this case, as shown in the flowchart of FIG.
As in the conventional distance measuring apparatus shown in FIGS. 3 to 3, coincident phase detection is performed, and the distance information obtained as a result is output and displayed. Also, as mentioned above, all 2-bit binary counters 24 in which matching phases are not effectively detected.
~ If the count of 26 becomes “1, 1”,
As a result, distance detection will be performed again as described below. That is, the output of the AND gate 36 is inverted to "1", and the output turns on the switching transistors 141 to 143 to discharge the capacitors 151 to 153, and also connects the flip-flops 21 and 22 and the binary counter 23 via the NOR gate 20. Then, the 2-bit binary counters 24 to 26 are reset, and the _Q0 output of the serial-in-parallel out shift register 18 is inverted to "1". 2-bit binary counter 2
When 4 to 26 are reset, AND gate 36
The output returns to "0" again, thereby turning off the switching transistors 1141-143 and charging the capacitors 151-153 again. Then, when the output of any one of the inverters 161 to 163 is inverted to "0" again, the Q output of the flip-flop 21 is set to "1".
The binary counter 23 starts counting the "0" pulses of the clock signal φ again. but,
This time, the Q ₀ output of the serial-in-parallel out shift register 18 is “1”, so
The outputs of the OR gates 29 and 33 inputting it are "1" from the beginning, so when the Q ₀ and Q ₁ outputs of the binary counter 23 both become "1", the output of the NAND gate 34 becomes "1". When the output of the NAND gate 35 is inverted to "0" and all the outputs of _Q1 to _Q3C become "1", the output of the NAND gate 35 is inverted to "0" and the count number of the 2-bit binary counters 24 to 26 is to be fixed. That is, Noah Gate 41-4
3 is opened when the binary counter 23 counts 3 pulses, 7 pulses, and 11 pulses, and the count number of the 2-bit binary counters 24 to 25 is fixed when 14 pulses are counted. In contrast to the last time when the light receiving element output was ranked and converted from 3 to 0 at a time interval of 8 pulses, this time the light receiving element output is similarly ranked from 3 to 0 at a time interval of 4 pulses. Therefore, this time, even if the output difference between the light-receiving elements is smaller than last time, it is more likely that some light-receiving elements will be ranked 2 or lower. Even with this, the 2-bit binary counter 24
When all the outputs of ~26 become 3, that is, "1, 1", the output of the AND gate 36 becomes "1" again, and the _Q1 output of the serial in parallel out register 18 also becomes "1". At the same time, the capacitors 151 to 153 are once discharged, the flip-flops 21 and 22, the binary counter 23 and the 2-bit binary counters 24 to 26 are reset, and the conversion of the light receiving element output is redone. And this time, since the Q ₀ and Q ₁ outputs of the serial-in-parallel out shift register 18 are “1”, the Q ₀ output of the binary counter 23 is “1”.
Noah Gates 41-43 were opened when
Both Q ₁ and Q ₂ outputs of binary counter 23 are “1”
2-bit binary counter 24~
A count number of 26 is fixed. That is, the NOR gates 41 to 43 are opened when the binary counter 23 counts 1 pulse, 3 pulses, and 5 pulses, and the 2-bit binary counter 2
The count number of 4 to 25 is fixed when the binary counter 23 counts 6 pulses. Therefore, since the light receiving element output is ranked and converted from 3 to 0 at the time interval of 2 pulses,
It becomes easier for light receiving element outputs to be ranked 2 or lower, and it is possible to prevent the conversion output pattern from becoming 3 flat in all cases. The relationship between the array pattern of the converted outputs converted as described above and the output array pattern of the light receiving elements is as shown in FIG. 6, and A in FIG. 6 shows an example of the output array pattern of the light receiving elements. B shows the array pattern of conversion outputs when the outputs of the light-receiving elements are ranked, for example, at 8-pulse intervals of the clock signal φ, and C shows the array pattern of conversion outputs when they are ranked at 4-pulse intervals. There is. According to the conversion circuit shown in FIG. 5, the array pattern of conversion outputs shown in C in FIG. 6 can be obtained in practically most cases. Accurate distance measurement can be performed by inputting the phase difference into the shift registers corresponding to registers 7 and 8 and finding the phase difference where the converted output array patterns of both light-receiving element arrays match, as in the detection circuit shown in Fig. 2. It turns out. In this case, the shift register is a 2-bit binary counter 24-2.
When the output of 6 etc. is input directly, the number of shift registers and coincidence detection circuit arrays is doubled as shown in Fig. 2, and the counter outputs of two coincidence detection circuit arrays are both "1". Then, the output of the AND circuit string that outputs "1" is counted. Before that, the decision control circuit is activated by setting the flip-flop 22 of FIG.
Since the output of the NAND gate 35 is inverted from "1" to "0", the outputs of the 2-bit binary counters 24-26, etc. are input to the shift register. Thereby, the above-mentioned matching phase detection is performed. Further, when the number of inversions of the AND circuit 36 to "1" reaches a predetermined number of times, the determination control circuit determines that a converted output pattern from which a matching phase can be detected cannot be obtained, and displays a display indicating that distance measurement is not possible. The main operations of the detection circuit including the conversion circuit shown in FIG. 5 described above are shown in FIG. 7, and δ=
1EV indicates, for example, the case where the time interval of 8 pulses of the clock signal φ in the explanation of FIG. 5 corresponds to 1EV of the difference in intensity of light received by the light receiving element. Also,
The n-value conversion is not limited to the 4-rank conversion shown in FIG.
This indicates that any n-rank change of 2 or more is sufficient. In other words, if a flat conversion pattern with all the conversion values being the highest values is obtained and distance detection is not possible, the slice level is successively reduced to 1/2 until it becomes 1/8 EV and the n-value conversion is redone. If a non-flat pattern is obtained, matching phase detection is performed and distance information is output and displayed. The slice level δ can be made as fine as you like, but in reality it is meaningless to make it finer than (1/8) EV, so even if (1/8) EV is used, when all the converted values reach the maximum value, the measurement It is said that it is impossible to reach. [Effects of the Invention] As is clear from the above description, according to the present invention, the outputs of the light receiving elements are ranked and converted based on the output of the highest output light receiving element in the light receiving element array, and the converted output array pattern is used. Since matching phases are detected, even if noise with a relative difference between the photodetector arrays is superimposed on the output of the photodetector, the effect of eliminating the influence of such noise can be obtained. Instead, an excellent effect can be obtained in that the array pattern of the converted output is obtained in a form in which matching phases can be detected, and the occurrence of inability to measure distance or incorrect distance measurement is greatly reduced.

[Brief explanation of drawings]

Figure 1 is a schematic plan view of the configuration of the device that projects an image in the ranging direction onto a pair of photodetector arrays, and Figure 2 detects the phase where the arrangement patterns of the photodetector outputs of the pair of photodetector arrays most match. 3 is a block circuit diagram of the light receiving element output, FIG. 4 is an output graph showing an example in which noise is superimposed on the output of the light receiving element array, and FIG. 5 is a diagram of the distance measuring device of the present invention. FIG. 6 is a circuit diagram showing an example of the conversion circuit, FIG. 6 is a graph showing the relationship between the output arrangement pattern of the light receiving element array and the arrangement pattern of the conversion output, and FIG. 7 is a flowchart of the main operations of the detection circuit. 1, 2... Lens, 3, 4... Light receiving element array,
5, 6... Binarization circuit array, 7, 8... Shift register, 9... Coincidence detection circuit array, 10... Counter, 11... Judgment control circuit, 12, 121-12
3...Photodiode, 13,131-13
3,14,141-143...Switching transistor, 15,151-153...Capacitor, 16,161-163...Inverter, 1
7,27,33...OR gate, 18...Serial in parallel out shift register, 19,3
8, 39... Inverter, 20, 41-43...
Noah Gate, 21, 22...Flip Flop,
23...Binary counter, 24-26...2-bit binary counter, 34, 35, 37, 40
...Nand Gate, 36...And Gate, C,
G...operation signal, R...reset signal, φ...clock signal, _VD ...drive voltage.

Claims (1)

[Scope of Claims] 1. A light receiving means in which two sets of light receiving element rows each consisting of a plurality of light receiving elements are arranged at a predetermined interval, and a light receiving means provided corresponding to each of the plurality of light receiving elements, and an amount of light received by the light receiving element. a plurality of comparing means for comparing whether or not has reached a predetermined value and outputting a signal when the predetermined value is reached; A peak detection means for detecting a signal, a pulse generation means for generating a plurality of clock pulses at predetermined time intervals based on the output of the peak detection means, a plurality of counter means, and a clock pulse synchronized with the output clock pulse of the pulse generation means. and a plurality of gate means for discriminating the outputs of the plurality of comparison means and causing the plurality of counter means to count the discrimination results, and quantizing the count value counted by each of the plurality of counter means. By outputting the information as information, comparing the quantization information output for one of the light receiving element arrays with the quantization information output for the other one of the light receiving element arrays and detecting a match. In a distance measuring device that measures the distance to a distance measurement target, when all the signals from the comparison means are output in synchronization with the first output clock pulse, the comparison means and the counter means are The apparatus is characterized in that a reset means is provided for outputting a reset signal, and based on the reset signal, the time interval of the clock pulses generated at the predetermined time interval is set to 1/n (n>1), and distance detection is performed again. distance measuring device. 2. It has a means for counting the number of outputs indicating a quantization level indicating the maximum received light intensity and a quantization level setting means for changing the quantization level, and the counting means is configured to perform counting for different quantization levels. A distance measuring device according to claim 1.