JPH03271925A - Memory disk device - Google Patents

Abstract

PURPOSE:To improve the versatility of a memory disk device by converting the disk access instruction signal from a personal computer to an address signal and a read/write signal related to a semiconductor memory. CONSTITUTION:This device is provided with a first signal generating means (a) which generates various control signals related to a motor and a magnetic head in accordance with the disk access instruction signal from the personal computer and a second signal generating means (b) which generates the address signal and the read/write signal related to the semiconductor memory in accordance with various control signals. A semiconductor (c) from which the data is read out in accordance with the signal from the second signal generating means (b) is provided. That is, the disk access instruction signal from the personal computer is converted to the address signal and the read/write signal related to the semiconductor memory (c) by the first signal generating means (a) and the second signal generating means (b). Thus, IO control soft of DOS (disk operating system) standards can be used, and the versatility of the memory disk device is improved.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a memory disk device that can use standard BiO2 and has improved versatility. a first signal generating means that generates various control signals related to the semiconductor memory; and a second signal generating means that generates address signals and read/write signals related to the semiconductor memory according to the various control signals.
The second signal generating means is characterized in that it comprises a semiconductor memory from which data is read out in accordance with the signal from the second signal generating means.

[Industrial application field]

The present invention relates to a memory disk device, and particularly to a memory disk device that can be easily replaced with a disk drive device without changing software on a personal computer.

In many cases, DOS (disk operating
The program medium of a personal computer (hereinafter referred to as a personal computer) that operates under the control of
Flexible disks (floppy disks) and hard disks are used. For this reason, personal computers are equipped with a floppy disk drive device or a hard disk drive device depending on the type of media.

Hereinafter, in this specification, a floppy disk drive device and a hard disk drive device will be simply referred to as a drive device.

Drive devices involve mechanical operations such as disk rotation and head seeking, and have the drawback of being vulnerable to vibration and dust. In particular, in the case of FA (factory automation) personal computers installed in various industrial machines, such as robots and handling equipment, which are used in adverse environments, this may pose a problem in terms of durability and reliability.

Therefore, in recent years, instead of a drive device, a memory disk device that does not involve mechanical movement has been used. Typical memory disk devices include: ■ One-sided bank memory type, ■ One-sided 10 memory type, etc. is well known.

[Conventional technology]

Bank memo! - Also called bank switching memory, extended memory is managed in bank units via page windows on main memory. FIG. 10 is a configuration diagram of an example.

The bank memory circuit 10 connects to the CPU (central processor) of the personal computer via an expansion bus 11.
a bus interface 12 connected to
Memory circuits 16, 17, etc. are provided with an address buffer 13, a control buffer 14, and a data buffer 15, and follow bank switching signals from the personal computer.
- Equipped with a memory selection circuit 18 that switches n in bank units.

Each page of a window separately set on the main memory of the personal computer is made to correspond to each bank of extended memory 16, 17, . . . n.

IO module 1 - A method of treating an ememory circuit as a virtual IO device. FIG. 11 is a configuration diagram of an example of this method. The IO memory circuit 20 includes a bus interface 22 connected to the CPU of the personal computer via an expansion bus 21, and an address buffer. 23, a control buffer 24, and a data buffer 25, and a memory address setting circuit 26 that sets a memory address according to a read/write instruction from a personal computer.
, a memory data access circuit 28 that accesses the memory circuit 27 according to a set memory address. The extended memory 27 can be treated as an external device.

[Problem to be solved by the invention]

However, although such conventional methods use semiconductor memory that does not involve mechanical movement and are superior in that reliability and durability can be improved, the DO3 standard IOi
#Jl software (BI OS: basicinpu
There were problems in that it was not possible to use the output system, required separate driver software for bank memory management and 10 memory management, and was inferior in versatility.

The present invention was made in view of these problems, and
The purpose is to provide a memory disk device that can use standard BIO3 and has improved versatility.

[Means to solve the problem]

In order to achieve the above object, the present invention has a first signal generating means a which generates various control signals regarding a motor and a magnetic head in accordance with a disk access instruction signal from a personal computer, as shown in FIG. , a second signal generating means for generating address signals and read/write signals for the semiconductor memory according to the various control signals, and a semiconductor memory C from which data is read out according to the signals from the second signal generating means. It is characterized by:

[Effect]

In the present invention, when a disk access instruction signal is issued from a personal computer, various control I signals regarding the motor and magnetic head are output from the first signal generating means a, and these signals are transmitted to the semiconductor memory memory by the second signal generating means. are converted into address signals and read/write signals related to the data.

Therefore, when viewed from the personal computer side, the semiconductor memory C is recognized as if it were a mechanical disk device, and the semiconductor memory can be accessed using DOS standard BrO3.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

2 to 9 are diagrams showing an embodiment of a memory disk device according to the present invention.

First, a floppy disk drive device (hereinafter referred to as a drive device), a part of which is used in this embodiment, will be described.

In FIG. 2, the drive device 30 includes a control section 31 and a mechanism section 32.

The control unit 31 includes an interface buffer 34 connected to a floppy disk interface 33 of a personal computer.
, a floppy disk control circuit 35 as a first signal generating means that generates various control W signals for the motor and magnetic head in accordance with a disk access instruction signal from a personal computer, and a floppy disk control circuit 35 that serves as a first signal generating means for generating various control W signals for the motor and magnetic head in accordance with a disk access instruction signal from a personal computer; It includes a write data control circuit 36 that converts into a write signal, and a read data control circuit 37 that converts a read signal from the FD into read data.

The mechanism section 32 also includes a floppy disk control circuit 35.
A motor control circuit 39 that controls starting/stopping of the motor unit 38 according to signals from the motor unit 38 comes into contact with the surface of the disk medium (i.e. FD) 40, or separates from the surface of the disk medium 40 and comes into contact with it, depending on the operating status of the motor unit 38. At times, magnetic information is written on the surface of the disk medium 40,
It is provided with a magnetic head 41 for reading data, and a magnetic read/write circuit 42 for generating magnetic information to be written on the disk medium 40 or reproducing a read signal from the read magnetic information.

Here, the waveforms of each part of the writing system and reading system for the disk medium 40 will be explained according to FIG. In addition,
Here, FM (frequency 5odula
tion>Recording method is taken as an example.

Write data is write data from the personal computer that expresses D=O if there is no data pulse D between two clock pulses C, and D=1 if there is. The flip-flop is alternately reversed between the clock pulse C and the data pulse D, and the direction and time of the write current applied to the magnetic head 41 are changed.
Perform magnetic recording on the surface.

On the other hand, for reading, the read voltage from the magnetic head 41 is differentially shaped to detect the peak voltage, and the reference voltage (OV) is
The signal that has been pulse-shaped in comparison with the above is used as the read data Read d-ata to be transferred to the personal computer.

The write/read operations of a floppy disk device are as follows:
Positioning of the magnetic head 41 is performed by rotating the disk medium 40 at a predetermined speed, positioning the magnetic head 41 according to instructions from a personal computer, and bringing the magnetic head 41 into contact with or releasing it from the track of the disk medium 40. (
This is done by specifying (recording areas forming concentric circles on the surface of the disk medium 40).

FIG. 4 is a block diagram of the memory disk drive device of this embodiment. The same reference numerals are given to the parts that are used from the configuration shown in FIG.

In this embodiment, a semiconductor memory section 50 is provided in place of the mechanism section 32 shown in FIG.

The semiconductor memory section 50 includes the floppy disk control circuit 3
A memory address generation circuit (second signal generation means) 51. generates various signals related to semiconductor memory access, such as control signals such as read/write signals and address signals, according to signals from 51. RAM (random access)
A memory circuit 52 consisting of a semiconductor memory such as S memory), and a serial t which converts serial string write data from the write data control circuit 36 into a parallel string.
o A parallel conversion circuit (second signal generating means) 53, a parallel-to-serial conversion circuit (second
signal generating means) 54.

According to this configuration, when the floppy disk control circuit 35 outputs various control signals related to the motor and magnetic head in accordance with the disk access instruction signal from the personal computer, these signals are sent to the memory address generation circuit 51.
are converted into address signals and read/write signals for the semiconductor memory. Then, the memory circuit 52 is accessed by the converted signal.

Therefore, when viewed from the personal computer side, the semiconductor memory section 50
and the mechanical section 32 of the floppy disk drive device can be recognized as the same, and DO3 standard BiO2 can be used. As a result, a memory disk device with improved versatility can be realized.

FIG. 5 is a diagram showing a specific example of the circuit of the semiconductor memory section 50. This example is an example applied to 640 KFD (FM recording method). Note that the same functional parts as in FIG. 4 are given the same reference numerals.

In FIG. 5, DIRC is a signal instructing the track selection direction, in other words, the direction of movement of the magnetic head 41 (L=
5TEP is a signal that instructs the movement step of the magnetic helad 41, HOLD is a head load designation signal that indicates access is valid, and VFOE is a signal that indicates that the drive device is The signal indicating the read state, R-DATA, is the read data (Read data) to be transferred to the PC, WG
is a signal indicating that the drive device is in the write state, W
D is write data input from the computer.
da, ta), TR0O is a signal indicating that the magnetic head 41 is located at the zero track, INDEX is a signal indicating that the magnetic head 4L is at the reference position of the disk, and CLR is a sector counter clear signal. be.

The memory address generation circuit 51 generates a down clock signal DOWN every 5 TEP when DIRC is at H level.
CLOCK or, when DIRC is at L level, an amplifier down clock generation circuit 158 consisting of an inverter gate 55 and a Nant gate 56, 57 that generates an up clock signal UP CLOCK every <5TEP, and UP/DOWN. A track counter 59 that counts CLOCK and generates 8-bit trunk data (which becomes the upper address of the memory circuit 52) AI4 to A□, and a master clock MCK CFMFM system 500K from the master clock circuit 6o.
H2 (twice the disk transfer speed 250KHz), MF
MFM system IMHz (twice the disk transfer speed of 500KHz)] is converted to 14-bit width (in the case of FM system, MFMFM system 15-bit width) sector data (becomes the lower address of the memory circuit 52) A0 to A, 3
, and a sector counter 6I that generates focus data B0 to Bt.

Here, the address width of this embodiment is determined as follows. That is, in the FM system, the capacity of one FD track is 5.208 bytes. In this method, two pieces of information, a clock bit and a data bit, are held as memory information, so one focus information in disc information corresponds to twice the capacity of memory information. Therefore, FM
The scheme requires 5.208 x 2 = 10,416 bytes, thus resulting in an address width of 14 bits.

However, the MFMFM method has a width of 15 bits.

The serial to parallel conversion circuit 53 includes a write data latch circuit 62 that generates a timing signal W-LATCH.
, W-LATCH, a write data shaping circuit 63, M that formats the WD from the personal computer in advance in order to synchronize with the W-LATCH.
a memory write pulse generation circuit 64 that generates a memory write signal WR based on CK, HOLD, and WC;
and write data shaping circuit 6 according to W-LATCH.
It is provided with a shift register 65 for converting the serial shaped data from 3 to 8-pin parallel data, and converts the WD input as a serial string into 8-bit wide parallel signals D0 to D.

The parallel-to-serial conversion circuit 54 includes an inverter gate 66 that generates a chip select signal C5, and an AND gate 6 that generates a read/write clock from HOLD and MCK.
7, a read data latch circuit 68 that generates a timing signal R-LATCH, and a read data latch circuit 68 that generates a timing signal R-LATCH, and a read data latch circuit 68 that generates a timing signal R-LATCH.
The 8-bit data read from the data creation circuit 69 and the memory circuit 52 is latched by CH and transferred to the personal computer as DATA.
, ~B2, and a memory read pulse generation circuit 71 that generates a memory read signal RD based on MCK, HOLD, and VF10,000. Converts parallel signals to serial signals.

Note that the TRoO generation circuit 72 is a circuit that generates a signal indicating a zero track when AI4 to A1 are all zeros, and the INDEX generation circuit 73 is a circuit that generates a signal indicating zero track when AI4 to A1 are all zeros.

The sector counter reset circuit 74, which is a circuit that generates a signal INDEX indicating a zero sector when A13 is all zero, is configured so that the value of A0 to A13 is 10.416 (F
In the case of the M method, when the MFMFM method 20,832> is exceeded, a signal CLR is generated to reset the sector counter 61. f).

The memory circuit 52 has a storage capacity equal to or greater than twice the capacity of the FD. For example, if the track capacity of one FD is 5.208 bytes, the maximum number of tracks is multiplied by 5,208 bytes. It has a storage capacity equal to or greater than twice the number.

Next, the operation of the circuit shown in FIG. 5 will be explained with reference to the timing charts shown in FIGS. 6 and 7 to 9.

About 59 (6) While DIRC is at H level, trunk address A 3 a is sent every 5 TEP.
~A! A value of 1 is counted and amplified, or DIRC
Trunk data A 1 every 5TEP while is at L level
The value of 4 to A z (is counted down. Note that A
14~A! The numbers written in the waveform of I (0, L2.3...
...255) is a count value and corresponds to the trunk number of the FD. Incidentally, the 0 track (the outermost track of the FD) is a system track for recording system information, and TR0O is output when the magnetic head 41 is positioned on this system track.

Regarding the Sef-Karan 61, the counter constantly counts MCK and generates bit address data B0 to B2 and sector & byte address data A, to A1.

B, ~Bt are created by dividing MCK by 21 to 21, and A
0 to A, 3 are created by dividing MCK by 24 to 217. One sector and the bytes within that sector are A0~
A is specified by 13, and the focus within the byte is specified by B, ~Bt.

Here, A14 to A made by the trunk counter 59
2. The relationship between B0 to B2 and A o "" A Is generated by the sector counter 61 is shown in the bit format of FIG.

The bit pattern of 25 bits in total consists of the upper 8 bits (
A14-A2. :hereinafter sometimes abbreviated as AU) corresponds to the trunk number of the FD, and the middle 14 bits (AO to A1
3: Hereinafter sometimes abbreviated as AL) corresponds to the FD sector number and the byte number within that sector, and the lower 3 bits (B, ~B, sometimes abbreviated as 2-base lower B) correspond to the bits within the byte. corresponds to the number. For example, if the total number of tracks of the FD to which this embodiment is applied is l, the number of sectors per track is n, and the number of bytes in one sector is m, the data capacity of the memory circuit 52 is at least 8mxnxj! x
It must be 2 bits or more (of course, information data such as an ID field is required in addition to the data).

Note that the values of l, n, and m vary depending on the formant format of the disc. For each commonly used format, the bit allocation in Figure 7 (number of focuses for AU, AL, and H)
Change as appropriate. Further, in this example, a memory circuit with a data width of 8 bits is assumed, but this data width is not particularly defined. The number of bits of AL and B in the bit allocation is changed according to the data width. For example, when the width is 16 bits, AL is set to 13 pins and B is set to 4 bits. When the width is 4 bits, AL is set to 15 pins and B is set to 2 bits.

Regarding the first part (8) When HOLD and WG are turned ON (H level) and the writing mode is entered, the WD from the PC is input.
After this WD is shaped by the write data shaping circuit 63,
The 8-bit parallel data (for example, 11
010111 h). This parallel data is then written to any address in the memory circuit 52 designated by B, AU, and AL. In addition, in FIG. 8, D, Ds D3 D, represents the presence or absence of Kronkvit C (1 = present 10 = absent), and the remaining glue, D4 Dg
Do represents the presence or absence of data bit D.

--Regarding (9) When HOLD and VFOE turn ON (H level) and enter the read mode, first, the count of the track counter 59 [(AI4 to A□) causes the memory circuit 52 to An upper address is designated.The address area of the memory circuit 52 designated by this upper address corresponds to a track of the FD.

Next, the count value of the sector counter 61 (A o
= A r s ), the subdivision area within the specified address area is specified in units of bytes (8-bit width).

The subdivision areas correspond to sectors of the FD.

Then, the count value of the sector counter 61 (Bo~
B,), the data of each bit is selected by the bit selection circuit 7.
0, and then transferred to the personal computer as R-DATA in the order of Do, D+, Dz, . . . , D according to the timing of R-LATCH.

As described above, in this embodiment, the mechanism section (reference numeral 3 in FIG.
2), a semiconductor memory section 50 is provided, and within this semiconductor memory section 50, a memory circuit 52 and various circuits that provide an interface between the control section 31 and the memory circuit 52, that is, a memory address generation circuit are provided. Since the circuit 51, serial to parallel conversion circuit 53, parallel to serial conversion circuit 54, etc. are provided, the memory circuit 52 can be recognized as if it were an FD from the personal computer side, and the Br applied to the FD can be recognized as if it were an FD.
O3(D.

The effect of being able to use the standard BIO3) of S is obtained.

Therefore, a memory disk device with improved versatility can be provided.

Further, according to the embodiment, in addition to the above effects, the following effects can be obtained.

1) The drive device and the memory disk device of this embodiment can be easily replaced by simply replacing the connector, and there is no need to be aware of the difference in device.

2) If the memory circuit 52 is made non-volatile by battery back-amplification or the like, the semiconductor memory section 50 becomes portable and can be handled in the same manner as an FD.

3) ROM (read only) in the memory circuit 52
If you use 5enSory), you can transform your FD-based computer into a ROM-based computer.

For example, if a BOOT program is installed in the ROM, the BOOT program in the ROM will be executed at the same time as the power is turned on, allowing silent startup.

4) Since there are no mechanical parts such as disk rotation or helad seek, read/write speeds can be increased, and durability can also be improved.

In addition, in the embodiment, an example of application of the FM recording method to an FD is shown, but the application is not limited to this, and recording methods such as MFM, MF2M, OCR, etc. may be used, and application to a hard disk drive device is also possible. It's okay.

〔Effect of the invention〕

According to the present invention, it is possible to provide a memory disk device that can use standard BIQs and has improved versatility.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Figs. 2 to 9 are diagrams showing an embodiment of a memory disk device according to the present invention, and Fig. 2 is a floppy disk whose part is used in the memory disk device. A block diagram of the drive device. Figure 3 is a waveform diagram showing the signal relationship of each writing/reading part of the floppy disk drive device in Figure 2. Figure 4 is a part of the floppy disk drive device in Figure 2. A block diagram of the memory disk device, FIG. 5 is a specific configuration diagram of the memory disk device, FIG. 6 is an operation waveform diagram of the track counter and sector counter, and FIG. 7 is the trunk data, sector &amp; byte data,
and a bit format diagram showing the focus data; FIG. 8 is an operational waveform diagram of the data write; FIG. 9 is an operational waveform diagram of the data read. Figures 10 and 11 are diagrams showing conventional examples. Figure 10 is a block diagram of a conventional memory disk device that uses one type of bank memory. Figure 11 shows a conventional memory disk that uses one type of bank memory. FIG. 2 is a block diagram of the device. a...First signal generation means, b...Second signal generation means, C...Semiconductor memory, 31...Control unit (first signal generating means), 51
...Memory address generation circuit (second signal generation means), 52 ...Memory circuit (semiconductor memory), 53
......Serial to parallel conversion circuit (second signal generation means), 54...Parallel to serial conversion circuit (second signal generation means)
(signal generating means).

Claims (1)

[Scope of Claims] a) first signal generating means that generates various control signals regarding the motor and magnetic head in accordance with a disk access instruction signal from a personal computer; and b) address signals and read/write signals regarding the semiconductor memory in accordance with the various control signals. A memory disk device comprising: second signal generating means for generating a write signal; and c) a semiconductor memory from which data is read in accordance with a signal from the second signal generating means.