JPH0327436A - Full adder - Google Patents

Abstract

PURPOSE:To reduce delay time and to obtain a fast speed full adder with less elements by setting a carry signal to be negative logic at every stage. CONSTITUTION:The full adder of n-stages which outputs a sum signal 01 and the carry signal Cn by receiving input signals C1 and C2 and the carry signal of negative logic, the inverse of Cn-1, and the full adder of n+1-th stage, which outputs a sum signal 02 and the carry signal of negative logic, the inverse of Cn+1 by receiving the carry signal Cn of n-th stage and input signals C3 and C4 are provided. In such a case, the carry signal is the negative logic at every stage. Thus, the carry signal for a subsequent stage is generated in one stage of a gate by inverting the logic of the carry signal at every stage, and outputting it. Thus, the adders in which delay time becomes a half of a conventional one and which can execute a high speed addition action can be constituted and the number of the elements can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital circuit, and more specifically, to a full adder used in an arithmetic device.

[Conventional technology]

FIG. 2 shows a circuit diagram of a conventional full adder configured using gates.

In the illustrated circuit diagram, input signals A and B are each branched into two, one of which is connected to the input of a first AND gate, and the other to the input of a first NOR gate. The outputs of the AND gate and the NOR gate are connected to the input of a NOR gate Gl3.

The outputs of NOR gate G13 are each branched into two,
One is connected to the input of the second AND gate, and the other is connected to the input of the second NOR gate. The inputs of the AND gate and the NOR gate include the previous stage, that is, the n-1th
Carry signal C of the full adder in the stage. -1 is also connected. The outputs of the second AND gate and the second NOR gate are connected to the input of a NOR gate Gl4.

The NOR game Gl4 outputs a sum signal S.

Furthermore, the input signals A and B are connected to the inputs of a third AND gate, and the output Gl 30 of the NOR gate G13 and the carry signal C7-1 from the previous stage are connected to the inputs of the fourth AND gate. . The outputs of the third and fourth AND gates are connected to the input of a third NOR gate. In this way, the third AND gate, the fourth AND gate
Game 1 and the third NOR gate are the composite game}Gl
5.

The output of the composite game Gl 5 is input to the inverter G16, and the inverter G16 carries the signal C. Output.

The full adder constructed as described above operates as follows.

For example, input signals A and B are "l゜" and "0", respectively.
゜", the output of the first AND gate and the first N
The outputs of the OR gates are both ゜゛0゜゛. This 2
Upon receiving the output, the output Gl 30 of the NOR game Gl 3
becomes the exclusive OR of the input signals, that is, "'1".

Here, the carry signal C. from the previous stage. , -1 is "1", the second AND is obtained by receiving O n-1 and Gl 30.
The output of the gate becomes "1", and the output of the second NOR gate becomes "0".Receiving these two outputs, the NOR gate
The output S of Gl4 becomes the exclusive OR of the input signal and the carry signal, that is, ``0''.

Further, in the composite gate G15, the third AND gate receives the input signals A and B, and the fourth AND gate receives the output G130 of the NOR gate G13 and the carry signal C n-1 from the previous stage. In response to these two outputs, the third NOR gate outputs "0".

The output II O I+ of the composite game Gl 5 is connected to the inverter G 1 . 6, and the carry signal Cn becomes ``1''.

That is, carry signal Cn is given by the following equation.

On=C,. *G1 30+A*B The values of the output S and co for various input values A, B and O n-1 values are shown in Table 1.

Table 1 Realizing such a conventional full adder with a CMOS circuit5 Then, 30 transistors are required in terms of the number of elements.

In addition, the carry signal C n-1 from the previous stage is input to this full adder, and is passed through the composite gate G1 before being output to the next stage.
5 and inverter Gl6, a delay of two gates occurs.

[Problem to be solved by the invention]

As mentioned above, conventional full adders have a large number of elements, and the carry signal from the previous stage propagates through two gates before being input to the next stage, so there is a delay of two gates. Therefore, there was a problem that a high-speed ripple carry full adder could not be used.

Therefore, the present invention aims to provide a high-speed full adder with a small number of elements by reducing the delay time.

[Means to solve the problem]

That is, according to the present invention, a first selector circuit receives first and second input signals and outputs an exclusive OR of the first and second input signals; A second circuit receives the carry signal which is the output and the carry signal from the previous stage and outputs the exclusive OR of the output and the carry signal as a sum signal.
a selector circuit, and a third receiving the first and second input signals, the output of the first selector circuit, and the carry signal from the previous stage, and outputting a carry signal that is a carry output to the next stage. In a full adder which performs binary addition of a large number of digits by taking into consideration carry-over from the lower digit, the carry signal is added to each stage by sequentially connecting circuits including a selector circuit via the carry signal. A full adder is provided which is characterized by negative logic.

[Effect]

In the full adder configured as described above, the carry signal is output in negative logic for each stage, so it is possible to eliminate the gate corresponding to the inverter 016 in the conventional full adder. In other words, by removing one of the two gates through which the carry signal from the previous stage is input until it is output as a carry signal to the next stage, the delay of two gates that occurs in the conventional adder can be reduced. , the full adder according to the present invention can reduce the delay to l gates.

Furthermore, by removing the inverter, the number of elements can also be reduced.

〔Example〕

Embodiments of a full adder according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the structure of one embodiment of a full adder embodying the present invention.

FIG. 1 shows an n-th stage full adder that outputs a sum signal 01 and a carry signal C, , upon receiving input signals Cl, C2 and a negative logic carry signal 10; nth
Stage carry signal C. and an n-th node which receives the input signals C3 and 04 and outputs the sum signal 02 and the carry signal τ of negative logic.
A circuit diagram of a +1 stage full adder is shown.

In the n-th stage full adder, the input signal C1 is branched into two, one is input to the transfer gate T2 via the inverter G1, and the other is directly input to the transfer gate T2.
connected to the input of l.

Input signal C2 is branched into two, one of which is connected to inverter G2.
The other is directly connected to the gate of the transfer gate T2 through the gate of the transfer gate T1.

The outputs of transfer gates Tl and T2 are combined at Sl and then branched into two, one of which is connected to the gate of transfer gate T3 via inverter G3, and the other directly connected to the gate of transfer gate T4.

The negative logic carry signal from the previous stage, that is, the (n-1)th stage, passes through inverter G4 and is branched into two, one of which is sent to the input of transfer game T4 via inverter G5, and the other is directly sent to the input of transfer gate T4. Transfer game} is connected to the input of T3.

The outputs of the transfer games T3 and T4 are combined at S2 and further connected to the output terminal of the sum signal Ol.

inverter G1 and G217) output GIO and G20,
That is, the inverted signals of input signals A and B are connected to the input of the first OR9 gate. Further, the output G30 of the inverter G3 and the negative logic carry signal On-1 are the second
is connected to the input of the OR gate.

The outputs of the lth and second OR gates are connected to the input of the lth NAND gate. The first and second OR gates and the first NAND gate constitute a composite game G6. The l-th NAND gate outputs the n-th stage carry signal C, .

In the n+1 stage full adder, the input signal C3 is branched into two, one of which is connected to the input of the transfer game T6 via an inverter G7, and the other directly connected to the input of the transfer game T50. The input signal C4 is branched into two, one of which is connected to the gate of the transfer gate T5 via an inharter G8, and the other directly connected to the gate of the transfer gate T6.

The outputs of transfer game T5 and T6 are combined at S3 and then branched into two, one being sent to the gate of transfer game T8 via inverter G9, and the other directly to the gate of transfer game T7. It is connected.

The carry signal C,, from the previous stage, that is, the n-th stage, passes through the inverter GIO and is branched into two, one of which is sent to the input of the transfer game T8 via the inverter Gll.
The other side is directly connected to the input of transfer game T7. Transfer game} The outputs of T7 and T8 are S
4 and is connected to the output terminal of the sum signal 02.

Input signals C3 and C4 are input to the first AND gate;
The output S30 from S3 and the nth stage carry signal C. ，
is connected to the input of the second AND gate. The first and second outputs are connected to the input of the first NOR gate. The first and second AND gates and the first NOR gate constitute a composite gate G12. 1st NO
The R gate receives the negative logic carry signal C, , + of the n+1 stage.
Outputs 1.

The full adder constructed as described above operates as follows.

In the n-th stage full adder, input signals Cl and C2 correspond to input signals A and B of the conventional full adder shown in FIG. Therefore, in order to compare the operations, input signals C1 and C2 are
Input signal A used in explaining the operation of a conventional full adder as
,B are selected. That is, the input signals C1 and C2 are set to "1'" and "O", respectively.

Since the input signal C2 is ``0'', the transfer gate Tl to which the input signal is connected via the inverter G2 becomes conductive, and the directly connected transfer gate T2 becomes non-conductive. Therefore, transfer game}Tl
The signal of the input signal C1, that is, "1" is output to the junction S1 of the outputs of the input signals C1 and T2.In this way, the exclusive OR of the input signals C1 and C2 is output to S1.

Since the output of 81 is "l", the transfer gate T4 directly connected to this output becomes conductive, and the transfer gate T3 connected via the inverter G3 becomes non-conductive.

Since the carry signal C from the previous stage, that is, the n-1th stage, is a negative logic carry signal, it is the inverted value of the carry signal C n-1 used in the explanation of the operation of the conventional full adder, ie, "'0". shall be. Therefore, the sum signal 01, which is the calculation result of the n-th stage full adder, has a value obtained by inverting the sum signal 7; twice, that is, "0". In this way, 101 has the inverted value of the negative logic carry signal O n-1, that is, the positive logic carry signal C. The exclusive OR of the outputs of -1 and 81 is output.

Further, in the composite game }G6, the first OR gate receives the inverted values G10 and G20 of the input signals C1 and C2 and becomes "1", and the second OR gate receives the input of the output of Sl and outputs "1". Output G30 and negative logic carry signal C from the previous stage. -, and outputs "O I+".

In response to these two outputs, the first NAND gate outputs "1" as the carry signal C0. That is, carry signal C. is expressed by the following equation.

As described above, the output 01 of the n-th stage full adder of this embodiment
The values of and co are the corresponding output values S and C in the description of the operation of a conventional full adder. -13- matches the value of . That is, the n-th stage full adder of this embodiment is
It basically operates in the same way as a conventional full adder.

Similarly, in the n+1 stage full adder, the input signal C3
The operation will be explained assuming that C4 and C4 are "1°" and "0"°, respectively.

Since the input signal C4 is "0", the transfer gate T5 to which the input is connected via the inverter G8 becomes conductive, and the directly connected transfer gate T6 becomes non-conductive. Therefore, transfer gates T5 and T6 The signal of the input signal C3, that is, "I I+" is output to the confluence S3 of the outputs of the input signal C3. In this way, in 83,
The exclusive OR of input signals C3 and C4 is output.

Since the output of S3 is II I I+, the transfer game }T7 directly connected to this output becomes conductive, and the transfer game }T8 connected via the inverter G9.
becomes non-conductive. If the carry signal C0 from the previous stage, that is, the n-th stage, is ``1'', the sum signal 02-14-, which is the operation result of the n+1-th stage full adder, is the value obtained by inverting Cn by the inverter G10. In other words, it becomes "'0". In this way, the exclusive OR of the output of S3 and the carry signal C, .

Furthermore, in the composite game G12, the first AND gate receives the input signals C3 and C4 and outputs "0'", and the second
The ND gate receives the output S30 of S3 and the carry signal C from the previous stage. and outputs “1 ++”.

In response to these two outputs, the first NOR gate outputs "0" as a negative logic carry signal.

That is, the negative logic carry signal = is expressed by the following equation.

C. +. =S30*C. +C 3 *C 4 As described above, the n+1 stage full adder of this embodiment operates basically in the same way as the conventional full adder.

The overall operation differs from the conventional one in that the logic of the carry signal is inverted for each stage and output.

When constructing a binary ripple carry full adder with two or more stages, it is sufficient to use a pair of full adders at the nth stage and the (n+1)th stage shown in FIG.

〔Effect of the invention〕

As explained above, in the full adder according to the present invention,
By inverting the logic of the carry signal and outputting it for each stage, the carry signal is generated to the next stage or can be done in one gate stage. Therefore, the delay time is also reduced to half that of the conventional one, and an adder capable of high-speed addition operation can be constructed. Furthermore,
By constructing a coincidence circuit and an exclusive OR circuit using transfer gates, the full adder of the present invention can be implemented with a CMOS circuit using 26 transistors.

That is, the number of elements can be reduced compared to the conventional full adder.

Therefore, the full adder according to the invention can be used over a wide range of applications.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of one embodiment of a full adder according to the present invention. FIG. 2 is a circuit diagram showing the configuration of a conventional full adder. (Main reference numbers) T1-T8...Transfer gate, 01-G
5,07~Gll,G16... Inverter, G
6... A composite gate that is better than an OR gate and a NAND gate, G12, G15... A composite gate that is better than an AND gate and a NOR gate, G13, GL4...
... NOR gate, Cl, C2 ... Input signal input to the n-th stage full adder, 10; π ...
・Negative logic carry signal of the n-1 stage full adder, 01
. . . Operation result of the n-th stage full adder, C. ...
...Carry signals of the n-th stage full adder, C3, C4・
...Input signal input to the n+1 stage full adder, 02......Arithmetic result of the n+1 stage full adder,
τ=... Negative logic carry signal of the n+1 stage full adder, CIO... Output signal of inverter G1, G20... Output signal of inverter G2, G
30... Output signal of inverter G3, C130
...Output signal of inverter 013. 1171

Claims (2)

[Claims] (1) receiving the first and second input signals;
a first selector circuit that outputs an exclusive OR of the input signals of the first selector circuit; A second signal that outputs the logical sum as a sum signal.
a selector circuit, and a third receiving the first and second input signals, the output of the first selector circuit, and the carry signal from the previous stage, and outputting a carry signal that is a carry output to the next stage. In a full adder, which is configured by sequentially connecting circuits including a selector circuit and a selector circuit via the carry signal, and performs binary addition of multiple digits in consideration of carrying from the lower digit, the carry signal is added at each stage. A full adder characterized by negative logic. (2) The full adder according to claim 1, wherein the first and second selector circuits are comprised of transfer gates.