JPH03276331A - Multiplier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a multiplier, and particularly to an improvement in the arrangement method of its unit adder cells.

[Conventional technology]

Figure 3 is a schematic diagram of the relative arrangement of unit circuit cells and the signal wiring between unit circuit cells in the layout pattern of a multiplier using the 8-bit x 8-bit quadratic Booth algorithm. . However, signal wiring between cells is omitted except for those necessary for explanation.

In the figure, 1 is a Booth decoder that outputs a control signal for generating partial products, and 2 is a carry-save adder that generates four 9-bit partial products, adds these partial products together, and outputs an intermediate phase.・Array (hereinafter referred to as C3A)
, 3 is an adder circuit that adds the intermediate sums from C3A2 and outputs the product of the lower 6 bits, and 4 is an adder circuit that adds the intermediate sums from C3A2 and outputs the product of the upper 9 bits.

Further, BS is a Booth shifter cell that outputs a 1-bit partial product, HA is a half adder cell, and FA is a full adder cell. 5 is the addition result signal wiring of the half adder cell HA or full adder cell FA constituting C3A2;
6 is a carry signal wiring of the half adder cell HA or full adder cell FA constituting C3A2, and 7 is a carry signal wiring of the half adder cell HA or full adder cell FA constituting the adder circuit 3.

2a is a Booth shifter cell placed at the lowest bit position of the first stage of C3A2, 2b is a Booth shifter cell placed at the second bit position of the first stage of C3A2, and 2c is a Booth shifter cell placed at the second bit position of the first stage of C3A2.
2d is a half adder cell placed at the second bit position of the first stage of C3A2, 2e is placed at the lowest focus position of the third stage of C3A2. Full adder cell, 2f is C3A
This is a full adder cell placed at the 2nd bit position of the 3rd row of 2.

In addition, 3a is a no\-fader cell that inputs the output signal of 2a, 3b is a half adder cell that uses the output signal of 2b and the carry signal of 3a as input, and 3C is the addition result signal of 2C and the carry signal of 3b. Full adder cell with input, 3d
is a full adder cell that inputs the addition result signal of 2d, a carry signal of 20, and a carry signal of 30, 3e is a full adder cell that inputs the addition result signal of 2e and a carry signal of 3d, and 3f is an addition of 2f. This is a full adder cell that receives a result signal, a carry signal of 20, and a carry signal of 3e.

Next, a method of arranging each unit circuit cell will be explained. For convenience, the column direction of C3A will be referred to as "vertical" and the row direction will be referred to as "horizontal."

In the case of a multiplier using the second-order Booth algorithm, an adder circuit 3 for two bits is required per stage of C3A to obtain the lower digit part of the product. In order to configure this adder circuit 3 using no\-fader cells and full adder cells,
Half adder cells 3a, 3b, and full adder cells 3c in one "vertical" row.

3d, 3e, and 3f are arranged and the necessary signal wiring is provided.

[Problem to be solved by the invention]

Since the conventional multiplier is configured as described above, the length of one side of the multiplier is determined by the length of the adder circuit that adds the intermediate sum from C3A and outputs the lower digit part of the product. There was a problem in that the element density as a whole decreased. This problem becomes even more pronounced when a cubic or higher-order Booth algorithm is used. This is because when the 9th-order Booth algorithm is used, an adder circuit that outputs the lower digit part of the product requires n unit adder cells for each partial product.

This invention was made in order to solve the above-mentioned problems, and the purpose is to obtain a multiplier that can improve the element density of the entire multiplier while realizing an array structure suitable for integration. shall be.

[Means to solve the problem]

The multiplier according to the present invention has a two-dimensional arrangement of unit adder cells in an adder circuit that adds intermediate sums from C3A and outputs the lower digit part of the product, and outputs signals from the same stage of C3A by hand. The unit adder cells are located in the same row.

[Effect]

In this invention, the adder circuit that adds the intermediate sums from C3A and outputs the lower digit part of the product is arranged so that the unit adder cells that use the output signals from the same stage of C3A as input are in the same row. Therefore, the height of the unit adder cell can be kept within the range of C3A-height per stage.

〔Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the relative arrangement of unit circuit cells and the layout pattern of a multiplier using the 8-bit x 8-bit quadratic Booth algorithm according to an embodiment of the present invention. FIG. 3 is a diagram schematically showing signal wiring. However, signal wiring between cells is omitted except for those necessary for explanation.

In the figure, the same reference numerals as in Figure 3 indicate the same or equivalent parts, and 8 is an adder circuit that adds the intermediate phase from C3A2 and outputs the product of the lower 6 bits.The arrangement method of the unit circuit cell is The cells are arranged in two vertical columns such that half-adder cells or full-adder cells receiving output signals from the same stage of C3A2 are located in the same row.

Further, in the arrangement of cells in the same row, the cells of the higher bits are closer to C3AZ. That is, half adder cells 3a, 3b are in the first row, and full adder cells 3c are in the second row.
, 3d, place full adder cells 3e and 3f in the third row,
Necessary signal wiring is provided.

According to this embodiment, the adder circuit 3 that adds the intermediate sums from C3A2 and outputs the product of the lower 6 bits of the product is replaced by a unit adder that receives the output signal from the same stage of C3A2. Since the cells are arranged in the same row, the height of the unit adder cell can be kept within the height of one stage of C3A2, which improves the element density of the entire multiplier. be able to.

In the above embodiment, the cells in the same row of the adder circuit 8 are arranged so that the higher bit cells are closer to C3A2, but the lower bit cells may be arranged closer to C3A2.

Further, in the above embodiment, an example of a multiplier using a second-order Booth algorithm was shown, but it goes without saying that the application can also be applied to a case where an n, (n>2) order Booth algorithm is used. , in this case, the cell position of the adder circuit 8 is n "vertical" columns.

Further, in the above embodiment, an ordinary carry adder circuit is used as the adder circuit 8.4, but the types of adder circuits that can be used are not limited to this.
For example, it may be an adder circuit that uses a high-speed technique such as carry look ahead or carry select.

Next, other embodiments of the invention will be described.

FIG. 2 is a diagram showing a layout pattern of a multiplier using the 8-bit x 8-bit second-order Booth algorithm in another embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same or equivalent parts. , 9 is an adder circuit, and in this embodiment, as in the above embodiment, the half adder cells or full adder cells receiving the output signal from the same stage of C5A2 are arranged in two vertical columns so that the half adder cells or full adder cells are located in the same row. The cells are arranged in a configuration in which the cells in adjacent rows are arranged in reverse order, that is, in the first row, the upper bit cells are closer to C3A2, in the second row, the lower bit cells are closer to C3A2, and in the third row, the cells with lower bits are closer to C3A2. are half adder cells 3a, 3b, full adder cells 3c, 3d, 3e, 3 so that the upper bit cells are closer to C3A2.
f is placed.

By arranging the cells in this manner, carry signal wiring from the half adder cells 3b, full adder cells 3d, and 3e can be wired without bending.

〔Effect of the invention〕

As described above, according to the multiplier according to the present invention, in the adder circuit that adds intermediate sums from the carry-save adder array (C3A) and outputs the lower digit part of the product, By arranging the adder cells two-dimensionally so that the unit adder cells that use the output signal from the same stage of C3A as human power are located in the same row, the height of the unit adder cell is set to the height of the above C3A-stage. This has the effect of being able to fit within a normal height range, realizing an array structure suitable for integration, and improving the element density of the entire multiplier.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the relative arrangement of unit circuit cells and signal wiring between unit circuit cells in a multiplier according to one embodiment of the present invention, and FIG. 2 is a diagram according to another embodiment of the present invention. A schematic diagram showing the relative arrangement of unit circuit cells in a multiplier and signal wiring between unit circuit cells. Figure 3 shows the relative arrangement of unit circuit cells in a conventional multiplier and the unit circuit. FIG. 3 is a schematic diagram showing signal wiring between cells. In the figure, 1 is a Booth decoder, 2 is a carry-save adder array (C3A), 8 is an adder circuit (first addition block) that outputs the lower digit part of the product, and 4 is the output unit that outputs the higher digit part of the product. BS is a Booth shifter cell, HA is a half adder cell, FA is a full adder cell, 5 is an addition result signal wiring, and 6 and 7 are carry signal wirings. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a multiplier that uses at least a second-order or higher-order Booth algorithm, a circuit block that outputs a control signal for generating partial products, generates a plurality of partial products according to the control signal, and adds the plurality of partial products. an array block formed by arranging unit circuit cells in an array that outputs the intermediate phase of the partial products; a first addition block that adds the intermediate sum of the partial products and outputs the lower digit part of the product; It is characterized by comprising a second addition block that adds intermediate sums of products and outputs a high-order digit part of the product, and that unit adder cells forming the first addition block are arranged two-dimensionally. Multiplier. (2) In the cell arrangement of the first addition block, unit adder cells that receive output signals from the unit circuit cells located in the same row of the array block are arranged in the same row. A multiplier according to claim 1, characterized in that: