JPH03277003A - High frequency high output amplifier - Google Patents

Abstract

PURPOSE:To realize a high efficiency for high and low power output by employing a FET with a large saturation output and a FET with a small saturation output and setting a voltage fed to a gate of one FET so that a drain current of the FET is almost zero an input of a signal. CONSTITUTION:A FET 11 with a large saturation output whose bias supply circuit is provided in other system and a FET 12 with a small saturation output whose bias supply circuit is provided in other system are connected in parallel via capacitors 131, 132 connecting gates and drains. Through the constitution above, a voltage fed to a gate of one FET is set to a value so that a peak voltage of an input signal does not exceed its pinch-off voltage so as to make a drain current of a relevant FET nearly zero. Thus, the operating FET is selected and the output is changed over. Through the gate voltage control as above, the FET with a large saturation output is used at the time of outputting high power and the FET with a small saturation output is used at the time of outputting low power respectively near their saturation output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency, high power amplifier used as a power amplifier of a communication device that transmits and receives high frequency signals.

In particular, the present invention relates to a high-frequency, high-output amplifier that has a configuration in which output power can be switched and achieves high efficiency at each output power.

[Prior Art] It is important that each circuit used in a mobile device such as a portable radio device has low power consumption.

In particular, the power consumption in the power amplifier during transmission accounts for a large proportion of the power consumption of the entire mobile device, and improving its efficiency has become a major issue.

Furthermore, it is essential for mobile devices to have the ability to switch output power depending on the distance from the base station, and it is required to maintain high efficiency even when using low output for a long time, just as when using high output. .

Generally, as a high-frequency amplifier with high efficiency and high output, a class B amplifier or a class F amplifier, which is a class B amplifier with a harmonic processing circuit added thereto, is used.

FIG. 4 is a diagram of an equivalent circuit of a conventional high frequency high output amplifier.

In the figure, in order to obtain a large output, a high frequency amplifier uses a large F with a gate width of several millimeters and a saturated output.
An ET (field effect transistor) 41 is used. The high frequency amplifier includes this FET 41 and an input/output matching circuit 43.
45, bias supply circuits 47, 49, and others. Here, the gate voltage v1 is applied to the input side of FET41.
．． The bias supply circuit 47 that supplies the drain voltage 4d is composed of a resistor, and the bias supply circuit 49 that supplies the drain voltage 4d to the output side is composed of an inductor that has a large actance with respect to the high frequency output. Note that the bias supply circuits 47 and 49 are incorporated into a part of the matching circuit,
Sometimes it is not possible to clearly distinguish between the two.

Incidentally, both class B amplifiers and class F amplifiers exhibit similar changes in output power and efficiency (drain efficiency) characteristics with respect to input power.

FIG. 5 is a diagram showing output power and drain efficiency characteristics with respect to input power in a class B amplifier and a class F amplifier.

These amplifiers exhibit high efficiency near the saturated output where the input power is high, but the efficiency remains low in the low output region where the input power is low. Therefore, in these amplifiers, special measures are taken at low output to improve efficiency.

Conventional techniques for maintaining high efficiency at low output include bias control that lowers the drain voltage of the FET at low output, or as shown in FIG. A method is used in which switches 65 and 67 are used to switch between the amplifier 63 and the amplifier 63, which has a small output.

[Problem to be solved by the invention]

However, the former method had the following problems.

■ At low output, where the output power is 1/10 or less compared to high output, sufficient efficiency cannot be obtained even if the drain voltage is lowered.

■ Since a large current flows through the drain, a dedicated variable output voltage DC/DC converter is required to switch the drain voltage. Moreover, since this converter has a complicated circuit configuration, the power conversion efficiency of the power supply circuit itself is poor, and when the efficiency of the til1 circuit is added to the efficiency of the entire amplifier, the configuration is not necessarily advantageous.

Furthermore, the latter method had the following problems.

■ Requires switches on both the input and output sides, resulting in insertion loss. In particular, the insertion loss on the output side is a factor that directly reduces the efficiency of the amplifier.

For example, if the insertion loss due to the switch on the output side is 1 dB, the resulting drop in efficiency will reach approximately 20%, and the impact on power consumption at high output cannot be ignored.

■ Since the switch on the output side is a high-frequency switch capable of handling high output, the power consumption for switching is large, the circuit size is also large, and it is expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency, high-output amplifier that has a simple configuration and can achieve high efficiency equivalent to that at high output even when the output is low.

[Means to solve the problem]

The present invention consists of an FET with a large saturated output and a small FE with a small saturated output, which has a separate bias supply circuit from this FET.
T, and a capacitor that connects the gate terminals of each FET and the drain terminals of each FET, and sets the voltage applied to the gate of either FET to a value such that the peak voltage of the input signal does not exceed its pinch-off voltage. The configuration is such that the FET to be activated is selected.

[For production]

The present invention has a configuration in which a large FET and a small FET with saturated outputs, which have separate bias supply circuits, are connected in parallel through capacitors connecting their respective gate terminals and drain terminals. In such a configuration, the voltage applied to the gate of one of the FETs is set to a value that does not allow the peak voltage of the input signal to exceed its pinch-off voltage, and the drain current of the corresponding FET is made approximately zero. , the FET to be activated is selected and the output is switched.

Here, the capacitors used on the gate side and the drain side can separate the bias supply circuit of each FET and also serve as a matching element for the FET with a small saturation output.

With such a configuration, by controlling the voltage applied to the gate of one of the FETs, the drain current can be reduced to zero and that FET can be turned off. That is, at high output, only the FET with a large saturated output is turned on, and the other one is turned off. Also, at low output, a small FE with saturated output
Only T is turned on and the other one is turned off.

By controlling the gate voltage in this way, a FET with a large saturated output can be used near its saturated output when the output is high, and a FET with a small saturated output can be used near its saturated output when the output is low. High efficiency can be achieved both at the time of output.

Note that in such a configuration, the output impedance of the FET in the off state can be made extremely high, so that the influence of the FET in the off state can be suppressed on the output side, which has a large effect on efficiency. Moreover, since no current flows through the gate of the FET, switching of the gate voltage is possible with a simple circuit configuration, and a decrease in power efficiency due to the power supply circuit can be avoided.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is an equivalent circuit diagram showing one embodiment of the present invention.

In the figure, FET II with a large saturated output and FET 12 with a small saturated output are connected in parallel via capacitors 13 and 13t that connect their gate terminals and drain terminals. The input signal is input to the input matching circuit 14
is input to the gate terminal of each FET11.12 via
The output of each FET II, 12 is taken out via an output matching circuit 15.

FET II (7) gate voltage v1.1 is applied via resistor 161, and drain voltage V, . applied via. Also, the gate voltage V9 of FETI2
, 2 is resistor 16! is applied via the drain voltage V
441 is applied through the inductor I7□ which has a large actance with respect to the high frequency output.

In this way, the bias supply circuits for each FET II and 12 are separate systems, and the individual voltages can be set independently.

Here, an equivalent circuit at high output and an equivalent circuit at low output in this embodiment are shown in FIGS. 2 and 3, respectively.

In FIG. 2, the FETI 2, which is turned off by controlling the gate voltage, is equivalently replaced by a capacitor 21 and a resistor 22 on the input side and a resistor 23 on the output side. In addition, in Fig. 3, the FETI that is turned off
1 is equivalently replaced with a capacitor 31 and a resistor 32 on the input side, and a resistor 33 on the output side.

On the input side, when looking at the FET from the input matching circuit 14, changes in impedance due to different combinations of ON and OFF states of FET II and 12 are relatively small. Therefore, the input matching circuit 14 can be designed within an allowable characteristic range regardless of whether the FET is on or off.

On the other hand, on the output side, the output impedance (resistor 23, 33) of the OFF FET has a much higher value than the impedance when looking at the output matching circuit 15 including the load from the FET side. Generally, the former is several ohms, while the latter is several tens of ohms. Therefore, there is almost no influence due to the FET in the off state being connected to the output side, and the output matching circuit 15 can be designed without considering the FET in the off state.

By the way, in a high-frequency, high-output amplifier, priority is given to efficiency at high output, so the output matching circuit 15 is designed in a state at high output with FET II on and FET 12 off. Therefore, in a low output state where FET II is off and FET I2 is on, the impedance seen from the drain terminal of the FET 12 to the output matching circuit 15 has a value considerably lower than the optimum impedance. This is because the FET's output impedance is inversely proportional to the gate width.
This is because the output impedance of FET 12, which has a smaller gate width than FET II, is relatively high.

However, in normal cases, when the impedance of the output matching circuit 15 seen from the drain terminal of the FET deviates to a lower value than the optimum value, the efficiency tends to be extremely reduced. Therefore, the present invention takes the following measures.

■ Reduce the capacitance of capacitor 13□ on the output side and
The impedance of the output matching circuit 15 viewed from the drain terminal of T12 is increased.

(2) When the drain voltage is lowered, the optimal impedance when looking at the output matching circuit 15 from the drain terminal moves to a lower direction, so the drain voltage V of the FET 12. 2
is the drain voltage V of FETII. Set lower than 1.

Through such operations, efficiency at low output can be maximized.

〔Effect of the invention〕

As described above, the present invention uses a FET with a large saturated output and a FET with a small saturated output, and sets the voltage applied to the gate of one FET so that the drain current of one FET becomes almost zero when a signal is input. By doing so, the other F
It is possible to switch the output to operate only ET.

Therefore, the present invention has a large F of saturation output at high output.
Since the ET can be used near its saturated output, and the FET with a small saturated output can be used near its saturated output when the output is low, high efficiency can be achieved at both high and low outputs.

Note that there is no need to switch the drain voltage, and switching the gate voltage can be done with a simple circuit configuration, so it is possible to avoid a decrease in power efficiency due to the power supply circuit. Furthermore, since a switch circuit is not required, there is no accompanying increase in power consumption or decrease in gain due to insertion loss, and the obtained efficiency can be maximized.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram at high output in the embodiment. FIG. 3 is an equivalent circuit diagram at low output in the embodiment. FIG. 4 is an equivalent circuit diagram of a conventional high frequency high output amplifier. FIG. 5 is a diagram showing output power and drain efficiency characteristics with respect to input power in a class B amplifier and a class F amplifier. FIG. 6 is a diagram showing a conventional configuration for maintaining high efficiency at low output. 11... FET with large saturated output, 12... FET with small saturated output, 13... Capacitor, 14...
Input matching circuit, 15... Output matching circuit, 16... Resistor, 17... Inductor, 21... Capacitor equivalent to FET 12, 22.23... Resistor equivalent to FET 12, 31.・Capacitor equivalent to FETII,
32.33...Resistor equivalent to FETII, 41...
・FET, 43.45... Matching circuit, 47.49...
・Bias supply circuit. Figure 2 Figure Input power (dam) Figure 3 Figure

Claims (1)

[Claims] (1) A FET with a large saturated output, a FET with a small saturated output whose bias supply circuit is separate from this FET, and a capacitor that connects the gate terminals and drain terminals of each FET, and either A high-frequency, high-output amplifier characterized in that the voltage applied to the gate of one FET is set to a value at which the peak voltage of an input signal does not exceed its pinch-off voltage, and the FET to be activated is selected.