JPH03280267A - Interleaving address generating circuit for digital audio tape recorder - Google Patents

Abstract

PURPOSE:To reduce the load of a decoder and to simplify the whole constitution of a decoder or the like by providing two counter systems and changing the initial values of respective counters. CONSTITUTION:A clock signal 64FS with a 64FS period formed based upon a reference clock is inputted to a 7-bit binary counter 60 (the FS is a clock corresponding to sampling frequency 32K). The counter 60 executes the binary counting of the 64FS and outputs an FS signal and a 0.5FS signal. The signal from the counter 60 is supplied to a pulse generating decoder 62 and E and O pulse signals obtained from the decoder 62 are respectively inputted to an E counter 64 and an O counter 66. A selector 70 determines the reset timing of the counters 64, 66 in accordance with a mode selected by a selector 70 and controls the resetting of the counters 64, 66 through a counting circuit 72. The outputs of respective digits of the counters 64, 66 are supplied to a decoder 80. The decoder 80 outputs the writing/reading addresses of a RAM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to interleaving of a digital audio tape recorder (hereinafter referred to as rR-DAT) that uses a rotary head to record audio signals as digital data on a magnetic tape. It relates to an address generation circuit.

[Background Art] With the advancement of digital technology, digital recording is being adopted for recording various signals, and devices that use digital recording such as compact discs are becoming popular for recording audio signals as well. .

Among devices that utilize such digital recording of audio, digital audio tape recorders (DAT), which are capable of not only reproducing audio signals but also recording audio signals, are attracting attention.

Because this DAT records audio signals as digital data on magnetic tape, it eliminates problems such as wow and flutter, hiss noise, and modulation noise associated with analog recording, and has a wide dynamic range and flat frequency over a wide frequency band. It has the characteristic of being able to achieve high quality sound recording and playback.

Here, there are two types of DAT: a method that uses a rotary head and a method that uses a fixed head. In particular, the standardization of the method that uses a rotary head (R-DAT) has been finalized, and commercialization is expected. It's progressing.

In the R-DAT, as shown in FIG. 7, signals are stored in each track that is tilted a little more than 6 inches with respect to the direction of travel of the magnetic tape.

Then, for each track, digital audio data (PC
In addition to the area for recording M), an area for recording subcodes consisting of various information necessary for reproduction, an area for recording ATF signals for tracking, etc. are provided separately.

In addition, the rotary head has magnetic tape tracks,
Two magnetic heads are provided for tracing, respectively, so that two tracks are traced in one rotation of the rotary head. The magnetic tape is designed to come into contact with the rotary head rotating at high speed only within a 90'' range.

As described above, the recording and reproduction of audio data on a magnetic tape by a magnetic head is intermittent, and in order to input and output continuous audio, time axis conversion of the data must be performed.

Furthermore, in order to minimize the effects of random errors and burst errors that occur during data recording on magnetic tape, DAT employs an interleave format in which data is recorded in a distributed manner.

Therefore, in order to perform time axis conversion and recording/reproduction using an interleave format, a RAM is required to store a certain amount of data.

In other words, when recording data, after performing time axis conversion, two tracks of data are written to RAM in an interleaved format, and while the next two tracks of data are being written, the previous two tracks are being written. data is read and recorded on magnetic tape. Also, during playback, the data read from the magnetic tape is written to RAM once, and then
After deinterleaving the data read from M, time axis conversion is performed.

In addition, the conversion of analog audio signals and digital data is performed by A.
/D converter and D/A converter, but DA
In order to enable long-term recording and to directly exchange digital signals with other audio equipment, the A/D converter uses 48 kHz and 44 kHz as frequencies for sampling digital data from audio signals.
．． Three sampling frequencies are available: 1kHz and 32kHz.

As a long-time playback mode, there is a 32kL mode, which has a sampling frequency of 32 and enables recording and playback for twice the normal time.

In this 32kL mode, audio data supplied from both left and right channels are A/D converted into 16-bit digital data at a sampling frequency of 32kHz, and this 16-bit digital data is logarithmically compressed to 12 bits.

Then, this is divided into 8-bit and 4-bit data, respectively, and three 8-bit data are generated from two 8-bit data and two 4-bit data from the obtained left and right channels, and this is converted into a predetermined interleave format. to write to RAM.

In this way, when the amount of data is compressed to 3/4, the data obtained in twice the time is 2X3/4, which is 1.5 times the normal data. On the other hand, since the RAM is prepared in correspondence with the data obtained by the sub-ring frequency of 48kHz, 3
It is possible to store 1.5 times as much data as the data obtained by the sampling frequency of mode 2.

Therefore, all the data obtained in twice the time are
It can be stored in AM format, and the magnetic tape can be used for twice as long, making it possible to record and play for twice as long.

Here, the interleave format in this 32kL mode is as shown in Figure 8, in which three data are written in the area for the A head (an area corresponding to one track traced by one magnetic head). After that, data is written in the B head area (an area corresponding to one track traced by other magnetic heads) in the same order. One area has 128 blocks (1 block 32 symbols, 1 symbol 8 bits), and the 24 blocks in the center are areas for error correction codes.

Therefore, the symbol address in the interleaved format (0 to 4095 for A head, 409 for B head)
6-8191) is rO,2゜64'', r6528,6
It will be like 5B0,6592J.

In order to generate interleaved addresses in such a 32kL mode, the RAM count (
0 to 3638B) was provided, and the output of this counter was decoded by a dedicated decoder so that it became an interleaved address.

[Problems to be Solved by the Invention] However, the generation of interleaved addresses in such a 32kL mode differs in timing from the generation of ink-leave addresses in normal times, and the interleaving method is completely different. There was a problem in that the circuit for generation was extremely complicated.

That is, in the case of normal (normal mode) interleaving, regardless of the sampling frequency, 16-bit data obtained by one sampling is divided into two parts and written into the RAM. However, in the case of 32 kL, three 8-bit data are created from two 16-bit data as described above, and this is recorded in the RAM. Therefore, A/
The sampling period in the D converter and the timing of writing to the RAM are different.

Furthermore, since the interleaving method is completely different from that in the normal mode, it is necessary to provide a completely separate decoder, resulting in the problem that the decoder is extremely complex and large in size.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an interleave address generation circuit for a digital audio tape recorder that can generate a complex 32kL mode interleave address with a simple circuit. With the goal.

[Means for Solving the Problems] The present invention provides two clock pulses that are alternately generated from a clock pulse synchronized with the sampling period when A/D converting an audio signal.
means for generating a series of pulse signals; two counters each receiving the two series of pulse signals and having different initial values at the start of counting; and a means for generating two series of outputs from the two counters. and a decoder that alternately selects and decodes the address signal in synchronization with the pulse generation period of the pulse signal.

[Operations] The interleave address generation circuit according to the present invention has the above-mentioned configuration, and includes two series of counters,
Input pulses alternately to this and count. 32kL
The RAM symbol address in mode interleaving is relatively simple if divided into three parts, and two
Since two counters are provided and the initial value of each counter is changed, the load on the decoder is lightened, and the overall configuration of the decoder and the like can be simplified.

[Example] Hereinafter, an example of the present invention will be described based on the drawings.

Explanation of the overall structure> FIG. 1 is a block diagram of the overall configuration of the embodiment.

A control signal (mode data) is sent from the CPU10 via the CIO data bus to the mode control circuit 12 that defines the operation of the internal circuit, and the output signal from this mode control circuit sets modes such as playback, recording, and high-speed search. be done.

During normal playback mode, the drum rotation speed is 200O.
rpm, and the digital data recorded on the magnetic tape is read by two magnetic heads A and B. Then, from the synchronization bit in this read data, the PLL
A synchronous clock is created in circuitry (not shown). In this way, the PCM data read from the track according to the synchronization clock is input to the demodulation circuit 14.

The demodulation circuit 14 detects the synchronization signal 5YNC in the input PCM data block, resets the symbol counter 16, and performs 10-8 conversion on the input PCM data. The symbol counter 16 counts the synchronization clock and receives the ID code data W1 and block address data W input after the synchronization signal 5YNC of the PCM data block.
2. A total of 35 symbols of parity PSPCM data (10
One symbol after -8 conversion is counted as 8 bits).

When the count value of the symbol counter 16 is "2", that is, the input of the block address data W2 of the data block is detected, it indicates the block address in the 8-bit block address data W2 output from the demodulation circuit 14. 7
The bits are set in bits A5-A11 of address counter 18.

Here, the lower 5 bits of the address counter 18 AoNA
4 is a counter output for counting 32 symbols of PCM data, while the upper two bits A1-A13 are bits for outputting a switching signal for magnetic heads A and B and a signal divided by half thereof. Therefore, when the first symbol of PCM data is input, the RAM 20 at 128 is accessed by the output of the address counter 18, and the PCM data symbol output from the demodulation circuit 14 is stored in the RAM 20.
will be written to.

While the read data from the magnetic heads A and B is being written into the half 64k of the RAM 20, the interleave address control circuit 22 accesses the remaining half 64k based on the sampling frequency. The PCM data stored at the address specified by the output data converter 24 is sent to the output data conversion circuit 24, converted from 8 bits to 16 bits, and output to the D/A converter for reproduction.

Note that during normal playback, when a predetermined amount of PCM data is stored in the RAM 20, the ECC address control circuit 26
accesses the RAM 20 and sends PCM data to the ECC circuit 28. The ECC circuit 28 checks the 01 code from the input data and writes the corrected data into the RAM 20 again. Also, one track, that is, A,
When all the data read by either magnetic head B is stored in the RAM 20, the FCC address circuit 26
The ECC circuit 28 checks the C2 code and corrects the data.

During recording, a control signal instructing the recording mode and sampling frequency is sent from the CPU 10 to the mode control circuit 12, and the internal circuit is set to the recording mode.

Then, according to the specified sampling frequency, the A/D
The converted data is input to the input data conversion circuit 30, which separates the 16-bit data into 8-bit data, and the symbols converted into 8-bit data are interleaved and written into 64k of the RAM 20 by the interleave address control circuit 22. Furthermore, E from the written symbol
A C1 code and a C2 code are created by the CC circuit 28,
The data is stored in a predetermined area of the RAM 20 again.

On the other hand, the CPU 10 outputs the SUB to be recorded together with the audio data.
The code data is output to the SUB code register 32.

This SUB code register 32 creates pack data including parity based on the stored SUB code data, and the created back data is sent to the pack address control circuit 3.
4, the writing to the magnetic head is completed in RAM20.
The C1 and C2 codes are written in the area 64 of . Then, a C1 code is created by the ECC circuit 28 from the written back data and stored in the RAM 20 again.

(7) In order to read the data written in the RAM 20 and output it to the magnetic heads A and B, first the symbol counter 36, block counter 38, and frame counter 36, which count the write clock FCH synchronized with the rotation of the rotating drum, are used. The address of the RAM 20 is designated by the counter 4o.

Therefore, the data stored at the designated address is inputted to the modulation circuit 44 via the switching circuit 42, converted into 8-10 data, and supplied to the magnetic heads A and B.

Note that switching between writing and reading from the RAM 20 in response to mode changes such as playback mode and recording mode is performed by an access control signal from the RAM access control circuit 50.

Interleave address generation circuit> Here, in the present invention, the interleave address generation circuit 2
2, a configuration that can easily support the 32kL mode is adopted. Therefore, the specific structure and operation of this interleave address generation circuit 22 are shown in FIGS. 1 and 3.
This will be explained based on FIGS.

Creation of two series of pulses In FIG. 1, a clock signal 64FS with a 64FS period created based on a reference clock obtained by an oscillator (not shown) is input to the 7-bit binary counter 60 (here, , FS is sampling frequency 32k
). As mentioned above, there are three types of sampling frequencies: 32 and 44.1.48, and the clocks for 32 and 48 are obtained by dividing the reference clock from the same oscillator, and are 44° 1k. The clock for the oscillator is created based on a reference clock from another oscillator. In addition, these clocks can be switched using the CP
This is done by a command from Ul0.

The 7-bit binary counter 60 performs a binary count of the 64 FS and outputs an FS signal (divided by 1/64) and a 0.5 FS signal (divided by 1/128).

Further, the signals of each stage from this 7-bit binary counter 60 are supplied to a pulse generation decoder 62. The pulse generation decoder 62 generates pulse signals for counting in normal times and in the 32kL mode from the output of the input 7-bit binary counter 30. For this purpose, the pulse generation decoder 62 is composed of AND gates and OR gates shown in FIG. 3, and outputs two different series of pulse signals, that is, an E pulse signal and an O pulse signal.

Here, the output from each stage of the 7-bit binary counter 60 is Q. -Q6, the outputs of Q1 to Q6 become signals of 16FS to 0.5FS, respectively, as shown in FIG. Then, a prescribed process is applied to this,
First, the occurrence of signals in the 32kL mode will be explained.

7. The output from the AND gate 62a to which the outputs Ql to Q3 of the pit binary counter 60 are input is as shown in FIG.
The pulse signal has a 4FS cycle as shown in a).

Then, the signal from this AND gate 62a and Q4~
Since Q6 is input to the Nantes gate 62b, the signal shown in FIG. 4(b) is output from the Nantes gate 62b. Furthermore, since the signal from the Nantes gate 62a and the input signal 5.06 are input to the Nantes gate 62c, the signal shown in FIG. 4(C) is obtained.

Since these signals are input to the NOR gate 62d, the signal shown in FIG. 4(d) is output from the NOR gate 62d. The E-pulse signal is obtained by inverting the signal shown in FIG. 4(d).

On the other hand, the output of the AND gate 62a in FIG. 4(a), Q4, Q5, and 6 are input to the Nantes gate 62e, so the signal in FIG. 4(e) is output from the Nantes gate 62e. . In addition, the Nantes gate 62f has the signal of the Nantes gate 62a and 06, mouth. is input, so the fourth
The signal shown in Figure (f) is obtained. Since these signals are input to the NOR gate 62g, this NOR gate 62g
The signal shown in FIG. 4(g) is output from the circuit. The signal shown in FIG. 4(g) becomes the O-pulse signal.

In this way, in the 32 kL mode, the E pulse signal and O pulse signal as shown in FIG. 4 are output from the pulse generation decoder 62.

On the other hand, in cases other than 32kL mode, the E pulse signal,
The pulse indicated by the broken line in FIG. 4 is added as the 0 pulse signal, and four pulses each with a 4FS period are output alternately as E and O pulse signals.

For this purpose, Nantes gates 62h and 62i are provided,
This output is input to NOR gates 62d and 62g, respectively. Also, this Noah Gate 62h,
62i has M32kL which becomes rHJ when in 32kL mode.
A signal is input via inverter 62j. For this reason,
The NOR gates 62h and 62i output signals only when in a mode other than 32kL mode.

In addition to the signal from the inverter 62j, the NOR gate 62h receives the signal 04. from the AND gate 62a. Q
5.06 is entered. Therefore, the pulse indicated by the broken line in FIG. 4(d) is output when the mode is other than 32kL mode. In addition to the signal from the inverter 62j, the NOR gate 62i also receives a signal from the AND gate 62a. , Q5. Q6 is input. Therefore, the pulse shown by the broken line in FIG. 4(g) is output when the mode is other than 32kL mode. In this way, 32
An E,0 pulse signal with one more pulse than in the kL mode is obtained.

Generation of symbol address The E and O pulse signals obtained in the pulse generation decoder 62 in this way are sent to the E counter 64 and the O counter 6.
6 respectively.

The E counter 64 is a binary/quaternary counter 64a1 that can be switched to a binary counter or a quaternary counter and outputs EQo.
Two hexadecimal counters 64b and 64c are connected to this and output EQ2 to EQ6 and EQ7 to EQ1□, respectively, and two flip-flops 64d output the upper digits EQ12'EQ13.

64e. And the hexadecimal counter 64b
, 64c is roooooo (0)J~rl10
01 (25) Count sequentially up to J.

On the other hand, the 0 counter 64 is a binary/quaternary counter 6 that can be switched to a binary counter or a quaternary counter and outputs oQo.
4a1 connected to this oQ2~OQ6, OQ7~OQ1
Two 26-decimal counters 64b, 6 that output □, respectively.
The 26-decimal counter 66b in the negative stage is set to roollo (8) J as an initial value, and counts from this value to rllllll (31) J, and
The 26-decimal counter 66b of the row is roooooo (0)J
~rl1001 (25) Count J.

The outputs of the E counter 64c and the 0 counter 66c are supplied to a selector 70, and the selector 70 is supplied with mode signals M32, MB2, M44.1, etc. Since the number of PCM errors varies depending on the mode, the selector 70 determines the reset timing of the E counter 64.0 counter 66 according to the selected mode. And count value control circuit 7
2, controls the reset of the count values of these counters 64 and 66.

The output of each digit of the E counter 64.0 counter 66 is then supplied to a decoder 80. This decoder 80 has a configuration as shown in FIG.
Outputs the write/read address of M20.

That is, A of the decoder 80. -Alo's output line has
E counter 64, O counter 66 Q7, QO"8"9
``10''11''2''3' Q4, Q5, and QB are connected in this order via selection games 72a to 72k.

The selection gates 72 a to 72 k have 0.5
FS signal and its inverted signal are supplied, 0.5FS
is rHJ, the output of the 0 counter 66 is selected, and 0.
When 5FS is rLJ, the output of E counter 64 is selected.

Also, 0.5FS is connected as is to AI□, and A1
2 is connected to a selection gate 721.

This selection gate 721 sets the output of the selection gate 72m to 0.
It is inverted according to 5FS, and the selection gate 72m
is EQl. and FS is selected. In the case of 32kL mode, the selection gate 72m selects EQr□, the selection gate 721 selects 0, and 51'S selects rHJ.
When EQl2 is inverted and output, 0.5FS becomes “L”.
”, EQl2 is output as is.

Further, a selection gate 72m is connected to A13, and this selection gate 72m is connected to the 32kL mode 521EQ1.
Select 3, and select EQl2 at other times.

The operation of the decoder 80 having such a configuration will be explained based on FIG. 6.

In the case of 32kL mode, the E pulse train is counted by the E counter 64 starting from "L" of 0.5FS.

Since the initial value of all E counters 64 is 0, all outputs of the 80"" A13 are 0. Then, when one E series pulse enters, the output of the E count 64a becomes rHJ
Therefore, EQ becomes rHJ, and therefore A3 becomes rHJ.

Therefore, the output of the decoder 80 is roooooooooo
oolo(2)". Next, when the E pulse is input, the output of the E counter 64a becomes "L", and the first digit EQ2 output of the E counter 64b becomes "H". Therefore, A6 of the decoder 70 becomes rHJ, and the output is rOOooo
ooloooooooo (64)J. In this example, as shown in Fig. 4, only 2 pulses are input at first, so it is possible to output "2" and "64" from the initial value 0, but after that, 3 pulses are input. Outputs three values.

Therefore, by the outputs of Eo, El, and E2 in Fig. 6, “■
, ■, ■", symbol addresses for the three data shown in FIG. 8 are output.

Since this is done for the IFS, 32-bit data can be written into the RAM 20 as 24-bit (3 symbols) data.

Next, when 0.5FS rises, selection circuits 72a to 72
1 is switched. And AI, is rH of 0.5FS
J is output as is, and A12 is EQl. rLJ is inverted and rHJ is output. Further, 80""A10 selectively outputs the output of the O counter 66. On the other hand, 0 counter 6
The hexadecimal counter 66b of 6 is roollo as an initial value.
It is set to J. Therefore, the output of the 0 counter 66 is OQ3. OQ4 is rHJ and the rest are rLJ.

Therefore, the output of the decoder 70 is A7. A8 is rHJ
Tona, rollooollooooooo(6528)J
becomes. Note that the 0 pulse signal has three pulses from the first time. Therefore, in order for the initial output to be the above-mentioned value, the actual initial setting value of the 0 counter 66 is preferably a value that becomes roolloJ when one pulse is input.

Then, with the input of the next pulse, AI becomes rHJ and the output becomes r6530J, and with the next pulse, A
1 "L", A6 "H" and the output becomes r6592J.

In this way, O6 of the 0 counter 66 shown in FIG.
According to the 0□, 02 output, "■, ■, ■" shown in Figure 8
can be output.

Here, since 0.5FS is switched, the E pulse is input to the E counter 64, and the outputs of A11'A12 return to rLJ. Therefore, the binary/quaternary counter 64a becomes rHJ, EQo, EQ2 or rHJ, and the output becomes "66". Furthermore, in the next pulse, E Q s becomes r
HJ becomes r128J, and in the next pulse, EQ
o, EQ3 becomes rHJ and becomes r130J. In this way, symbol addresses in the 32kL mode can be sequentially output by inputting three pulses.

Then, when the 26-decimal counters 64b and 66b count up to 26, the 26-decimal counter 64c
, 66C with rHJ. Therefore, Q7 is rHJ
Then, the output will shift to the odd numbered symbol address.

Note that the 26-decimal format is used for RAM2 as shown in Figure 8.
This is because blocks 52 to 75 at the center of 0 are areas for error correction codes, and are areas in which PCM data supplied from the A/D converter is not written.

Also, as the count progresses and EQl2 becomes rHJ, A1
2 becomes rHJ. Based on the symbol addresses output so far, addresses for a total of 4096 symbols are output from the left side area of the A head table and the right side area of the B head table of the RAM 20. Since EQ12 becomes rHJ, the timing at which it becomes rHJ is opposite to 0.5FS of A12. Therefore, the output of the decoder 80 is r4096.4098.4160.
The symbol address of the right side area of the A head table and the left side area of the B/SOD table is output. A similar interleave address is also output for this area.

In this manner, when addressing of both the AB and SOD table areas of the RAM 20 is completed, EQ13 becomes rHJ. Therefore, A18 becomes rHJ and the address of the table area is similarly output.

In this way, interleaved addresses in 32kL mode can be generated.

On the other hand, in normal mode, the M32kL signal is rL
J, and the binary/quaternary counters 64a and 66a are 4.
It is a forward counter. In addition, the pulse generation decoder 6
E and O pulse signals consisting of four pulses are output from 2 to IFS.

Then, the selection circuits 72a to 72 have 0. The EQ output and OQ output from the EQ counters 64 and 66 are switched every 5FS. Further, the selection circuit 72m selects FS, and the selection circuit 721 sequentially inverts the FS according to 0.5FS and outputs it.

Therefore, EQo changes from rLj - rHJ - rLJ to rHJ by inputting the E pulse to the binary/quaternary counter 64a. Therefore. The output EQ of this binary/quaternary counter 64a changes in the same way as A1 to which it is connected, and the output is rO,
It becomes 2,0,2J.

On the other hand, as described above, the selection circuit 721 sets the FS to 0.5FS.
Since the A12 signal is sequentially inverted by rLLHH,
HHLLJ will be sequentially repeated. Further, A11 repeats rLLLL and HHHHJ. Therefore, here 2
If we look at only one output, rO, 0,4096,4096
,6144°6144.2048,2048J.

The initial value of the 0 counter 66 is "00" as described above.
110'', the output of the decoder 80 is rO,2,4096,4098,6528°65B0
, 2432, 2434J. In this way, since the symbol address is output using the outputs of the binary/quaternary counters 64a and 66a, the 32kL mode and the comparison counter 6
4.66 finishes outputting all 20 symbol addresses of RAM at half count. Therefore, when EQ12 of the flip-flop tube 64d becomes rHJ, "Hj" from the selection circuit 72n is output to A13, and the front and back of the RAM is switched.

In this way, the symbol address for normal mode can be output.

Note that the output of the decoder 80 is supplied to the address bus ADRBUS via the gate 82 at a predetermined timing.

[Effects of the Invention] According to the present invention, the sampling frequency of R-DAT is 32
Since the same interleave address generation circuit can support normal modes using KHz, 44.1 KHz and 48 KHz and LONG mode using a sampling frequency of 32 KHz, the circuit can be significantly simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the interleave address generation circuit of the present invention, FIG. 2 is an overall configuration diagram of an R-DAT in which the interleave address generation circuit of the present invention is used, and FIG. 3 is a block diagram showing the configuration of the interleave address generation circuit of the present invention. Circuit diagram, Figure 4 shows pulse generation decoder 6
5 is a circuit diagram of the decoder 80, FIG. 6 is a timing chart showing the operation of the decoder 80, FIG. 7 is an explanatory diagram of data storage on a magnetic tape, and FIG. 8 is a circuit diagram of the decoder 80. - It is an explanatory diagram of the interleave format in RAM20 of DAT. 22... Interleave address control circuit 60
... 7-bit binary counter 62 ... Pulse generation decoder 64 ... E counter 66 0 counter 0 decoder

Claims (1)

[Claims] Means for generating two series of pulse signals that are generated alternately from clock pulses synchronized with a sampling period when A/D converting an audio signal; , and at the same time, it selects two counters with different initial values at the start of counting and alternately selects and decodes the outputs from these two counters in synchronization with the pulse generation period of the two series of pulse signals. An interleave address generation circuit for a digital audio tape recorder, comprising: a decoder that generates an address signal using a decoder;