JPH03280413A - Capacitor network structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to stably form a terminal electrode having very small internal by a method wherein the holes, which penetrate the patterns of each internal electrode, are provided on each pattern group, electrode paste is filled in each hole, a sintering operation is conducted, and a terminal electrode is formed. CONSTITUTION:A laminated green sheet, having condenser pattern, is obtained by alternately laminating a green sheet 1 provided with electrode patterns 2, and another green sheet 3 provided with capacitor pattern 4 which are formed by printing. Through-holes 5 are perforated at the position corresponding to each capacitor pattern group, thick film electrode paste is printed, the through- holes 5 are filled up with conductive paste, and a green sheet laminated body having a terminal electrode 6 is formed. A small type laminated capacitor is obtained by sintering the above-mentioned laminated body and cutting it at the prescribed cutting line; or after holes are formed on the green sheets 1 and 3, they are cut at the preset cutting line, the perforated green sheet laminated body is sintered, thick film conductive paste is printed, the through-holes 5 are filled up with conductive paste, and a sintering operation is conducted thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chip capacitor used in a high-density mounting wiring board. In particular, the present invention relates to a chip capacitor network structure for incorporating a plurality of capacitors in one chip to achieve circuit miniaturization and low-cost implementation.

[Prior art and problems to be solved by the invention] Conventional capacitors with built-in multiple capacitors (referred to as capacitor networks) are large and cannot be mounted on a circuit with multiple external lead-out electrodes formed on the same side. If you do,
For ease of use, lead pins were connected to external electrodes, and the entire resin-molded part was inserted into a hole on the circuit and soldered.

In order to miniaturize the circuit and increase the packaging density, it is necessary to miniaturize the capacitor network, but when forming multiple external electrodes on the same side, the spacing between them becomes narrower, and the conventional method of forming external 11L electrodes becomes difficult. , a defect occurs where adjacent electrodes come into contact. Therefore, it has not been possible to manufacture a small capacitor network with a distance between electrodes of about 0.3 cm.

As electronic devices become smaller and thinner, circuit boards become smaller and components are mounted with higher density. Circuit boards with a line width of about 0.3 m have come to be manufactured, and electronic components have also moved to smaller chips. Furthermore, in order to achieve high-density packaging, it is effective to provide multiple functions within one chip, and a capacitor network is one such method. This provides a new method for constructing terminal electrode spacing.

The present invention solves the above-mentioned problems by:
It is an object of the present invention to provide a capacitor network structure and a manufacturing method thereof that can stably mass-produce capacitor network chip components having terminal electrodes with minute intervals, for example, 0.3 m width.

[Means for Solving the Problems] The gist of the present invention is to provide a compact multilayer capacitor in which internal electrodes of a multilayer capacitor are provided in a multilayer dielectric material, and a plurality of electrodes are provided on the side surface of the dielectric material for each internal electrode. This is a capacitor network structure in an electronic component, characterized in that each pattern group has six holes penetrating each internal electrode pattern, and each hole has a terminal electrode filled with electrode paste and fired. Then, each green sheet with each electrode pattern formed thereon is laminated, holes penetrating each electrode pattern group are provided through the created laminate, and the electrode paste is applied to each of the holes before or after firing. This method of manufacturing a capacitor network is characterized in that terminal electrodes are created by filling and firing the dielectric laminate, and then cutting the resulting dielectric laminate having the laminate electrodes along predetermined cutting lines.

[Function] For example, when trying to manufacture a capacitor network with a size of 3.2 x 1.6 To attach a tip terminal electrode, the tip was immersed in electrode paste and baked or electroless plating was used, but in the case of a capacitor network, these methods require protecting the parts where you do not want the electrode attached with resist, etc. There was a need. When downsizing, it becomes increasingly difficult to print such resists on the sides of small chips in terms of precision.

Therefore, as a result of intensive research into a method that is suitable for mass production and that can be easily formed into terminal electrodes, a method was found in which the terminal electrodes can be formed in the subsequent process at the green stage without firing the chips. That is, in the present invention, after the terminal electrodes are configured after lamination,
Baking it to produce a chip with terminal electrodes, or
Alternatively, at the stage of laminating the green sheets, a processing method is used that facilitates the attachment of terminal electrodes in the subsequent process.

To explain in more detail, according to the present invention, after laminating the sheets, holes are accurately punched at the terminal electrode positions using a laser beam or a small punching machine, and then a conductive paste is printed.
The conductive paste is filled into the hole and connected to the internal electrode. Thereafter, the structure having a large number of laminated capacitors is cut into a predetermined size and fired to produce a chip with terminal electrodes.

Alternatively, after drilling, cutting and firing, chips with terminal electrodes are arranged, and the holes are filled with electrode paste by printing, and the terminal electrodes are constructed by firing.

When constructing closely spaced terminal electrodes, before firing,
Since there is no firing shrinkage of about 20 to 30%, there is a margin for accuracy in printing. Since it can be processed before cutting and separating the bulbs into pieces, it has the advantage of being suitable for mass production and of making it easier to obtain positioning accuracy. Even if the hole is deep, it is possible to fill it with electrode paste by printing multiple times.

As for the perforation method, a diameter of about 0.5 cm is sufficient, and a laser or a small-sized perforation machine can be used satisfactorily.

In order to form the terminal electrodes of a small capacitor/sa network, performing these processes is important for mass production.

The materials of the dielectric layer used in the present invention include barium titanate BaTiOs, lead titanate PbTi0. A mixed sintered body containing at least one dielectric compound selected from the group consisting of strontium titanate, 5rTiOs, and strontium titanate is preferred. Furthermore, the insulating ceramic used is a ceramic sintered body containing at least one metal oxide selected from the group consisting of alumina, silica, and magnesia as a main component.

Further, the internal electrode pattern is preferably formed using a thick film conductor paste containing at least one metal selected from the group consisting of gold, silver, copper, platinum, and palladium as a main component.

Next, the multilayer capacitor chip of the present invention will be explained using specific examples, but the present invention is not limited to this explanation.

[Example] Regarding the material, barium titanate Ba was used as a dielectric material.
Ti0. , using palladium Pd as the internal electrode material and a dielectric layer produced by a printing method.
), (2), (3), (4), (5), (6) and (7
An example of creating a multilayer capacitor network having the structure shown in ) will be described below, but the present invention is not limited to the following.

An organic binder is added to B a Ti Os powder to create a dielectric paste, and a green sheet 1 is created as shown in FIG. A green sheet 3 is formed as shown in FIG. 1 (2), another capacitor pattern 4 is printed on it, and these two types of green sheets 1.3 are laminated alternately. , to obtain a laminated green sheet having the capacitor pattern shown in FIG. 1 (3) Next, as shown in FIG. Next, a thick film electrode paste is printed on the thus-perforated green sheet laminate, the through holes 5 are filled with conductive paste, and the green sheet laminate having the terminal electrodes 6 is formed. Form the body and make it 1300
A multilayer capacitor network of the present invention is formed by firing at a temperature of about 100°C for about 2 hours, and then cut along predetermined cutting lines to obtain a small multilayer capacitor as shown in FIG. 1 (6). It will be done.

Alternatively, after perforating the green sheet 1.3, a green sheet laminate having perforated holes shown in FIG. By printing, filling the through holes 5 with conductive paste, and firing, a small multilayer capacitor of the present invention as shown in FIG. 1 (6>) is obtained.

In accordance with the present invention, a multilayer capacitor component manufactured by filling a drilled hole with a conductive paste to form a terminal electrode has improved mechanical strength and hand tear resistance compared to conventional multilayer capacitors. The results were excellent.

[Effects of the Invention] Firstly, the capacitor network chip of the present invention enables stable single production of a capacitor network chip portion for surface mounting having terminal electrodes of 0 and 3 widths, which has conventionally been impossible to manufacture. Now you can.

Second, the method for manufacturing a multilayer capacitor chip has become simpler, automation has become easier, and a surface mount chip capacitor having a structure that can be manufactured in a small size at low cost has been provided. Third, a multilayer capacitor chip has been provided. Technical effects such as providing a chip capacitor with a structure that reduces variation in electrode dimensions without requiring special attention during the chip manufacturing process and allows for an easy-to-manage manufacturing process. .

[Brief explanation of drawings]

Figure 1 (1), (2), (3), (4), (5) and (
6) is a plan view showing the preparation of a network chip manufactured according to the present invention. FIG. 2 is a perspective view showing a conventional multilayer chip capacitor. [Explanation of symbols of main parts] 1.3 , , , , , , Green sheet 2.4. ,,
, , , Internal electrode butter 5 , , , , Punched hole 6 , , , , , , Terminal electrode

Claims (2)

[Claims] 1. In a small electronic component in which internal electrodes of a multilayer capacitor are provided in a multilayer dielectric material, and a plurality of electrodes are provided on the side surface of the dielectric material for each internal electrode, a hole is provided for each pattern group to penetrate through the pattern of each internal electrode. A capacitor network structure comprising terminal electrodes each of which is filled with an electrode paste and fired. 2. Each green sheet with each electrode pattern formed thereon is laminated, holes penetrating each electrode pattern group are provided through the created laminate, and electrode paste is filled into each of the holes before or after firing. 1. A method for manufacturing a capacitor network, which comprises firing to create terminal electrodes, and then cutting the obtained dielectric laminate having the laminate electrodes along predetermined cutting lines.