JPH03280425A - Wiring formation process - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring forming method that provides high heat resistance.

(Summary of the Invention) The present invention forms an insulating film on a semiconductor substrate in two steps, and after forming a first insulating film, a barrier metal layer is formed to cover the bottom of the first insulating film. forming a film that can be selectively grown; forming a second insulating film on the first insulating crotch, in which a second opening is opened on the barrier metal layer or the film that can be selectively grown; By selectively growing a high melting point metal material within the opening, high heat resistance can be obtained and a highly reliable wiring formation method is provided.

[Prior Art] As semiconductor devices become more highly integrated, contact holes are also being miniaturized. Conventionally, the method of forming electrode wiring in such minute contact holes has been to use an aluminum layer by sputtering or CVD, but recently, tungsten (W) etc. have been formed by vapor phase CVD. Technologies for depositing high-melting point metal materials are being actively researched. This technology allows wiring material to be filled into minute contact holes, and is attracting attention as a wiring formation technology suitable for high integration.

In the above-mentioned wiring formation technology using the vapor phase CVD method, a silane reduction method is known as a method for selectively growing a tungsten layer on a diffusion layer made of a silicon layer exposed at the bottom of a contact hole. In this silane reduction method, reaction between the WF6 gas used and the silicon layer is less likely to occur, and the diffusion layer is less likely to be eroded, so it is widely put into practical use.

On the other hand, in the selective growth of the tungsten layer as described above, the reaction between the silicon layer and the tungsten layer does not occur at temperatures below 650° C., so relatively high heat resistance can be ensured. However, for example, glass reflow of a BPSG film used for flattening an insulating film between the eyebrows, and annealing of a polysilicon layer used as a resistive element in SRAM, three-dimensional integrated circuits, etc.

Alternatively, heat treatment for activating the impurity region of a thin film transistor (TPT) formed in a thin polysilicon layer is performed at 90%
It is carried out at a temperature of about 0 to 1000'' C. When such heat treatment is carried out, a reaction occurs between the silicon layer and the tungsten layer, causing problems such as destruction of the PN junction.

As a solution to this problem, a technique is known in which a barrier metal layer is provided within the contact hole in order to prevent the reaction between the silicon layer and the tungsten layer.

For example, as shown in FIG. 3, an insulating film 54 is formed on an n-type impurity region 53 on the surface of a p-type silicon substrate 51 surrounded by an element isolation region 52.

This insulating film 54 has an opening 55 above the impurity region 53, and a barrier metal layer 56 made of a tungsten nitride film is formed at the bottom of the opening 55. This barrier metal layer 56 is obtained, for example, by nitriding a tungsten layer in an NH atmosphere. A tungsten layer 57 is further selectively grown on the barrier metal layer 56.

Furthermore, a technique using a titanium nitride film formed by sputtering or the like as a barrier metal layer has also been proposed.

Alternatively, as described in Japanese Unexamined Patent Publication No. 64-41241, a metal silicide film and a metal nitride film are sequentially laminated on the diffusion layer of the contact portion in the contact hole, and a conductive layer such as a tungsten layer is formed on the metal nitride layer. Techniques for selectively growing materials are known.

Problems to be Solved by Invention J] By the way, in the above-mentioned furan reduction method, in order to improve the selectivity with respect to the underlying layer consisting of a silicon layer or the like,
WF6 gas and SiH are raw material gases.

The gas flow rate ratio is adjusted so as to be rate-determining.

Therefore, the silicon layer undergoes a reduction reaction and the underlying layer is eroded, resulting in junction leakage.

In addition, in this silane reduction method, if the underlying layer is different, such as a tungsten layer, for example, by an n-type impurity region, a p-type impurity region, and a tungsten silicide layer, the amount of tungsten layer deposited may also be reduced by the n-type impurity region. Area>p”
The order differs depending on the type impurity region>tungsten silicide layer.

On the other hand, in the method of forming a tungsten nitride film in an NHs atmosphere as shown in FIG. 3, the tungsten layer is difficult to nitride, so that only a barrier metal layer 56 with a film thickness of about 1000 layers at most can be obtained. Furthermore, in the obtained tungsten nitride film, the Noricon substrate 51 and the tungsten layer 57 react in a tunnel-like manner and become silicided.

Therefore, sufficient heat resistance cannot be ensured.

Furthermore, with the conventional method of using a titanium nitride film as a barrier metal layer, it is extremely difficult to form a titanium nitride film with a sufficient thickness at the bottom of a minute contact hole, and there are problems with the titanium nitride film. Since tungsten has low selectivity, it is not suitable for embedding a tungsten layer by selective growth in contact holes.

Therefore, the present invention has been proposed in view of the conventional situation, and an object of the present invention is to provide a wiring forming method that provides high heat resistance and excellent reliability.

[Means to solve the problem]

The wiring forming method of the present invention has been proposed to achieve the above-mentioned object.

That is, the present invention forms a thin first insulating film having a first opening on a semiconductor substrate, and a film that can be selectively grown to cover the semiconductor substrate exposed at the bottom of the first opening. forming a second insulating film having a second opening where the film capable of selective growth faces at the bottom; and selectively growing a high melting point metal material within the second opening. .

Further, in another invention of the present application, a barrier metal layer is formed at the bottom of the first opening. As this barrier metal layer, for example, a titanium nitride film, a titanium tungsten film, a tungsten nitride film, a zirconium nitride film, etc. can be used. A film that can be selectively grown is formed on this barrier metal layer by a CVD method or the like. This film that can be selectively grown is
For example, a tungsten silicide film or the like can be used.

[Effect]

In the present invention, a first semiconductor substrate having a first opening on a semiconductor substrate is provided.
An insulating film is formed, and a film that can be selectively grown is formed to cover the semiconductor substrate exposed at the bottom of the first opening. Since the first insulating film is a thin film, the aspect ratio of the first opening is small. Therefore, a film that can be selectively grown can be reliably formed at the bottom of the first opening.

A second insulating film having a desired thickness is formed on the first insulating film including the film that can be selectively grown as described above. A second opening is formed in the second insulating film above the first opening, and the film capable of selective growth is exposed at the bottom of the second opening. Therefore, since the high melting point metal material is selectively grown on the exposed film that can be selectively grown, good selectivity can be ensured regardless of the underlying layer below the high melting point metal material. Therefore, it is possible to reliably fill the second opening with the high melting point metal material by selective growth, so that good electrode wiring can be formed.

In addition, since the second opening is opened so that the pre-formed film capable of selective growth faces at the bottom, even if the aspect ratio of the second opening is high, the bottom of the second opening faces A film that can be grown selectively can be formed.

Furthermore, in the present invention, a barrier metal layer is formed at the bottom of the first opening, and a film that can be selectively grown is formed on the barrier metal layer, so that even if heat treatment is performed at a high temperature, the first opening can be maintained. There is no area in which the high melting point metal material selectively grown on the selectively grown film can react with the semiconductor substrate exposed at the bottom of the part.

Therefore, electrode wiring having sufficient heat resistance can be obtained.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Example In this example, the eyebrow insulating film is formed in two steps, and after forming the first interlayer insulating film having the first opening,
A tungsten silicide film is formed as a film that can be selectively grown at the bottom of the opening, and a tungsten layer is selectively grown on the tungsten silicide film exposed in the second opening formed in the second glabellar insulating film. This is an example.

First, as shown in FIG. 1(a), a gate electrode 3 is formed on a p-type silicon substrate 1 with a gate oxide film 2 interposed therebetween. After patterning the gate oxide film 2 and the gate electrode 3, ions are implanted into the surface of the Noricon substrate 10 using the gate electrode 3 as a mask to form an n-type impurity region 4.

After forming a silicon oxide film or the like on the entire surface including the impurity region 4, etching back is performed. As a result, the silicon oxide film remains on the side walls of the gate electrode 3, and a side cool film 5 is formed. Ion implantation is performed using the sidewall film 5 and the gate electrode 13 as a mask, and an n'' type impurity region 6 is formed on the surface of the silicon substrate 1 by the sidewall film 5 and the self-alignment line.

The S transistor has an LDD structure, and electric field concentration at the source and drain can be suppressed.

Next, a first glabellar insulating film 7 made of a silicon oxide film is formed on the entire surface by a CVD method or the like. The first interlayer insulating film 7 has a thickness of about 1,000 layers. A photoresist layer is coated on this first interlayer insulating film 7, and after exposing and developing the photoresist layer in accordance with the opening button of the contact hole, etching is performed using this photoresist layer, as shown in FIG. As shown in (b), a first opening 8 is formed in the first glabellar insulating film 7. First interlayer insulating film 7
Since it is made into a thin film, the aspect ratio of the first opening 8 becomes low. Note that the opening width of the first opening 8 is desirably designed to be slightly larger in order to absorb mask alignment misalignment.

Subsequently, as shown in FIG. 1(c), tungsten silicide M1, which is a film that can be selectively grown by CVD or the like, is formed over the entire surface of the impurity region 6 exposed in the first opening 8.
form 0. Here, in this example, the temperature is set to 360°.
C, SiH, gas flow rate 100O5CC gate, WFb
Gas flow rate: IO5CCMHe gas flow rate: 3603CCM
Then, CVD is performed to form a tungsten silicide film 10 having a thickness of about 1000 nm. First opening 8
Since the aspect ratio of the tungsten silicide film 10 is low, the tungsten silicide film 10 can be reliably deposited even on the exposed impurity region 6 mentioned above.

After coating a photoresist layer 11 on this tungsten silicide film 10, this photoresist layer 11 is
The pattern is exposed and developed so as to remain only on the opening 8 of. Using this photoresist layer 11, the tungsten silicide film 10 is etched.

By the above-mentioned etching, as shown in FIG. 1(d),
Tungsten silicide film 10 remains covering impurity region 6 exposed at the bottom of first opening 8 . The end of this tungsten silicide film 10 exists near the first opening 8 on the first glabellar insulating film 7. Then, a second glabellar insulating film 12 made of a silicon oxide film or the like is deposited on the entire surface including the tungsten silicide film 10. The thickness of this second interlayer insulating film 12 is, for example, about 4000.
be done. This second glabellar insulating film 12 is patterned to have an opening above the first opening 8 . This results in
The second glabellar insulating film 12 above the first opening 8 is opened to form a second opening 13, and the tungsten silicide film 10 is exposed at the bottom of the second opening 13. In this way, after forming the tungsten silicide film 10 in advance, a second film is formed on the tungsten silicide film 10.
Therefore, even if the aspect ratio of the second opening 13 is high, a good tungsten silicide film 1o can be obtained at the bottom of the second opening 13.

Finally, as shown in FIG. 1(e), the second opening 13
A tungsten layer 14 is selectively grown therein.

At this time, as a pretreatment, for example, after performing light etching with g-acid and water, under reduced pressure of 0.05 Torr,
RF power 88W, NF, gas flow rate 1105CC, H
Etching is performed with a ffiff standard amount of 705 CCM.

Then, the pressure was set to 0.2 Torr, and the temperature was set to 260°.
Keep SiH at C, gas flow rate 75CCM, WFa gas flow rate 10SCCM, Hz gas flow rate l O00
A tungsten layer 14 is selectively grown as 5CCM.

This tungsten it 1.4 is connected to impurity region 6 via tungsten silicide film 10. Since the tungsten layer 14 is formed on the tungsten silicide film 10, good selectivity can be ensured. Therefore, the tungsten layer 14 can be reliably buried in the second opening 13 by selective growth without being affected by the underlying layer underlying the tungsten layer 14. Thereby, electrode wiring with excellent reliability can be formed even within the minute second opening 13. In this example, the base layer is the silicon layer which is the impurity region 6, but other materials such as an aluminum layer, which are difficult to form a tungsten layer by selective growth, may be used as the base layer. The present invention can also be applied to such cases.

Second Example In this example, the glabella insulating film is formed in two steps, and after forming the first glabella insulating film having the first opening,
In this example, a titanium nitride film and a tungsten silicide film are laminated at the bottom of the opening, and a second glabellar insulating film is further formed.

First, as shown in FIG. 2(a), a gate electrode 23 is formed in a predetermined pattern on a p-type silicon substrate 21 with a gate oxide film 22 interposed therebetween. Using this gate electrode 23 as a mask, ions are implanted into the surface of the silicon substrate 21 to form an n-type impurity region 24. After forming a silicon oxide film etc. on the entire surface including the top of this impurity region 24,
Etch hacking is performed to leave the silicon oxide film on the side walls of the gate electrode 23. This silicon oxide film functions as a sidewall film 25. An n-type impurity region 26 is formed on the surface of the silicon substrate 21 using the sidewall film 25 and the self-alignment line.

In an nMOS transistor having such an LDD structure, electric field concentration at the source and drain can be suppressed.

Next, a film thickness of about 1000% is applied to the entire surface by CVD method etc.
A first interlayer insulating film 27 made of a thin silicon oxide film is formed. A photoresist layer is applied on the first glabellar insulating film 27. This photoresist layer is exposed and developed into a pattern with openings above the impurity region 24. Etching is performed using this photoresist layer to form a first opening 28 in the first interlayer insulating film 27, as shown in FIG. 2(b). Since this first interlayer insulating film 27 is a thin film, the aspect ratio of the first opening 28 is low. Note that the opening width of the first opening 28 is desirably designed to be slightly larger in order to absorb mask alignment misalignment.

Next, as shown in FIG. 2(c), the first opening 28
Titanium nitride 11129 is formed on the entire surface by sputtering or the like, covering the impurity region 26 exposed inside. This titanium nitride film 29 functions as a barrier metal layer, and its film thickness is reduced by about 1000 times.

A tungsten silicide film 30 is laminated on this titanium nitride film 29 by CVD or the like. Since the aspect ratio of the first opening 28 is low, titanium nitride 829 and tungsten silicide (Wi) 130 can be reliably deposited even on the impurity region 26 as described above. This tungsten silicide film 30 is a tungsten layer 34 which will be described later.
formed to improve selectivity. Here, in this example, the temperature is 360°C, and the 5iHn gas flow rate is 1100OSCC, WF! Gas flow rate is 10SCCM,
CvD was performed with a He gas flow rate of 3603 CCM,
Tungsten silicide film 3 with a film thickness of about 500 mm
form 0.

After coating a photoresist layer 31 on this tungsten silicide film 30, this photoresist layer 31 is
The pattern is exposed and developed to remain only on the opening 2B. Using this photoresist layer 31, etching is performed under conditions such that the etching rates of the tungsten silicide film 30 and the titanium nitride film 29 are approximately equal.

By the above-mentioned etching, as shown in FIG. 2(d),
The titanium nitride film 29 and the tungsten silicide 30 remain covering the impurity region 26 at the bottom of the first opening 28. The ends of the titanium nitride film 29 and the tungsten silicide WJ, 30 are located near the first opening 28 on the first interlayer insulation M21. Then, a second interlayer insulating film 32 made of a silicon oxide film or the like is deposited over the entire surface including the top of the tungsten silicide film 30. The thickness of this second interlayer insulating film 32 is set to about 5,000, for example. This second interlayer insulating film 32 is patterned to have an opening above the first opening 28 . As a result, the second glabellar insulating film 32 above the first opening 28 is opened to form a second opening 33. Tungsten silicide film 30 is exposed within this second opening 33. In this way, since the second opening 33 is opened on the tungsten silicide 30 after forming the titanium nitride film 29 and the tungsten silicide film 30 in advance, even if the aspect ratio of the second opening 33 is high, 2
A good tungsten silicide film 30 is obtained at the bottom of the opening 33.

Finally, as shown in FIG. 2(e), the second opening 33
A tungsten layer 34 is selectively grown therein.

At this time, as a pretreatment, for example, after performing light etching by passing sulfuric acid water, the RF power was set to 88W, NF, and the gas flow rate was 1103CC under reduced pressure to 0.05 Torr.
, Hz gas flow rate 70SCC? Perform Buri I7 as I. Then, the pressure was set to 0.2 Torr, and the temperature was set to 260″.
Set S i H to C, gas flow rate to 75CCM, W
Selective growth of the tungsten layer 34 is performed with the F & gas flow rate set at 10 SCCM, Hz and the gas flow rate set at 100 O3C.

This tungsten layer 34 is connected to the impurity region 26 via the titanium nitride vi, 29 and the tungsten silicide film 30. Since tungsten layer 34 is formed on tungsten silicide 1130, good selectivity is obtained. Therefore, the tungsten layer 34 can be reliably filled in the second opening 33 by selective growth without being affected by the underlying body. Thereby, electrode wiring with excellent reliability can be formed. In addition, tungsten layer 3
Since the titanium nitride film 29 is interposed between the tungsten layer 34 and the impurity region 26, the tungsten layer 34
There is no possibility that the impurity region 26' will react with the impurity region 26'. Therefore, sufficient heat resistance can be ensured.

[Effects of the Invention] As described above, in the present invention, in the contact hole, the high melting point metal material is selectively grown on a film that can be selectively grown, so that good selectivity can be obtained.

Therefore, the high melting point metal material can be selectively grown within the contact hole without being affected by the underlying layer that is the lower layer of the high melting point metal material. Therefore, even with a minute contact hole, highly reliable electrode wiring can be obtained.

Furthermore, since a barrier metal layer that functions as a heat-resistant layer is formed at the bottom of the first opening formed in the first interlayer insulating film on the semiconductor substrate, the barrier metal layer is not buried in the opening even if heat treatment is performed at high temperature. Reaction between the high melting point metal material and the semiconductor substrate is prevented. Therefore, a method for forming wiring with excellent heat resistance is provided.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are process cross-sectional views for explaining an example of the wiring forming method of the present invention according to its manufacturing process, and FIGS. 2(a) to 2(e) are ) are process cross-sections for explaining other examples according to their manufacturing processes, and the third example is a process cross section for explaining other examples according to the manufacturing process.
FIG. 3 is a cross-sectional view showing the structure of gL pole wiring. 1.21... Silicon substrate 5.25... Side wall film 6.26... (n' type) impurity region 7.27...
・First interlayer insulating film 8°9 10°12°13°4 28...First opening...Titanium nitride film 30...Titanium silicide film 32...Second interlayer insulating film 33 ...Second opening 34...Tungsten layer

Claims (2)

[Claims] (1) A first thin film having a first opening on a semiconductor substrate.
forming an insulating film, forming a film capable of selective growth so as to cover the semiconductor substrate exposed at the bottom of the first opening, and forming a second opening facing the bottom of the selectively growing film; 1. A method for forming wiring, comprising: forming a second insulating film having a second insulating film, and selectively growing a high melting point metal material within the second opening. (2) a first thin film having a first opening on a semiconductor substrate;
forming an insulating film, and forming a barrier metal layer to cover the semiconductor substrate exposed at the bottom of the first opening,
a second opening having a second opening portion where a film capable of selective growth is formed on the barrier metal layer, and the film capable of selective growth faces at the bottom;
1. A wiring forming method, comprising: forming an insulating film, and selectively growing a high melting point metal material within the second opening.