JPH03280448A - Dicing of semiconductor wafer - Google Patents
Dicing of semiconductor waferInfo
- Publication number
- JPH03280448A JPH03280448A JP2079905A JP7990590A JPH03280448A JP H03280448 A JPH03280448 A JP H03280448A JP 2079905 A JP2079905 A JP 2079905A JP 7990590 A JP7990590 A JP 7990590A JP H03280448 A JPH03280448 A JP H03280448A
- Authority
- JP
- Japan
- Prior art keywords
- roller
- chips
- wafer
- semiconductor wafer
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 235000012431 wafers Nutrition 0.000 claims description 15
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
未発IJIは、半導体ウェーハをチップに分離するダイ
シング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] Undeveloped IJI relates to a dicing method for separating semiconductor wafers into chips.
(従来の技術〕
ダイシング方法としては、レーザ、ダイヤモンド針によ
りチップに沿ってスクライブ線を刻設して機械的に分割
するスクライビング方式と、ダイシングソ一方式とある
。従来、前記スクライビング方式では、半導体ウェーハ
にスクライブ線を刻設してから、その線に沿ってローラ
を圧迫して分離している。(Prior Art) There are two dicing methods: a scribing method in which a scribe line is carved along the chip with a laser or a diamond needle to mechanically divide the chip, and a dicing saw method. Conventionally, in the scribing method, semiconductor wafers are A scribe line is carved into the material, and then a roller is pressed along the line to separate the material.
I−述した従来の機械的分離方法では、断面がほぼ真円
のローラを用いており、チップの大きさに合わせて適切
な径のローラを選ぶようにしている。小さなチップの場
合には小さな径の、大さなチップには大きな径のローラ
が適する。In the conventional mechanical separation method described above, a roller having a substantially perfect circular cross section is used, and the roller is selected to have an appropriate diameter depending on the size of the chips. A roller with a small diameter is suitable for small chips, and a roller with a large diameter is suitable for large chips.
一方、多品種少量生産を効率良く行なうために、最近は
、同一半導体ウェーハに大きさの異なるチップを組込む
ことが多くなっている。この場合、−枚の半導体ウェー
ハのチップ分離を行なうときに、チップの大きさの異な
る部分ごとにローラの径を変える必要があるので、数段
階に作Iを分けて行なわなければならないという欠点が
ある。On the other hand, in order to efficiently perform high-mix, low-volume production, chips of different sizes have recently been increasingly incorporated into the same semiconductor wafer. In this case, when separating the chips from two semiconductor wafers, it is necessary to change the diameter of the roller for each part of the chip of different size, so there is a drawback that the process must be carried out in several stages. be.
本発明の目的は、上記の欠点を除去し、大きさの異なる
チップを含む半導体ウェー/\を、ただ一つのローラを
用いてチップに分離することを可能とする方法を捉供す
ることにある。The object of the invention is to provide a method which obviates the above-mentioned drawbacks and makes it possible to separate a semiconductor wafer containing chips of different sizes into chips using only one roller.
本発明は、大きさの異なる種別のチー7プが少なくとも
2種以上含まれる半導体ウェーハにスクライブ線を刻設
した後、軸に垂直方向の外周面の曲率が部分的に異なる
ローラにより圧迫することによりチップ分離をする。The present invention involves scribing a scribe line on a semiconductor wafer containing at least two types of chips of different sizes, and then pressing the semiconductor wafer with rollers having partially different curvatures on the outer peripheral surface in the direction perpendicular to the axis. The chips are separated by
ローラの断面の曲率を、半導体ウェーハに含まれる、チ
ップの大きさのそれぞれ異なる領域に適合するように、
それぞれ部分的に適切な曲率になるように定める。これ
によって、ローラを変えることなく最適条件で、半導体
ウェーハを圧迫し、チップ分離を行なうことができる。The curvature of the cross section of the roller is adjusted to suit the different sizes of chips included in the semiconductor wafer.
Each part is determined to have an appropriate curvature. This makes it possible to press the semiconductor wafer and separate the chips under optimal conditions without changing the rollers.
以下1図面を参照して、本発明の実施例につき説明する
。第1図において、ローラ11はその断面を大きい曲率
半径のA部分と、小さい曲率半径のB部分とを含むよう
にしてあって、半導体ウェーハ1上を、回転軸lOのま
わりに回転させ、圧迫するようにしている。半導体つ工
−ハlは第3図に示すように1例えば2.II類のチッ
プ大きさを有し、スクライブ線IAが刻設されている。Embodiments of the present invention will be described below with reference to one drawing. In FIG. 1, the roller 11 has a cross section including a portion A with a large radius of curvature and a portion B with a small radius of curvature, and is configured to rotate and press the top of the semiconductor wafer 1 around the rotation axis lO. I have to. As shown in FIG. It has a class II chip size and has a scribe line IA engraved on it.
ローラ11を半導体基板l上で回転し、圧迫を加えると
きに、チップの大きさに適合した曲率で各部が圧迫され
、−回の操作でオリエンテーションフラッ)IBに垂直
方向のスクライブ線IAに沿って分離できる。When the roller 11 is rotated over the semiconductor substrate l and pressure is applied, each part is compressed with a curvature that matches the size of the chip, and the orientation is flattened by the -times operation along the scribe line IA perpendicular to the IB. Can be separated.
次に、第2実施例として、第2図にローラ駆動方式を変
えた例を示す、この例では部分的に曲率が異なる外側ロ
ーラ21を内側ギヤ22で駆動するようにしている。第
1実施例と同等の効果を提する。Next, as a second embodiment, an example in which the roller drive system is changed is shown in FIG. 2. In this example, outer rollers 21 having partially different curvatures are driven by inner gears 22. This provides the same effect as the first embodiment.
以上説明したように未発IJ1は2部分的に曲率の異な
るローラを用いてスクライブ線を刻設した半導体ウェー
ハを圧迫することにより、大きざの異なるチー2プを含
む半導体ウェーハを、唯一回の操作で個々のチップに分
割できる効果がある・As explained above, undeveloped IJ1 is produced by compressing a semiconductor wafer with scribe lines using two rollers with different curvatures. It has the effect of being able to be divided into individual chips by operation.
第1図、第2図は本発明の実施例の構成を示す断面図、
第3図は大きさの異なるチップを含む半導体ウェーハの
平面図である。
l・・・半導体ウェーハ、IA・・・スクライブ線、1
1・・・ローラ、 21・・・外側ローラ、22
・・・内側ギヤ。
特
許
出
願
人
n本電気株式
第2図
)
B
オリエンテーションフラット1 and 2 are cross-sectional views showing the configuration of an embodiment of the present invention,
FIG. 3 is a plan view of a semiconductor wafer containing chips of different sizes. l...Semiconductor wafer, IA...Scribe line, 1
1...Roller, 21...Outer roller, 22
...Inner gear. Patent Applicant n Hon Electric Stock Figure 2) B Orientation Flat
Claims (1)
まれる半導体ウェーハを、個々のチップに分離する工程
において、スクライブ線の刻設された半導体ウェーハ上
を、軸に垂直方向の外周面の曲率が部分的に異なるロー
ラにより圧迫することによってチップ分離をなすことを
特徴とする半導体ウェーハのダイシング方法。In the process of separating a semiconductor wafer containing at least two types of chips of different sizes into individual chips, the curvature of the outer peripheral surface in the direction perpendicular to the axis is A method for dicing semiconductor wafers, characterized in that chips are separated by pressure using different rollers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079905A JPH03280448A (en) | 1990-03-28 | 1990-03-28 | Dicing of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079905A JPH03280448A (en) | 1990-03-28 | 1990-03-28 | Dicing of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280448A true JPH03280448A (en) | 1991-12-11 |
Family
ID=13703302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2079905A Pending JPH03280448A (en) | 1990-03-28 | 1990-03-28 | Dicing of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280448A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5329157A (en) * | 1992-07-17 | 1994-07-12 | Lsi Logic Corporation | Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area |
| US5532934A (en) * | 1992-07-17 | 1996-07-02 | Lsi Logic Corporation | Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions |
| US5561086A (en) * | 1993-06-18 | 1996-10-01 | Lsi Logic Corporation | Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches |
| US5668400A (en) * | 1995-04-03 | 1997-09-16 | Xerox Corporation | Semiconductor wafer divisible into chips for creating or recording images |
| KR20160102336A (en) * | 2015-02-20 | 2016-08-30 | 가부시기가이샤 디스코 | Wafer dividing apparatus and wafer dividing method |
-
1990
- 1990-03-28 JP JP2079905A patent/JPH03280448A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5329157A (en) * | 1992-07-17 | 1994-07-12 | Lsi Logic Corporation | Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area |
| US5340772A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
| US5341024A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die |
| US5532934A (en) * | 1992-07-17 | 1996-07-02 | Lsi Logic Corporation | Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions |
| US5561086A (en) * | 1993-06-18 | 1996-10-01 | Lsi Logic Corporation | Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches |
| US5668400A (en) * | 1995-04-03 | 1997-09-16 | Xerox Corporation | Semiconductor wafer divisible into chips for creating or recording images |
| KR20160102336A (en) * | 2015-02-20 | 2016-08-30 | 가부시기가이샤 디스코 | Wafer dividing apparatus and wafer dividing method |
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