JPH03280456A - Lead frame used for semiconductor device - Google Patents

Lead frame used for semiconductor device

Info

Publication number
JPH03280456A
JPH03280456A JP2081537A JP8153790A JPH03280456A JP H03280456 A JPH03280456 A JP H03280456A JP 2081537 A JP2081537 A JP 2081537A JP 8153790 A JP8153790 A JP 8153790A JP H03280456 A JPH03280456 A JP H03280456A
Authority
JP
Japan
Prior art keywords
surface treatment
treated layer
lead
treatment layer
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2081537A
Other languages
Japanese (ja)
Inventor
Takeshi Takeuchi
武 竹内
Katsuhisa Kajiwara
梶原 克久
Minoru Takaoka
稔 高岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2081537A priority Critical patent/JPH03280456A/en
Publication of JPH03280456A publication Critical patent/JPH03280456A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To hold down the diffusion rate of Sn so as to prevent an Sn or a solder plating layer from deteriorating in adhesion or separating by a method wherein a part of a first-surface treated layer and all the third surface-treated layer are coated with resin, and the first-surface treated layer is interposed between a second surface-treated layer and a resin sealed region. CONSTITUTION:All outer lead 4 and a part of an inner lead 3 located inside a dam bar 5 are subjected to an Ni-plating treatment to form a first surface- treated layer 7. In succession, the surface of a region which is located outside of a resin sealed region and does not include the outer lead 4 is coated with a tin or a solder plating film to form a second surface-treated layer 8. Furthermore, a device mounting pad 2 and a wire bonding area 10 located at the tip of the inner lead 3 are subjected to a base partial plating treatment, which is coated with a gold or a tin plating layer to form a third surface-treated layer 9. In the lead frame 1 provided with the first third treated layer, 7-9, a semiconductor device 13 is fixed onto the device mounting pad 2, the bonding pad of the semiconductor device 13 is connected to the third surface-treated layer 9 located at the tip of the inner lead 3 with a wire 14 to constitute an electrically conductive circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、リードフレームの所要の部分を異種金属のめ
っき層で被覆した複数の表面処理層を有するリードフレ
ームに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame having a plurality of surface treatment layers in which required portions of the lead frame are coated with plating layers of different metals.

〔従来の技術〕[Conventional technology]

一般的な半導体装置は、リードフレームの素子搭載パッ
ドに表面処理層を介して半導体素子を固着し、この半導
体素子のポンディングパッドとリードフレームのインナ
ーリードとをワイヤで結線し、電気的導通回路を形成し
た後、これらを樹脂封止することによって製造されてい
る。
In a typical semiconductor device, a semiconductor element is fixed to the element mounting pad of a lead frame via a surface treatment layer, and the bonding pad of the semiconductor element and the inner lead of the lead frame are connected with a wire to form an electrically conductive circuit. It is manufactured by forming these and then sealing them with resin.

半導体装置に用いられるリードフレーム31は、第3図
に示すように、半導体素子を搭載する素子搭載パッド3
2と、先端がこの素子搭載パッド32を取り囲むように
放射状に配列したインナーリード33と、これらのイン
ナーリード33と直交する方向に延びてインナーリード
33を一体的に支持するダムバー35と、このダムバー
35を介して各インナーリード33に対応して接続する
ように配置したアウターリード34と、素子搭載パッド
32を支持するサポートパー36とから構成されている
As shown in FIG. 3, a lead frame 31 used in a semiconductor device has an element mounting pad 3 on which a semiconductor element is mounted.
2, inner leads 33 whose tips are arranged radially so as to surround the element mounting pad 32, a dam bar 35 which extends in a direction perpendicular to these inner leads 33 and integrally supports the inner leads 33, and this dam bar. The outer lead 34 is arranged to be connected to each inner lead 33 via a wire 35, and a support pad 36 supports the element mounting pad 32.

このリードフレーム31は、インナーリード33の先端
部分を金めつき又は銀めっき等の表面処理層が施される
。これらの表面処理層は、樹脂封止後の工程で行われて
いる。
In this lead frame 31, the tip portions of the inner leads 33 are subjected to a surface treatment layer such as gold plating or silver plating. These surface treatment layers are performed in a step after resin sealing.

このようにめっき層を施すため製造工程が複雑になるの
で、コスト面での障害の一つとなる。また、樹脂封止と
リードとの境界の隙間からめっき液に含まれる腐食性成
分(CI−、SO,−、F−など)が侵入し、ボンディ
ングワイヤを腐食させ、断線の原因となるなど信頼性の
低下の一因ともなっている。
Applying a plating layer in this way complicates the manufacturing process, which is one of the obstacles in terms of cost. In addition, corrosive components contained in the plating solution (CI-, SO,-, F-, etc.) may enter through the gap between the resin seal and the lead, corrode the bonding wire, and cause disconnection. It is also a factor in the decline in sexuality.

このような問題を解消するため、従来では第4図に示す
ような構造が採用されている。これは、樹脂封止する前
の工程で、リードフレーム31の素子搭載パッド32及
びインナーリード33の先端部に金又は銀めっき等の表
面処理層37を形成し、更にアウターリード34及びイ
ンナーリード33の一部を含む領域を半田めっきの表面
処理層38で被覆したものである。そして、このような
表面処理を施したリードフレーム31を用いる場合、表
面処理層38は樹脂39による封止領域に含まれて製品
化されている。
In order to solve this problem, a structure as shown in FIG. 4 has been conventionally adopted. This is a step before resin sealing, in which a surface treatment layer 37 such as gold or silver plating is formed on the tip of the element mounting pad 32 and the inner lead 33 of the lead frame 31, and then the outer lead 34 and the inner lead 33 are coated with a surface treatment layer 37. A region including a part of is covered with a surface treatment layer 38 of solder plating. When the lead frame 31 subjected to such surface treatment is used, the surface treatment layer 38 is included in the sealing area with the resin 39 and is manufactured into a product.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、表面処理層38の錫又は錫合金は厚いポーラ
スな酸化被膜を形成しやすく、また錫酸化被膜は金属素
地との密着性が悪く簡単に剥離してしまう性質がある。
However, the tin or tin alloy of the surface treatment layer 38 tends to form a thick porous oxide film, and the tin oxide film has poor adhesion to the metal base and easily peels off.

このため、半田めっきの表面処理層38が樹脂39によ
って被覆されていると、このような剥離現象によって表
面処理層38と樹脂39との間に隙間を生じることある
。したがって、この隙間から水分や腐食成分等が侵入し
て、半導体装置の信頼性を低下させる恐れがある。
Therefore, if the surface treatment layer 38 of solder plating is covered with the resin 39, a gap may be created between the surface treatment layer 38 and the resin 39 due to such a peeling phenomenon. Therefore, there is a risk that moisture, corrosive components, etc. may enter through this gap, reducing the reliability of the semiconductor device.

これに対し、半田めっきの表面処理層を樹脂の封止領域
の外部に施すものもある。しかし、これを用いる場合で
は、表面処理層と樹脂との聞にリードフレーム材料の金
属素地が露出してしまう。
On the other hand, some devices apply a surface treatment layer of solder plating to the outside of the resin sealing area. However, when this is used, the metal base of the lead frame material is exposed between the surface treatment layer and the resin.

リードフレームの金属素地は、Cu系の合金又は42%
Niの合金が主として利用されているが、Cu系の合金
は大気中でCuOの酸化被膜を形成しやすく、また42
%Niの合金は樹脂との熱膨張係数に大きな差異があり
しかもFed、 Fe20s の錆が生じる点から、長
期間にわたっての信頼性に欠けるという問題がある。
The metal base of the lead frame is Cu-based alloy or 42%
Ni alloys are mainly used, but Cu-based alloys tend to form a CuO oxide film in the atmosphere, and 42
%Ni alloy has a large difference in thermal expansion coefficient from that of the resin, and also has the problem of lacking long-term reliability because it rusts like Fed and Fe20s.

更に、リードフレームの他の種類には、銅又は銅合金の
上に直接銀又は半田めっきを施したり、銅めっきを施し
た上の層に錫又は半田めっきを施すものもある。この場
合では、長期の使用環境によって、SnとCuの相互拡
散が起こり、錫又は半田めっき層と下地めっき層との境
界面に多数の空孔が発生する。このため、錫又は半田め
っき層の密着性の劣化を生じ、カーケンダル効果によっ
て錫又は半田めっき層が簡単に剥離してしまう。
Further, other types of lead frames include those in which silver or solder plating is directly applied on copper or copper alloy, or in which tin or solder plating is applied to a layer on top of copper plating. In this case, due to the long-term use environment, mutual diffusion of Sn and Cu occurs, and a large number of pores are generated at the interface between the tin or solder plating layer and the base plating layer. Therefore, the adhesion of the tin or solder plating layer deteriorates, and the tin or solder plating layer easily peels off due to the Kirkendall effect.

そこで、本発明は、従来の欠点を全て解消し安定性及び
信頼性に優れた表面処理層を形成することによって、高
い品質のリードフレームを提供することを目的とする。
Therefore, an object of the present invention is to provide a high quality lead frame by eliminating all the conventional drawbacks and forming a surface treatment layer with excellent stability and reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のリードフレームは、アウターリードの基端部側
までを含み且つワイヤボンディング領域の外のインナー
リード及び半導体素子の素子搭載パッドの裏面をNi又
はNi合金によって被覆して第1表面処理層を形成し、
樹脂封止領域の外側の前記アウターリードをSn又はS
n合金によって被覆して第2表面処理層を形成し、更に
前記素子搭載パッドの搭載面側及びインナーリードのワ
イヤボンディング領域を八〇又は八g又はPd又はその
合金によって被覆して第3表面処理層を形成したことを
特徴とする。
In the lead frame of the present invention, the inner lead including the base end side of the outer lead and outside the wire bonding area and the back surface of the element mounting pad of the semiconductor element are coated with Ni or a Ni alloy, and a first surface treatment layer is formed. form,
The outer lead outside the resin sealing area is made of Sn or S.
n alloy to form a second surface treatment layer, and further coat the mounting surface side of the element mounting pad and the wire bonding area of the inner lead with 80 or 8g or Pd or an alloy thereof to form a third surface treatment layer. It is characterized by forming a layer.

〔作用〕[Effect]

本発明のリードフレームを用いて半導体装置を組み立て
ると、樹脂封止領域と非封止領域との境界線は第1表面
処理層の上を走る。一方、半導体素子の搭載やワイヤボ
ンディング等の半導体装置組立て工程における高温処理
を経る過程で、第1表面処理層のNi又はNi−Sn合
金のめっき層の表面は酸化されて数100 人の厚さの
酸化被膜を形成する。この酸化被膜はNiOと推定され
、樹脂との密着性は従来の42%Ni系合金、コバルト
、銅或いは銅合金等と樹脂との密着性よりも遥かに優れ
ている。このため、樹脂封止後に樹脂とリードフレーム
との間に水分や腐食性成分が侵入することが防止される
When a semiconductor device is assembled using the lead frame of the present invention, the boundary line between the resin-sealed region and the non-sealed region runs on the first surface treatment layer. On the other hand, during high-temperature treatment in semiconductor device assembly processes such as mounting of semiconductor elements and wire bonding, the surface of the Ni or Ni-Sn alloy plating layer of the first surface treatment layer is oxidized to a thickness of several hundred nanometers. forms an oxide film. This oxide film is estimated to be NiO, and its adhesion to the resin is far superior to that of conventional 42% Ni-based alloys, cobalt, copper, copper alloys, etc. and resins. Therefore, moisture and corrosive components are prevented from entering between the resin and the lead frame after resin sealing.

また、アウターリードの第2表面処理層と樹脂との間に
は第1表面処理層が介在するので、半導体装置の組立て
工程や使用環境においてSnとNiのNis Sn、等
の金属間化合物が形成され、Snのリードフレームへの
拡散が阻止される。
In addition, since the first surface treatment layer is interposed between the second surface treatment layer of the outer lead and the resin, intermetallic compounds such as Sn and Ni (Nis Sn) are formed during the assembly process and usage environment of the semiconductor device. This prevents Sn from diffusing into the lead frame.

〔実施例〕〔Example〕

第1図は本発明のリードフレームの平面図、第2図は第
1図のI−I線矢視位置であってめっき処理した後の断
面図である。
FIG. 1 is a plan view of the lead frame of the present invention, and FIG. 2 is a sectional view taken along the line I--I in FIG. 1 after plating.

リードフレーム1は、従来例と同様に、半導体素子の素
子搭載パッド2.インナーリード3.アウターリード4
.ダムバー5及び素子搭載パッド2のサポートパー6を
プレス加工によって成形したものである。
As in the conventional example, the lead frame 1 has device mounting pads 2 . Inner lead 3. outer lead 4
.. The dam bar 5 and the support part 6 of the element mounting pad 2 are formed by press working.

このプレス加工した後のリードフレーム1はめっき工程
に送られ、まずアウターリード4の全体及びダムバー5
より内側のインナーリード3の一部をNiめっき処理し
て第1表面処理層7を形成させる。この第1表面処理層
7はNi−Sn合金でもよく、また厚さは1μm程度で
ある。
The lead frame 1 after this press processing is sent to a plating process, and first the entire outer lead 4 and the dam bar 5 are plated.
A part of the inner lead 3 on the inner side is subjected to Ni plating treatment to form a first surface treatment layer 7 . This first surface treatment layer 7 may be made of a Ni-Sn alloy, and has a thickness of about 1 μm.

次いで、樹脂封止領域より外側に出る範囲であって且つ
アウターリード4含まない領域までの前面を錫又は半田
めっきで被覆して第2表面処理層8を形成する。この第
2表面処理層8の厚みは1〜2μm程度である。
Next, a second surface treatment layer 8 is formed by covering the front surface of the resin-sealed area to the area outside the resin-sealed area and not including the outer leads 4 with tin or solder plating. The thickness of this second surface treatment layer 8 is approximately 1 to 2 μm.

更に、素子搭載パッド2及びインナーリード3の先端部
のワイヤボンディングエリア10に1μm程度の下地の
部分めっきを施した後、金又は銀めっき層で被覆して第
3表面処理層9を形成する。
Further, the element mounting pad 2 and the wire bonding area 10 at the tip of the inner lead 3 are partially plated with a base of about 1 μm, and then covered with a gold or silver plating layer to form a third surface treatment layer 9.

この第3表面処理層9の銅下地めっきは、リードフレー
ムlの前面に施してよいが、第3表面処理層9の上層の
銅下地めっき層をにCN溶液中で陽極電解処理して剥離
溶解除去する。
The copper base plating of the third surface treatment layer 9 may be applied to the front surface of the lead frame l, but the upper copper base plating layer of the third surface treatment layer 9 may be peeled off and dissolved by anodic electrolytic treatment in a CN solution. Remove.

第1〜第3表面処理層7〜9を施したリードフレーム1
は、第2図に示すように素子搭載パッド2の上に半導体
素子13を固着し、この半導体素子13のポンディング
パッドとインナーリード3の先端の第3表面処理層9と
をワイヤ14で結線して電気的導通回路を形成させる。
Lead frame 1 provided with first to third surface treatment layers 7 to 9
As shown in FIG. 2, the semiconductor element 13 is fixed on the element mounting pad 2, and the bonding pad of the semiconductor element 13 and the third surface treatment layer 9 at the tip of the inner lead 3 are connected with a wire 14. to form an electrically conductive circuit.

そして、これらの半導体素子13及びワイヤ14を一体
にして、樹脂封止境界線11の中の領域を樹脂12によ
って封止すれば製品が得られる。
Then, by integrating these semiconductor elements 13 and wires 14 and sealing the area within the resin sealing boundary line 11 with resin 12, a product is obtained.

なお、インナーリード3及び素子搭載パッド20表面処
理層はインナーリード3の先端部のみでもよい。また、
樹脂は無機質材料でもよいことは熱論であり、表面処理
層はめっきだけでなく蒸着やクラッド等の手法であって
もよい。
Note that the surface treatment layer of the inner leads 3 and the element mounting pads 20 may be applied only to the tips of the inner leads 3. Also,
It is a matter of theory that the resin may be an inorganic material, and the surface treatment layer may be formed not only by plating but also by vapor deposition, cladding, or the like.

〔発明の効果〕〔Effect of the invention〕

本発明では、第1表面処理層の一部と第3表面処理層の
全体とが樹脂によって被覆され、第2表面処理層と樹脂
封止領域との間に第1表面処理層を介在させている。こ
のため、Snの拡散速度が抑制され、Sn又は半田めっ
き層の密着性の劣化や剥離を防ぐことができる。
In the present invention, a part of the first surface treatment layer and the entire third surface treatment layer are coated with resin, and the first surface treatment layer is interposed between the second surface treatment layer and the resin sealing region. There is. Therefore, the diffusion rate of Sn is suppressed, and deterioration in adhesion and peeling of Sn or the solder plating layer can be prevented.

また、樹脂で封止する以前に、表面処理層がリードフレ
ームの所要の箇所を被覆しているので、不純物による腐
食性成分等の付着も少なくなる。
Furthermore, since the surface treatment layer covers the required portions of the lead frame before sealing with the resin, the adhesion of corrosive components due to impurities is reduced.

このため、樹脂とリードフレームとの密着性も良く、安
定性及び信頼性の高い半導体装置が得られる。更に、従
来の製造過程に比べると工程数も少なくなり、コスト面
でも有利となる。
Therefore, the adhesion between the resin and the lead frame is good, and a highly stable and reliable semiconductor device can be obtained. Furthermore, compared to conventional manufacturing processes, the number of steps is reduced, making it advantageous in terms of cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のリードフレームの平面図、第2図はリ
ードフレーム及び表面処理層の厚さを拡大して示す第1
図の1−1線矢視位置での縦断面図、第3図及び第4図
は従来例を示すものである。 1:リードフレーム 2:素子搭載パッド3;インナー
リード 4;アウターリード5;ダムバー    6:
サポートパー7:第1表面処理層 8:第2表面処理層
9:第3表面処理層 lO;ワイヤボンディングエリア 11:樹脂封止領域境界線 12;樹脂      13:半導体素子14:ワイヤ
FIG. 1 is a plan view of the lead frame of the present invention, and FIG. 2 is an enlarged view of the lead frame and the thickness of the surface treatment layer.
A longitudinal sectional view taken along the line 1-1 in the figure, and FIGS. 3 and 4 show a conventional example. 1: Lead frame 2: Element mounting pad 3; Inner lead 4; Outer lead 5; Dam bar 6:
Support par 7: First surface treatment layer 8: Second surface treatment layer 9: Third surface treatment layer lO; Wire bonding area 11: Resin sealing region boundary line 12; Resin 13: Semiconductor element 14: Wire

Claims (1)

【特許請求の範囲】[Claims] 1、アウターリードの基端部側までを含み且つワイヤボ
ンディング領域の外のインナーリード及び半導体素子の
素子搭載パッドの裏面をNi又はNi合金によって被覆
して第1表面処理層を形成し、樹脂封止領域の外側の前
記アウターリードをSn又はSn合金によって被覆して
第2表面処理層を形成し、更に前記素子搭載パッドの搭
載面側及びインナーリードのワイヤボンディング領域を
Au又はAg又はPd又はその合金によって被覆して第
3表面処理層を形成したことを特徴とする半導体装置に
用いるリードフレーム。
1. A first surface treatment layer is formed by coating the inner lead outside the wire bonding area and the back surface of the element mounting pad of the semiconductor element including up to the base end side of the outer lead with Ni or Ni alloy, and resin sealing. The outer lead outside the stop area is coated with Sn or a Sn alloy to form a second surface treatment layer, and the mounting surface side of the element mounting pad and the wire bonding area of the inner lead are coated with Au, Ag, Pd, or the like. A lead frame for use in a semiconductor device, characterized in that the lead frame is coated with an alloy to form a third surface treatment layer.
JP2081537A 1990-03-28 1990-03-28 Lead frame used for semiconductor device Pending JPH03280456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2081537A JPH03280456A (en) 1990-03-28 1990-03-28 Lead frame used for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2081537A JPH03280456A (en) 1990-03-28 1990-03-28 Lead frame used for semiconductor device

Publications (1)

Publication Number Publication Date
JPH03280456A true JPH03280456A (en) 1991-12-11

Family

ID=13749053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2081537A Pending JPH03280456A (en) 1990-03-28 1990-03-28 Lead frame used for semiconductor device

Country Status (1)

Country Link
JP (1) JPH03280456A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300678B1 (en) 1997-10-03 2001-10-09 Fujitsu Limited I/O pin having solder dam for connecting substrates
WO2017179447A1 (en) * 2016-04-12 2017-10-19 古河電気工業株式会社 Lead frame material and method for producing same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161850A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Resin sealed type semiconductor device and lead frame used therefor
JPS6249646A (en) * 1985-08-29 1987-03-04 Shinko Electric Ind Co Ltd Lead frame
JPH0290661A (en) * 1988-09-28 1990-03-30 Kobe Steel Ltd Semiconductor device lead frame and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161850A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Resin sealed type semiconductor device and lead frame used therefor
JPS6249646A (en) * 1985-08-29 1987-03-04 Shinko Electric Ind Co Ltd Lead frame
JPH0290661A (en) * 1988-09-28 1990-03-30 Kobe Steel Ltd Semiconductor device lead frame and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300678B1 (en) 1997-10-03 2001-10-09 Fujitsu Limited I/O pin having solder dam for connecting substrates
WO2017179447A1 (en) * 2016-04-12 2017-10-19 古河電気工業株式会社 Lead frame material and method for producing same
JPWO2017179447A1 (en) * 2016-04-12 2018-04-19 古河電気工業株式会社 Lead frame material and manufacturing method thereof

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