JPH0590465A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Prevents peeling of the Pd layer on the surface, and also maintains the long-term reliability by satisfying the essential conditions of semiconductor devices such as electrical conductivity, low contact property, bonding property, and solder wettability. To provide a high quality semiconductor device that can be manufactured. [Structure] The element mounting portion 24 on which a required shape processing is performed,
A lead frame including an inner lead 25 and an outer lead 26, a semiconductor element 27 mounted on the element mounting portion 24, the semiconductor element 27 and the inner lead 25.
In the semiconductor device 23 having a wire 29 for connecting the semiconductor element 27, the semiconductor element 27, the wire 29 and the inner lead 25, and an electrically insulating resin 30 for sealing and encapsulating a predetermined region of the lead frame, The Pd layer 35 is provided as the uppermost layer, and the Sn—Ni layer 33 is provided as an intermediate portion, and the Cu thin layer 34 is formed between the Pd layer 35 and the Sn—Ni layer 33. There is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a lead frame which is useful for preventing heat diffusion of metals, electromigration and corrosion caused by battery operation and whose coating layer does not peel off even when bent. ..

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated and have high performance, and accordingly, semiconductor packages have been miniaturized and thinned, or the number of pins of the same size has been increased. Therefore, a QFP whose partial cross section is shown in FIG.
In the (Quad Flat Package) type semiconductor device 10, for example, the outer lead pitch is 0.3.
mm, and the number of pins is required to be 200 to 300 pins.
Therefore, as shown in FIG. 2, the lead widths and intervals of the outer leads 11 and the inner leads 12 are made narrower, the package thickness is made thinner, and the surface coating layers of the outer leads 11 and the inner leads 12 are made thinner to make the same as the above. It was necessary to cope with the increase in the number of pins within the size and the reduction in thickness, and to prevent electrical corrosion and electromigration. Further, the conventional semiconductor device 10 made into a chip has a C
A metal member of a lead frame in which a metal strip material such as a u alloy or a Ni alloy is formed into a desired shape by etching or pressing is used. The lead frame includes an element mounting portion 14 on which the semiconductor element 13 is mounted, an inner lead 12 that connects the pad portion 15 of the semiconductor element 13 through a wire 16 to form an electrical conduction circuit, and a connection that holds the inner lead 12. The inner leads 1 connected to each other by
Outer lead 1 that composes the external connection terminal corresponding to 2
1 and. The lead frame is entirely Ni
In addition to the underlying plating layer 17 such as, the wire bonding portion 18 of the inner lead 12 and the element mounting portion 14 are partially plated with a noble metal such as Ag.
Therefore, in manufacturing the semiconductor device 10, the semiconductor element 13 is generally mounted on the element mounting portion 14 of the lead frame.
, One end of the wire 16 is bonded to the pad portion 15 of the semiconductor element 13, and the other end is connected to the wire bonding portion 18 at the tip of the inner lead 12 to form an electric circuit. It is covered and sealed with 20. Then, a connection portion (not shown) having the outer leads 11 protruding around the insulating resin 20 is separated and molded, and then the solder coating layer 21 is formed on the protruding outer leads 11 to manufacture a semiconductor device. .. In the lead frame plating coating structure used for the semiconductor device 10 according to the conventional example, the width and interval of the outer leads 11 and the inner leads 12 become narrower in accordance with the increase in the number of pins and the reduction in thickness described above, and accordingly the surface It is necessary to reduce the thickness of the plating coating layer. However, if the coating layer is made thin, there is a drawback that a large number of pinholes, which are large defects against corrosion of the plating coating layer, are generated depending on the plating solution and plating conditions. Further, when the pinhole is present in the plating coating layer, a potential difference occurs between the base metal layer and the uppermost plated metal layer through the pinhole to form a local battery. A battery action occurs between the metal layer and the plated metal layer, the metal of the base metal layer dissolves, precipitates and oxidizes through the pinholes, contaminates the surface of the plated metal of the uppermost layer, and lowers the solder wettability. In addition, there is a problem that the base metal layer is corroded.

[0003]

Therefore, the applicant of the present invention is
First, in Japanese Patent Application No. 3-135483, we proposed a semiconductor device in which the surface of a lead frame was coated with a thin plating of a dissimilar metal with the uppermost layer being a Pd layer, and a solution to the above problems was obtained. It was However, when the Pd layer is formed as the uppermost layer of the lead frame and the Sn-Ni layer is formed as the lower layer thereof, when the outer lead is bent in the final step, it depends on the plating conditions, etc. Since the affinity between the Pd layer and the Sn-Ni layer thereunder is not sufficient,
There was a problem that it might peel off. The present invention has been made in view of such circumstances, and it is possible to prevent peeling of the Pd layer on the surface and further satisfy the essential conditions of the semiconductor device such as electrical conductivity, low contact property, bonding property, and solder wettability for a long time. An object is to provide a high quality semiconductor device which can maintain reliability.

[0004]

A method according to the above-mentioned object.
The semiconductor device described above is mounted on the element mounting portion, which is a lead frame made of a metal member having an element mounting portion subjected to a required shape processing, an inner lead and an outer lead and having a metal coating layer formed on the surface thereof. A semiconductor element, a wire connecting the pad portion of the semiconductor element and the tip of the inner lead to form an electric conduction circuit, and a predetermined area of a lead frame including the semiconductor element, the wire and the inner lead, which is covered and sealed. In the semiconductor device having an electrically insulating resin that stops, the uppermost layer of the metal coating layer of the lead frame is a Pd layer, the intermediate layer is a Sn-Ni layer, and the Pd layer and the Sn-Ni layer are the same. An ultra-thin Cu layer is formed in the middle. The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the Pd layer has a thickness of 0.05 to 0.3 μm.
m, the thickness of the Cu ultra-thin layer is 0.05 to 0.3 μm, Sn−
The Ni layer has a thickness in the range of 0.5 to 3 μm.

[0005]

In the semiconductor device according to any one of claims 1 and 2, the uppermost layer of the metal cover layer of the lead frame is a Pd layer, the intermediate layer is a Sn-Ni layer, and the Pd layer and the Sn-Ni layer are the same. An ultra-thin Cu layer is formed in the middle of.
The Cu layer has a strong affinity with the lower Sn-Ni layer, and further has a strong affinity with the uppermost Pd layer, and as a result, the bonding force between the Sn-Ni layer and the Pd layer is increased, which causes bending. It is possible to prevent peeling of the uppermost Pd layer during processing.

[0006]

Embodiments of the present invention will now be described with reference to the accompanying drawings to provide an understanding of the present invention. 1 shows a partial cross-sectional view of a semiconductor device 23 according to one embodiment of the present invention, the semiconductor device 23 according to one embodiment of the present invention includes an element mounting portion 24, an inner lead 2
5 and a lead frame including the outer lead 26,
Semiconductor element 2 bonded to the element mounting portion 24
7, a wire 29 having one end connected to the pad portion 28 of the semiconductor element 27 and the other end connected to the inner lead 25 to form an electric circuit, and an insulating synthetic resin 30 covering and encapsulating the wire 29. Is configured.

The lead frame is made of a Cu alloy (or Ni alloy) metal member, and an element mounting portion 24, inner leads 25, and outer leads 26 are formed by pressing or etching. When the press working is performed, a stress relieving annealing process is performed in order to remove the residual stress. The lead frame has a metal coating layer 31 formed by plating together with a connecting portion (not shown) formed outside the outer lead 26. The metal coating layer 31 is a base layer made of a thin plating layer. Ni strike layer 32 that forms a layer, an Sn-Ni layer 33 that is an intermediate layer, a Cu layer 34 that forms a bonding layer thereabove, and a Pd layer 35 that is the uppermost layer.
It is composed by. Here, the Ni strike layer 32 is provided for the thermal diffusion of Cu contained in the metal member and the prevention of plating solution contamination. And Sn in the middle part
The Ni layer 33 stochastically covers the pinholes of the base layer, the Cu layer 34 above the metal member and the Pd layer 3 of the uppermost layer.
5 to prevent the generation of local batteries. And, even if a local battery is formed between the metal member and the uppermost layer in which the upper and lower pinholes are continuous, the potential difference between them is alleviated by providing the intermediate layer, and the battery action corrosion of the metal member layer and In addition to preventing the metal from being precipitated and oxidized on the uppermost layer, the reliability of the semiconductor device is improved by eliminating a short circuit between leads due to electromigration. In addition,
The Sn—Ni layer 33 has a thickness of 0.5 to 3 μm (preferably about 1 μm), and the Cu layer 34 has a thickness of 0.05 to 0.3.
μm (preferably about 0.1 μm), and the thickness of the Pd layer 35 is 0.05 to 0.3 μm (preferably about 0.1 μm).
m).

As described above, after the semiconductor element 27 is bonded to the element mounting portion 24 of the lead frame on which the metal cover layer is formed, the pad portion 28 of the semiconductor element 27 and the tip portion of the inner lead 25 are connected by the wire 29. They are connected to form an electric circuit. Thereafter, the tip portions of the element mounting portion 24, the semiconductor element 27, the inner lead 25, and the outer lead 26 are covered and sealed with an insulating synthetic resin 30, and are integrated with the tips of the outer leads protruding from the covered and sealed area. The semiconductor device 23 is completed by separating the connecting portion (not shown) that is joined as shown in FIG. The present invention is also applicable to the case where the Ni strike layer is omitted in the above embodiment.

[0009]

In the semiconductor device according to the present invention, the metal cover layer of the lead frame has the uppermost layer of the Pd layer and the intermediate layer of the Sn-Ni layer, and further, the P
Since the Cu ultra-thin layer is formed between the d layer and the Sn—Ni layer, the Cu layer functions as an intermediate bonding layer, which prevents peeling of the uppermost Pd layer during bending.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor device according to a conventional example.

[Explanation of symbols]

 23 Semiconductor Device 24 Element Mounting Part 25 Inner Lead 26 Outer Lead 27 Semiconductor Element 28 Pad Part 29 Wire 30 Insulating Synthetic Resin 31 Metal Covering Layer 32 Ni Strike Layer 33 Sn-Ni Layer 34 Cu Layer 35 Pd Layer

Claims (2)

[Claims] 1. An element mounting portion which has been subjected to required shape processing,
A lead frame made of a metal member having an inner lead and an outer lead and having a metal coating layer formed on the surface, a semiconductor element mounted on the element mounting portion, a pad portion of the semiconductor element, and the inner lead tip. A wire that is connected to form an electric conduction circuit, and the semiconductor element,
In a semiconductor device having an electrically insulating resin that covers and seals a predetermined area of a lead frame including the wire and the inner lead, the metal cover layer of the lead frame has a Pd layer as an uppermost layer and a Sn- layer as an intermediate layer. It consists of a Ni layer and the P
A semiconductor device, wherein an extremely thin Cu layer is formed between the d layer and the Sn-Ni layer. 2. The thickness of the Pd layer is 0.05 to 0.3 μm,
The thickness of the Cu ultra-thin layer is 0.05 to 0.3 μm, Sn-Ni
The semiconductor device according to claim 1, wherein the thickness of the layer is in the range of 0.5 to 3 μm.