JPH03280461A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve a semiconductor device in reliability by a method wherein a silicon nitride film is formed under such conditions that a deposition temperature is set to a prescribed value or below and a deposition rate is set to a prescribed value or above. CONSTITUTION:A silicon nitride film is formed through a CVD method under such condition that the deposition temperature is set to 680 deg.C or below and the deposition rate is set to 2Angstrom /min or above. it is preferable that the deposition rate is set to 4Angstrom /min or above. For instance, a thin oxide film 106 is formed as thick as 5nm through thermal oxidation, and successively a CVD silicon nitride 107 10nm in thickness is formed through a CVD method where dichlorosilane is made to react with ammonia at a deposition temperature of 660 deg.C under a reduced deposition pressure of 0.6Torr. At this point, the reason why a deposition temperature is set to 660 deg.C is that nitrogen becomes small in thermal oscillation mobility at an initial growth stage on the surface of a substrate to slow down the growth of nucleuses when a deposition temperature is set lower than 660 deg.C.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method of manufacturing a semiconductor device, and In particular, it relates to improvements in the process of forming ultra-thin silicon nitride films.

(Prior Art) One of the conventionally known semiconductor devices is a DRAM (DRAM), which configures a memory cell by combining a capacitor and a transistor.
s read vrlte Memory)
There is. In this device, a silicon dioxide (S i 02) film is conventionally used as a capacitor insulating film formed between a capacitor electrode and a semiconductor substrate. Since the capacitance of a capacitor can be increased by reducing the thickness of a capacitor insulating film, the thickness of an oxide film for a DRAM capacitor is rapidly becoming thinner as the degree of integration increases. This thickness cannot be made as thin as you want, so
Recently, materials with higher dielectric constants than oxide films have begun to attract attention.

For example, consideration is being given to using a silicon nitride film having a higher dielectric constant than 5in2 as an insulating film.

In this case, since there is a lot of leakage current in the silicon nitride film itself, its applied form is a so-called two-layer film (nitride film - thermal oxide film) or a three-layer film (thermal oxide film - nitride film - thermal oxide film). are being considered.

The problem with using such a composite film is that the effective film thickness increases and the capacitance of the capacitor decreases.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to reduce the thickness of each film. However, as the oxide film becomes thinner, a new problem arises: an increase in leakage current, which in turn leads to deterioration of dielectric strength.

On the other hand, a problem when forming an extremely thin silicon nitride film by the CVD method is non-uniformity in film thickness at the atomic level due to island growth at the initial stage of deposition. As a result of this island growth, in a silicon nitride film with a thickness of about 10 nm, the dielectric breakdown voltage is significantly lowered at a thinner part. This problem becomes particularly serious when a thermal oxide film is formed on a nitride film. This is because, when a nitride film is thermally oxidized, the oxidation progresses from the thin part of the film to the underlying layer, resulting in a significant increase in film thickness. This causes not only an increase in film thickness but also a significant deterioration in breakdown voltage. Therefore, the device deteriorates and the reliability of the DRAM etc. is reduced.

(Problems to be Solved by the Invention) As described above, when silicon nitride films are made thinner, non-uniformity in film thickness occurs at the atomic level due to island growth in the initial stage of deposition. There was a problem in that the dielectric strength of the film deteriorated.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a step of forming a silicon nitride film that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The method of the present invention, when forming a silicon nitride film by the CVD method, sets the deposition temperature to 680°C or less and the deposition rate to 2 people/■In or more. It is characterized by As for the deposition speed, more preferably 4
Person/sin or more.

(Function) When a silicon nitride film is formed by the CVD method under such conditions, island growth at the initial stage of deposition is suppressed. As a result, the non-uniformity in film thickness caused by this can be prevented, and the dielectric strength of the ultra-thin nitride film or its composite film is improved. It is particularly effective for thin films of about 30 to 200 layers used in semiconductor devices.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 1A to 1D are cross-sectional views showing the manufacturing process of a first embodiment in which the present invention is applied to a trench capacitor in a DRAM. First, as shown in FIG. 1(a), a P-type (100) silicon substrate 1 with a specific resistance of 5 to 50 Ω.
01 is prepared, and a field oxide film 10 is formed by selective oxidation.
form 2.

Next, as shown in FIG. 1(b), a CVD oxide film 103 of about 0.8 μm is formed on the entire surface, and this CVD oxide film 103 is
After patterning 3, a groove 104 having a depth of about 3 μm and having vertical sidewalls is formed on the surface of the silicon substrate by reactive ion etching (RIE) using this as a mask.

After this, as shown in FIG. 1(C), the CVD oxide film 103
After removing, an n-type impurity layer 105 is formed on the sidewalls of trench 104 and the silicon surface of other capacitor regions.

A thin oxide film 106 with a thickness of 5 nm is formed by thermal oxidation,
Subsequently, a CVD silicon nitride film 107 with a thickness of Q nm was formed by a CVD method using a reaction between dichlorosilane and ammonia (flow rate ratio 1:10) at a deposition temperature of 660° C. and a deposition pressure of 0 and 6 Torr.
form. At this time, the reason why the deposition temperature is set to 660° C. is that at a temperature of 680° C. or lower, the thermal vibrational movement of nitrogen on the substrate surface at the initial stage of growth is reduced and the growth of nuclei is slowed down. However, even at such a low temperature, if the deposition rate is too slow, island growth will occur because there will be enough time for nitrogen to grow as a nucleus. In addition to temperature, pressure is another factor that slows down the deposition rate; generally, the lower the pressure, the slower the deposition rate.

Formation of a silicon nitride film through the reaction of ammonia and dichlorosilane is usually carried out in a reduced pressure atmosphere where the partial pressure of ammonia is sufficiently large compared to that of dichlorosilane, but if the partial pressure of ammonia becomes too large, The deposition rate becomes smaller.

Therefore, in order to increase the deposition rate, the deposition pressure is set to 0.6 Torr and the flow rate ratio of ammonia to dichlorosilane is set to 10. Thereafter, a thermal oxide film 108 is formed on the CVD silicon nitride film 107.

Next, as shown in FIG. 1(d), a capacitor electrode 109 made of a first n+ type packed crystal silicon film is formed. Further, a thermal oxide film 108° CVD silicon nitride film 107 which is a capacitor insulating film in the switching MO8FET region
．． The oxide film 106 is peeled off and removed. In this case, wet etching or chemical dry etching (CDE) using a hydrofluoric acid aqueous solution is used for the oxide film, and hot phosphoric acid or a hydrofluoric acid aqueous solution is used for the nitride film. Thereafter, a gate oxide film 110 is formed, and a gate electrode 111 . made of a second n+ type packed crystal silicon film is formed. n+ of source and drain regions
+ Impurity layers 112 and 113 are formed to complete the memory cell.

FIG. 4 shows an MI formed according to the first embodiment described above.
S capacitor and MIS formed according to conventional method
This is a comparison of dielectric strength with a capacitor. In the conventional example, the deposition temperature during silicon nitride film formation was set at 720°C.
The MIS capacitor was constructed under the same conditions as in the example except that the conditions were set at 0.degree. C., the deposition pressure at 0.3 Torr, and the flow rate ratio of ammonia and dichlorosilane at 10.

As is clear from the figure, it can be seen that the dielectric strength of this example is significantly improved compared to the conventional example.

The reason why the dielectric strength of the MIS capacitor is improved by this embodiment will be specifically explained with reference to FIG. 3. FIG. 3(a) shows the state of the silicon nitride film at the initial stage of the CVD process when nitrogen (adsorbed species) does not cover the entire surface of the underlying substrate.

Since nitrogen is physically adsorbed at this stage, it easily moves randomly on the surface due to thermal vibration. In the conventional method where the deposition temperature is high, this thermal oscillation is large;
As shown in FIG. 3(b), these particles collide with each other and gradually grow into nuclei. After that, as shown in Figure 3(c), many nuclei are formed, contact each other, and coalesce, resulting in non-uniform growth, that is, island growth, on the underground surface, resulting in extremely thin spots in the ultra-thin silicon nitride film. can. This reduces the dielectric strength.

On the other hand, in the case of this embodiment in which the deposition temperature is set low, island growth is suppressed as shown in FIG. 3(d), and even an extremely thin silicon nitride film can be obtained with sufficient uniformity.

Next, we will present experimental data when MIS capacitors similar to those in the example were formed by varying the deposition temperature and deposition rate (which are functions of temperature, pressure, and gas flow rate ratio) during silicon nitride film formation. show.

FIG. 6(a) shows the measurement of the average breakdown voltage with respect to the deposition temperature of the SiN film, with the deposition rate being changed as a parameter of 1, 2, and 4 persons/1 nl, respectively. Further, FIG. 6(b) shows the measurement of the average breakdown voltage with respect to the deposition rate of the SiN film, which was carried out at 660, 680, and 700° C., respectively, using the deposition temperature as a parameter.

From these results, the deposition temperature is 680℃ or less,
14 MV with a deposition rate of 2 Å or more
It was found that a high withstand voltage of more than / cm can be achieved.

Note that the deposition rate is preferably 10 people/sin or less. If it is faster than this, for example, about 50 thin SiN
This is because the film cannot be formed with good controllability. Further, if the deposition temperature is lower than 680° C., the deposition rate becomes too slow to be practical.

As is clear from the above data, by setting the deposition temperature to 680° C. or lower and the deposition rate to 2 people/sin or higher, an ultra-thin silicon nitride film having a practically sufficient dielectric strength can be obtained.

FIGS. 2(a) to 2(d) are cross-sectional views showing the manufacturing process of a second embodiment in which the present invention is applied to a stacked capacitor cell in a DRAM. First, as shown in FIG. 2(a), a P type (100) silicon substrate 201 with a specific resistance of 5 to 50 Ω·cm is prepared, and a field oxide film 202 is formed by selective oxidation.

After this, as shown in FIG. 2(b), the gate oxide film 20 is
3, and a gate electrode 204.3 made of a second n+ type packed crystal silicon film. By forming n-type impurity layers 205 and 206 in the source and drain regions, a switching MOSFET is formed.
form. Next, as shown in FIG. 2(c), CVD
After depositing the oxide film 207, a direct contact hole 208 is formed.
After forming, n-type polycrystalline silicon is formed on the entire surface,
Lower electrode (storage node) 2 by buttering
09 is formed.

After this, dichlorosilane and ammonia (
By the low pressure CVD method using a reaction with a flow rate ratio of 1:10),
A CVD silicon nitride film 210 with a thickness of 5 nm is formed, and a thermal oxide film 211 with a thickness of about 2 to 4 nm is further formed on the CVD silicon nitride film 210 by thermal oxidation.

Next, a memory cell is completed by forming a capacitor electrode 212 of a second n+ type packed crystal silicon film (FIG. 2(d)).

FIGS. 5(a) and 5(b) show leakage currents and dielectric breakdown voltages of a MOS capacitor with a gate oxide film formed according to the second embodiment and a MOS capacitor formed according to the conventional method, respectively. This is a comparative diagram. In the conventional example, a silicon nitride film with a thickness of 5 nm is similarly formed at a deposition temperature of 700°C, a deposition pressure of 0.3 Torr, and a flow m ratio of dichlorosilane and ammonia of 1=10, and then a silicon nitride film with a thickness of 5 nm is formed on these silicon nitride films. 2nm thick
This is the case of a MIS capacitor using an insulating film with a thermal oxide film formed thereon. As is clear from the figure, in comparison with the conventional example, in the case of this example, the leakage current is suppressed to a low level, and the dielectric strength voltage is also good.

Although the embodiments have been described with respect to the gate insulating film of DRAM, the present invention is applicable not only to the gate insulating film of DRAM but also generally to cases including a process of forming an ultra-thin silicon nitride film on a substrate. .

[Effects of the Invention] According to the present invention, a thin silicon nitride film with sufficient uniformity and flatness at the atomic level can be formed. As a result, the film itself has excellent insulating properties σ.Furthermore, when a thermal oxide film is formed on this silicon nitride film, oxidation does not progress by penetrating the underlying silicon from locally thin parts. Therefore, an extremely good two-layer structure of silicon nitride film and silicon dioxide film can be obtained.

Therefore, by using an insulating thin film having such excellent characteristics, it is possible to provide a highly reliable semiconductor device such as a DRAM.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show the DRA of the first embodiment of the present invention.
A cross-sectional view of the manufacturing process of the M cell. FIGS. 2(a) to (cl) show the DR of the second embodiment of the present invention.
FIG. 3 is a cross-sectional view of the AM cell manufacturing process. FIGS. 3(a) to 3(d) are diagrams for explaining island growth. Fig. 4 is a diagram showing the dielectric strength voltage of the capacitor insulating film in the first embodiment compared with the conventional example, and Fig. 5 (a) is a diagram comparing the leakage current of the capacitor insulating film in the second embodiment with the conventional example. 5(b) is a diagram showing the dielectric strength voltage of the capacitor insulating film in the second embodiment in comparison with that of the conventional example, and FIG. 6(a) and (b) are diagrams showing the deposition temperature and FIG. 3 is a diagram showing the results of measuring the relationship between the position rate and the average breakdown voltage of the SiN film obtained. 101...p-type silicon substrate, 102...field oxide film, 103...CVD oxide film, 104...groove. 105...n-type impurity layer, 1-06...thin oxide film. 107... Silicon nitride film, 108... Thermal oxide film. 109... Capacitor electrode, 110... Gate oxide film. 111... Gate electrode, 113.114... N-type impurity layer, 201... P-type silicon substrate, 2o2...
・Field oxide film, 203... Gate oxide film, 2o
3... Gate oxide film, 204... Gate electrode, 20
5゜206...n-type impurity layer, 207...CVD
Oxide film. 208... Direct contact hole, 2o9... Lower electrode, 210... CVD silicon nitride film, 2]1.
...Thermal oxide film. 2 2... Capacitor electrode.

Claims (1)

[Claims] In a method for manufacturing a semiconductor device including a step of forming a silicon nitride film on a semiconductor substrate by a CVD method, the step of forming the silicon nitride film is performed at a deposition temperature of 680° C.
A method for manufacturing a semiconductor device, characterized in that the process is carried out under conditions such that the temperature is below 0.degree. C. and the deposition rate is 2 Å/min or above.