JPH03280475A - Manufacture of photoelectric conversion device - Google Patents

Manufacture of photoelectric conversion device

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Publication number
JPH03280475A
JPH03280475A JP2082582A JP8258290A JPH03280475A JP H03280475 A JPH03280475 A JP H03280475A JP 2082582 A JP2082582 A JP 2082582A JP 8258290 A JP8258290 A JP 8258290A JP H03280475 A JPH03280475 A JP H03280475A
Authority
JP
Japan
Prior art keywords
layer
temperature
semiconductor layer
intrinsic semiconductor
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2082582A
Other languages
Japanese (ja)
Inventor
Hitoshi Nishio
仁 西尾
Hideo Yamagishi
英雄 山岸
Keizo Asaoka
圭三 浅岡
Yoshihisa Owada
善久 太和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanegafuchi Chemical Industry Co Ltd
Original Assignee
Kanegafuchi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanegafuchi Chemical Industry Co Ltd filed Critical Kanegafuchi Chemical Industry Co Ltd
Priority to JP2082582A priority Critical patent/JPH03280475A/en
Publication of JPH03280475A publication Critical patent/JPH03280475A/en
Pending legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To prevent a photoelectric conversion device from deteriorating in initial conversion efficiency by a method wherein a low temperature layer is formed on a first impurity semiconductor layer, an intrinsic semiconductor layer is formed at a temperature higher than the film forming temperature of the low temperature layer to serve as a high temperature layer, and a second impurity semiconductor layer is formed. CONSTITUTION:A P layer 3 of a-SiC:H is formed as thick as 250Angstrom or so on a transparent electrode 2, for instance, of SnO2 on a glass substrate 1. In succession, a low temperature I layer 4 of a-Si:H is formed as thick as 4000Angstrom on the P layer 3. The glass substrate 1 is kept at a temperature of 20 deg.C identical to that when the P layer 3 is formed. Other conditions are as follows: gas flow rate of SiH4 is 10sccm; reaction pressure is 0.3Torr; and RF power is 50mW/cm2. In succession, a high temperature layer 5 of a-Si:H is formed as thick as 1000Angstrom at a substrate temperature of 320 deg.C. An N layer 6 of micro- crystallized a-Si:H is formed on the layer 5 as thick as 300Angstrom . Lastly, a back electrode 7 of metal is formed on the N layer 6.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、太陽電池等の充電変換装置の製造方法に関し
、特に導電型の異なる2つの不純物半導体層(p層、n
層)の間に真性半導体層(i層)を設けた非単結晶半導
体からなる光電変換装置の製造方法に関する。
Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a method for manufacturing a charge conversion device such as a solar cell, and in particular, the present invention relates to a method for manufacturing a charge conversion device such as a solar cell.
The present invention relates to a method of manufacturing a photoelectric conversion device made of a non-single crystal semiconductor in which an intrinsic semiconductor layer (i-layer) is provided between layers.

[従来の技術] 非単結晶半導体からなる光電変換装置は、安定性が良く
ないといわれている。特にアモルファスシリコン太陽電
池の場合には、5taebler−Wronski効果
と呼ばれる現象がある。すなわち、p層、i層及びn層
からなる素子のうち活性層であるi層の電導度が光照射
によりしだいに低下してキャリア輸送能が下がり、素子
の変換効率が低下するのである。
[Prior Art] Photoelectric conversion devices made of non-single crystal semiconductors are said to have poor stability. Particularly in the case of amorphous silicon solar cells, there is a phenomenon called the 5taebler-Wronski effect. That is, the conductivity of the i-layer, which is the active layer, of the device consisting of the p-layer, i-layer, and n-layer gradually decreases due to light irradiation, the carrier transport ability decreases, and the conversion efficiency of the device decreases.

そこで、i層を薄膜化してこの層の電界強度を高める試
みがなされている。キャリア輸送能を予め上げておくこ
とによって素子の劣化を抑制しようとするのである。
Therefore, attempts have been made to increase the electric field strength of this layer by making the i-layer thinner. The attempt is made to suppress the deterioration of the device by increasing the carrier transport ability in advance.

また、それぞれp層、1層及びn層からなる複数の素子
をタンデム接続し、受光面側素子のi層を薄膜化する試
みもなされている。このようなタンデム構造の採用によ
り、受光面側素子はi層薄膜化の効果で劣化が抑制され
、裏面側素子は長波長光のみが照射されるために劣化が
抑制されると考えられている。
Also, attempts have been made to connect a plurality of elements each consisting of a p-layer, a single-layer, and an n-layer in tandem to thin the i-layer of the light-receiving surface side element. By adopting such a tandem structure, it is thought that the deterioration of the light-receiving side element is suppressed due to the thinning of the i-layer, and the deterioration of the back side element is suppressed because it is irradiated with only long wavelength light. .

[発明が解決しようとする課8] 上記i層薄膜化技術やタンデム構造の採用によっても太
陽電池の劣化の抑制は十分ではなく、1年問屋外使用し
たときの光電変換効率の劣化の割合が15%を上回る問
題があった。
[Issue 8 to be solved by the invention] Even with the adoption of the above-mentioned i-layer thinning technology and tandem structure, the deterioration of solar cells is not sufficiently suppressed, and the rate of deterioration of photoelectric conversion efficiency when used outdoors for one year is More than 15% of respondents had problems.

さて、p層とn層との間のi層を高温で成膜することは
劣化抑制に効果があるものと考えられる。しかしながら
、本発明者らは、太陽電池の製造過程において単にi層
を高温で成膜するだけでは初期変換効率が著しく低下す
ることを見いだした。p層上にi層を高温成膜する際に
0層中の不純物がi層内に拡散してp/i界而に面活性
層が生成し、これにより初期変換効率が低下するものと
考えられる。
Now, it is considered that forming the i-layer between the p-layer and the n-layer at a high temperature is effective in suppressing deterioration. However, the present inventors have discovered that simply forming the i-layer at a high temperature during the solar cell manufacturing process significantly reduces the initial conversion efficiency. It is thought that when the i-layer is formed on the p-layer at high temperature, impurities in the 0-layer diffuse into the i-layer and a surface active layer is generated at the p/i interface, which reduces the initial conversion efficiency. It will be done.

本発明は、導電型の異なる2つの不純物半導体層の間に
真性半導体層を設けた非単結晶半導体からなる光電変換
装置に関し、初期変換効率の低下を防止しながら劣化の
抑制を実現する製造方法を提供することを目的とする。
The present invention relates to a photoelectric conversion device made of a non-single crystal semiconductor in which an intrinsic semiconductor layer is provided between two impurity semiconductor layers of different conductivity types, and a manufacturing method that suppresses deterioration while preventing a decrease in initial conversion efficiency. The purpose is to provide

[課題を解決するための手段] 本発明に係る光電変換装置の製造方法は、第1の不純物
半導体層(p層又はn層)上にこの層の成膜温度と同等
又はこれより低い温度で真性半導体を成膜して低温i層
とし、この低温i層の成膜温度より高い温度で更に真性
半導体を成膜して高温i層としたうえで、第2の不純物
半導体層(n層又はp層)を成膜するものである。
[Means for Solving the Problems] A method for manufacturing a photoelectric conversion device according to the present invention includes forming a film on a first impurity semiconductor layer (p layer or n layer) at a temperature equal to or lower than the film formation temperature of this layer. An intrinsic semiconductor is formed into a film to form a low-temperature i-layer, an intrinsic semiconductor is further formed at a temperature higher than the film-forming temperature of the low-temperature i-layer to form a high-temperature i-layer, and then a second impurity semiconductor layer (n-layer or p layer) is formed.

高7!!i層の成膜温度は、200℃以上、400℃以
下とする。
High school 7! ! The film formation temperature of the i-layer is set to be 200° C. or higher and 400° C. or lower.

i層の膜厚については、低温i層の膜厚を300Å以上
、4000Å以下とし、かつ低温i層と高温i層との膜
厚の和を4000Å以上、7000Å以下とする。
Regarding the thickness of the i-layer, the thickness of the low-temperature i-layer is 300 Å or more and 4000 Å or less, and the sum of the thicknesses of the low-temperature i-layer and the high-temperature i-layer is 4000 Å or more and 7000 Å or less.

[作 用] 本発明に係る方法によれば、第1の不純物半導体層上に
低温i層を成膜する。後者の成膜温度は前者の成膜温度
と同等又はこれより低いから、低温i層の成膜の際に第
1の不純物半導体層から低温1層中に不純物が拡散する
ことはない。しかも、低!ii層の成膜によって表面の
耐熱性及び耐プラズマ性を向上させたうえで高温i層の
成膜を行なうから、高温1層中への不純物拡散もない。
[Function] According to the method according to the present invention, a low-temperature i-layer is formed on the first impurity semiconductor layer. Since the latter film-forming temperature is equal to or lower than the former film-forming temperature, impurities do not diffuse from the first impurity semiconductor layer into the low-temperature first layer when forming the low-temperature i layer. Moreover, it is low! Since the high temperature i layer is formed after improving the heat resistance and plasma resistance of the surface by forming the ii layer, there is no diffusion of impurities into the high temperature 1 layer.

したがって、初期変換効率の低下が防止できる。Therefore, a decrease in initial conversion efficiency can be prevented.

また、高if層は光照射を受けてもキャリア輸送能が安
定しており、劣化が抑制される。
Further, the high if layer has stable carrier transport ability even when exposed to light irradiation, and deterioration is suppressed.

[実施例] 第1図は、本発明の実施例に係る方法で製造した有効面
積1.0cm2 (1,0cmX1゜Ocm)の太陽電
池の断面図である。ただし、各゛1′−導体層の成膜に
は平行平板容量結合型グロー放電装置を使用するのが適
当である。
[Example] FIG. 1 is a cross-sectional view of a solar cell with an effective area of 1.0 cm 2 (1.0 cm×1° Ocm) manufactured by a method according to an example of the present invention. However, it is appropriate to use a parallel plate capacitively coupled glow discharge device for forming each 1'-conductor layer.

ガラス基板(1)上の例えばS n O2からなる透明
電極(2)の上に、まずa−3iC:Hからなるp層(
3)を250人成膜する。グロー放電装置に供給するガ
ス流量は、SiH4が5scc m s CH4が15
 s c cms B2 Ha (1000ppml(
2希釈品)が15secm%H2が50secmである
。他の条件は、反応圧力1、OTo r r、基板温度
200℃、RFパワー50mW/cm2である。
First, a p layer (made of a-3iC:H) (
3) will be deposited by 250 people. The gas flow rate supplied to the glow discharge device is 5 scc m s for SiH4 and 15 m s for CH4.
sc cms B2 Ha (1000ppml(
2 dilution product) is 15 seconds and %H2 is 50 seconds. Other conditions were reaction pressure 1, OTorr, substrate temperature 200° C., and RF power 50 mW/cm 2 .

次に、p層(3)上にa−8i:Hからなる低温1層(
4)を4000人成膜する。基板温度は、p層(3)の
成膜の場合と同じ200℃である。
Next, a low-temperature single layer (
4) will be deposited by 4,000 people. The substrate temperature is 200° C., which is the same as in the case of forming the p-layer (3).

他の成膜条件は、S t H4のガス流m 10 s 
ccm、反応圧力0.3To r r、RFパワー50
 m W / c m 2である。
Other film forming conditions were S t H4 gas flow m 10 s
ccm, reaction pressure 0.3Torr, RF power 50
mW/cm2.

続いてa−Si:Hからなる膜厚100o人の高温i層
(5)を基板温度320”Cで成膜する。
Subsequently, a high-temperature i-layer (5) made of a-Si:H and having a thickness of 100 μm is formed at a substrate temperature of 320″C.

他の成膜条件は、低温i層(4)の場合と同じである。Other film forming conditions are the same as for the low temperature i-layer (4).

この高温i層(5)の上に、微結晶化したa−Si:H
からなるn層(6)を300人成膜する。
On top of this high-temperature i-layer (5), microcrystalline a-Si:H
300 people deposited an n-layer (6) consisting of:

ガス流量は、S iH4が5sccm、PH3(100
0ppmH2希釈品)が101005c s H2が2
00 s e cmである。他の条件は、反応圧力1.
0Torr、基板温度200℃、RFパワー500 m
W/ c m2である。
The gas flow rate was 5 sccm for SiH4 and 5 sccm for PH3 (100 sccm).
0ppmH2 diluted product) is 101005c s H2 is 2
00 sec cm. Other conditions were reaction pressure 1.
0Torr, substrate temperature 200℃, RF power 500m
W/cm2.

最後に金属からなる裏面電極(7)をn層(8)上に成
膜する。
Finally, a back electrode (7) made of metal is formed on the n-layer (8).

第2図は、以上に説明した方法で製造した太陽電池の初
期外部特性(電流電圧特性)を示すグラフである。測定
には、AM−1,100mW/Cm2のソーラーシミュ
レート光を用いた。
FIG. 2 is a graph showing the initial external characteristics (current-voltage characteristics) of the solar cell manufactured by the method described above. For the measurement, solar simulated light of AM-1, 100 mW/Cm2 was used.

特性値は、開放電圧0.858volLs 、短絡型流
16.06mA/cm  %FF (フィルファクタ)
60.22%、光電変換効率8.302%である。1年
問屋外使用したときの充電変換効率の劣化の割合は10
%未満であって、従来に比べて大幅に劣化が抑制されて
いる。
Characteristic values are open circuit voltage 0.858volLs, short circuit current 16.06mA/cm %FF (fill factor)
The photoelectric conversion efficiency was 60.22%, and the photoelectric conversion efficiency was 8.302%. The rate of deterioration of charging conversion efficiency when used outdoors for one year is 10
%, which significantly suppresses deterioration compared to conventional methods.

第3図は太陽電池の比較例を示す断面図である。a−5
t:Hからなる膜厚5000人のi層全体(5)を基板
温度320℃の高温で成膜した点以外は上記実施例と同
一である。第4図は、この比較例の場合の初期外部特性
を示す。特性Allll性は上記実施例の場合と同一で
ある。特性値は、開放電圧Q、 8Q 6volts 
、短絡電流15.58mA/cm   FF47.82
%、光電変換効率6.014%である。
FIG. 3 is a sectional view showing a comparative example of a solar cell. a-5
This example is the same as the above example except that the entire i-layer (5) consisting of t:H and having a thickness of 5000 layers was formed at a high substrate temperature of 320°C. FIG. 4 shows the initial external characteristics of this comparative example. All characteristics are the same as in the above embodiment. Characteristic values are open circuit voltage Q, 8Q 6volts
, short circuit current 15.58mA/cm FF47.82
%, and the photoelectric conversion efficiency was 6.014%.

両特性の比較から、高温i層(5)の成膜前に低温i層
(4)を成膜することによって、FF等の初期外部特性
が改善されることがわかる。特に初期変換効率の大幅な
改善が認められる。
A comparison of both characteristics shows that initial external characteristics such as FF are improved by forming the low temperature i-layer (4) before forming the high-temperature i-layer (5). In particular, a significant improvement in initial conversion efficiency is observed.

p層(3)の成膜温度は、50℃以上、400℃以下が
望ましい。低温i層(4)の成膜温度は、p層成脱湿度
と同等又はこれより低いことが必要であるが、100℃
以上、300℃以下が望ましく、更に好ましくは150
℃以上、250℃以下である。高温i層(5)の成膜温
度は、低温i層(4)の成膜温度より高く、200℃以
上、400℃以下であることが必要である。
The film formation temperature of the p layer (3) is preferably 50°C or higher and 400°C or lower. The film formation temperature of the low-temperature i-layer (4) needs to be equal to or lower than the p-layer formation/desorption humidity, but it is 100°C.
Above, the temperature is preferably 300°C or less, more preferably 150°C or less.
℃ or higher and 250℃ or lower. The film-forming temperature of the high-temperature i-layer (5) is higher than the film-forming temperature of the low-temperature i-layer (4), and needs to be 200°C or more and 400°C or less.

p層(3)及びn層(6)の膜厚は、80Å以上、30
0Å以下が適当である。低温i層(4)の膜厚は300
Å以上、4000Å以下である必要があるが、好ましく
は500Å以上、4000Å以下である。高温i層(5
)の膜厚は、低温i層(4)の膜厚との和が4000Å
以上、7000Å以下となる範囲で決定する必要がある
The film thickness of the p layer (3) and n layer (6) is 80 Å or more, 30 Å
A suitable thickness is 0 Å or less. The film thickness of the low temperature i-layer (4) is 300
The thickness needs to be 500 Å or more and 4000 Å or less, preferably 500 Å or more and 4000 Å or less. High temperature i-layer (5
), the sum of the thickness of the low temperature i-layer (4) is 4000 Å.
As mentioned above, it is necessary to determine the thickness within a range of 7000 Å or less.

なお、光電変換装置を構成する非単結晶半導体としては
S iSS t Cs S t N %S IG e 
5SiSn等の水素化合金(例えば実施例でp層(3)
に使用したa−9iC:Hやi層(4,5)に使用した
a−3i:H)やフッ素化合金等の一般に光起電力素子
に使用されるアモルファスシリコン系半導体をあげるこ
とができる。上記実施例においてn層(6)に使用した
ような微結晶を含むアモルファス半導体でも良いし、多
結晶半導体でも良い。受光面側には、上記実施例のよう
にa−5iC:Hに周期律表mb族の元素をドープした
p層(3)を配するのが最も好適である。ただし、受光
面側にn層を配置しても良く、この場合のn層には周期
律表vb族の元素をドープしたa−SiC:Hを使用す
るのが最適である。
In addition, as a non-single crystal semiconductor constituting a photoelectric conversion device, S iSS t Cs S t N %S IG e
Hydrogenated alloy such as 5SiSn (for example, p layer (3) in the example)
Examples include amorphous silicon-based semiconductors commonly used in photovoltaic devices, such as a-9iC:H used for the i-layer (4, 5), a-3i:H) used for the i-layer (4, 5), and fluorinated alloys. It may be an amorphous semiconductor containing microcrystals, such as the one used for the n-layer (6) in the above embodiment, or a polycrystalline semiconductor. It is most preferable to arrange, on the light-receiving surface side, a p-layer (3) in which a-5iC:H is doped with an element of group MB of the periodic table, as in the above embodiment. However, an n-layer may be arranged on the light-receiving surface side, and in this case, it is optimal to use a-SiC:H doped with an element of group Vb of the periodic table.

p層(3)とi層(4,5)との間又はn層(6)と1
層(4,5)との間にi層(4,5)に向かって光学的
禁制帯幅及び不純物濃度が段階的に減少する層を設けて
も良い。この不純物半導体層の膜厚は、30Å以上、5
00Å以下が適当であり、より好ましくは50Å以上、
200Å以下である。
Between the p layer (3) and the i layer (4, 5) or between the n layer (6) and 1
A layer whose optical forbidden band width and impurity concentration gradually decrease toward the i-layer (4, 5) may be provided between the layers (4, 5). The film thickness of this impurity semiconductor layer is 30 Å or more, 5
00 Å or less is suitable, more preferably 50 Å or more,
It is 200 Å or less.

受光面側の不純物半導体層(p層(3)又はn層)と透
明電極(2)との間に、両者間の接触抵抗を下げる目的
で、受光面側不純物半導体層と同じ導電型の高濃度ドー
ピング層を設けても良い。この高濃度ドーピング層の膜
厚は、5Å以上、100Å以下が適当であり、より好ま
しくは10Å以上、50Å以下である。不純物濃度は、
受光面側不純物半導体層の5倍以上、50倍以下が適当
である。
In order to reduce the contact resistance between the impurity semiconductor layer (p-layer (3) or n-layer) on the light-receiving surface side and the transparent electrode (2), a high-conductivity layer of the same conductivity type as the impurity semiconductor layer on the light-receiving surface side is added. A concentration doping layer may also be provided. The thickness of this heavily doped layer is suitably 5 Å or more and 100 Å or less, more preferably 10 Å or more and 50 Å or less. The impurity concentration is
Appropriately, it is 5 times or more and 50 times or less as large as the impurity semiconductor layer on the light-receiving surface side.

それぞれp層、i層及びn層からなる2素子をタンデム
接続した2段タンデム構造を採用する場合には、受光面
より遠い側の素子について本発明を適用するのが効果的
である。
When employing a two-stage tandem structure in which two elements each consisting of a p-layer, an i-layer, and an n-layer are connected in tandem, it is effective to apply the present invention to the elements on the side farther from the light-receiving surface.

[発明の効果] 以上に説明したように、本発明に係る製造方法は、導電
型の異なる2つの不純物半導体層の間に真性半導体層を
設けた非単結晶半導体からなる光電変換装置の製造方法
であって、第1の不純物半導体層上にこの層の成膜温度
と同等又はこれより低い温度で真性半導体を成膜して低
温真性半導体層とし、この低温真性半導体層の成膜温度
より高い温度で更に真性半導体を成膜して高温真性半導
体層としたうえで、第2の不純物半導体層を成膜するも
のであるから、光電変換装置の初期変換効率の低下を防
止しながらその劣化を抑制することができる。したがっ
て本発明によれば高効率かつ高信頓性の光電変換装置を
製造することができる。
[Effects of the Invention] As explained above, the manufacturing method according to the present invention is a method for manufacturing a photoelectric conversion device made of a non-single crystal semiconductor in which an intrinsic semiconductor layer is provided between two impurity semiconductor layers of different conductivity types. A low-temperature intrinsic semiconductor layer is formed by forming an intrinsic semiconductor on the first impurity semiconductor layer at a temperature equal to or lower than the film-forming temperature of this layer, and the film-forming temperature is higher than the film-forming temperature of the low-temperature intrinsic semiconductor layer. Since an intrinsic semiconductor is further formed at high temperature to form a high-temperature intrinsic semiconductor layer, and then a second impurity semiconductor layer is formed, it is possible to prevent the initial conversion efficiency of the photoelectric conversion device from deteriorating while preventing its deterioration. Can be suppressed. Therefore, according to the present invention, a highly efficient and highly reliable photoelectric conversion device can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例に係る方法で製造した太陽電池
の断面図、第2図は前図の太vA1a池の初期外部特性
を示すグラフ、第3図は太陽電池の比較例を示す断面図
、第4図は前図の太陽電池の初期外部特性を示すグラフ
である。 符号の説明 1・・・ガラス基板、2・・・透明電極、3・・・p層
、4・・・低温i層、5・・・高温i層、6・・・n層
、7・・・裏面電極。
Fig. 1 is a cross-sectional view of a solar cell manufactured by the method according to an embodiment of the present invention, Fig. 2 is a graph showing the initial external characteristics of the thick vA1a cell shown in the previous figure, and Fig. 3 is a comparative example of the solar cell. The cross-sectional view, FIG. 4, is a graph showing the initial external characteristics of the solar cell shown in the previous figure. Explanation of symbols 1... Glass substrate, 2... Transparent electrode, 3... P layer, 4... Low temperature i layer, 5... High temperature i layer, 6... N layer, 7...・Back electrode.

Claims (1)

【特許請求の範囲】 1、導電型の異なる2つの不純物半導体層の間に真性半
導体層を設けた非単結晶半導体からなる光電変換装置の
製造方法であって、第1の不純物半導体層上にこの層の
成膜温度と同等又はこれより低い温度で真性半導体を成
膜して低温真性半導体層とし、この低温真性半導体層の
成膜温度より高い温度で更に真性半導体を成膜して高温
真性半導体層としたうえで、第2の不純物半導体層を成
膜する製造方法。 2、高温真性半導体層の成膜温度を200℃以上、40
0℃以下とする請求項1記載の製造方法。 3、低温真性半導体層の膜厚を300Å以上、4000
Å以下とし、低温真性半導体層と高温真性半導体層との
膜厚の和を4000Å以上、7000Å以下とする請求
項1又は2に記載の製造方法。
[Claims] 1. A method for manufacturing a photoelectric conversion device made of a non-single crystal semiconductor in which an intrinsic semiconductor layer is provided between two impurity semiconductor layers of different conductivity types, the method comprising: An intrinsic semiconductor is deposited at a temperature equal to or lower than the deposition temperature of this layer to form a low-temperature intrinsic semiconductor layer, and an intrinsic semiconductor is further deposited at a temperature higher than the deposition temperature of this low-temperature intrinsic semiconductor layer to form a high-temperature intrinsic semiconductor layer. A manufacturing method in which a second impurity semiconductor layer is formed after forming a semiconductor layer. 2. The film-forming temperature of the high-temperature intrinsic semiconductor layer is 200°C or higher, 40°C.
The manufacturing method according to claim 1, wherein the temperature is 0°C or lower. 3. The thickness of the low-temperature intrinsic semiconductor layer is 300 Å or more, 4000 Å or more.
3. The manufacturing method according to claim 1, wherein the total thickness of the low-temperature intrinsic semiconductor layer and the high-temperature intrinsic semiconductor layer is 4000 Å or more and 7000 Å or less.
JP2082582A 1990-03-28 1990-03-28 Manufacture of photoelectric conversion device Pending JPH03280475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2082582A JPH03280475A (en) 1990-03-28 1990-03-28 Manufacture of photoelectric conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2082582A JPH03280475A (en) 1990-03-28 1990-03-28 Manufacture of photoelectric conversion device

Publications (1)

Publication Number Publication Date
JPH03280475A true JPH03280475A (en) 1991-12-11

Family

ID=13778478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2082582A Pending JPH03280475A (en) 1990-03-28 1990-03-28 Manufacture of photoelectric conversion device

Country Status (1)

Country Link
JP (1) JPH03280475A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566594B2 (en) 2000-04-05 2003-05-20 Tdk Corporation Photovoltaic element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566594B2 (en) 2000-04-05 2003-05-20 Tdk Corporation Photovoltaic element
US6960718B2 (en) 2000-04-05 2005-11-01 Tdk Corporation Method for manufacturing a photovoltaic element

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