JPH03280497A - Electronic circuit board - Google Patents

Electronic circuit board

Info

Publication number
JPH03280497A
JPH03280497A JP2081564A JP8156490A JPH03280497A JP H03280497 A JPH03280497 A JP H03280497A JP 2081564 A JP2081564 A JP 2081564A JP 8156490 A JP8156490 A JP 8156490A JP H03280497 A JPH03280497 A JP H03280497A
Authority
JP
Japan
Prior art keywords
resin
resin layer
layer
electronic circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2081564A
Other languages
Japanese (ja)
Other versions
JP2693618B2 (en
Inventor
Masayuki Arakawa
雅之 荒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba AVE Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba AVE Co Ltd filed Critical Toshiba Corp
Priority to JP2081564A priority Critical patent/JP2693618B2/en
Publication of JPH03280497A publication Critical patent/JPH03280497A/en
Application granted granted Critical
Publication of JP2693618B2 publication Critical patent/JP2693618B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/225—Correcting or repairing of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は電子回路基板に関し、特に、高密度化を向上さ
せるために多層構造を採用した電子回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic circuit board, and particularly to an electronic circuit board employing a multilayer structure to improve density.

（従来の技術） 近年、オーディオ・ビデオ等の電子機器は小形化が進ん
でおり、これ°に伴いプリント配線板等の電子回路基板
においては高密度化が要求されている。このため、プリ
ント配線板を２段重ねとする方法を採用することがある
。(Prior Art) In recent years, electronic devices such as audio and video devices have been becoming smaller and smaller, and as a result, electronic circuit boards such as printed wiring boards are required to have higher density. For this reason, a method of stacking printed wiring boards in two layers is sometimes adopted.

第３図はこのような従来の電子回路基板を示す正面図で
ある。FIG. 3 is a front view showing such a conventional electronic circuit board.

プリント配線板１．２上には夫々チップ部品３及びリー
ド部品４を実装している。プリント配線板１．２は上下
に配置し、フレキシブル配線板５によって電気的に接続
している。なお、フレキシブル配線板５に代えてコネク
タを使用してプリント配線板１，２を接続することもあ
る。これにより、＾密度実装を可能にしている。A chip component 3 and a lead component 4 are mounted on the printed wiring board 1.2, respectively. Printed wiring boards 1.2 are arranged one above the other and are electrically connected by a flexible wiring board 5. Note that, instead of the flexible wiring board 5, a connector may be used to connect the printed wiring boards 1 and 2. This enables ^density mounting.

しかし、この方法ではプリント配線板１．２上の各チッ
プ部品３及びリード部品４からフレキシブル配線板５の
端子６まで配線（図示せず）を弓回さねばならない。プ
リント配線板１，２の端子６とは反対側の端部に配置さ
れた部品も端子６まで配線を引回すことになり、配線の
設計の自由度が低く、実装密度の向上が阻害されてしま
う。However, in this method, wiring (not shown) must be routed from each chip component 3 and lead component 4 on the printed wiring board 1.2 to the terminal 6 of the flexible wiring board 5. Components placed on the opposite ends of the printed wiring boards 1 and 2 from the terminals 6 also have to be routed to the terminals 6, which reduces the degree of freedom in wiring design and impedes improvements in packaging density. Put it away.

そこで、上下の基板の部品を接続するコンタクト層を介
挿した多層構造を採用することもある。Therefore, a multilayer structure may be adopted in which a contact layer is inserted to connect the components of the upper and lower boards.

第４図はこのような従来の電子回路基板を示す説明図で
ある。FIG. 4 is an explanatory diagram showing such a conventional electronic circuit board.

プリント配線板１１．１２上の端部には夫々ダム枠１３
ａ、　１３ｂを形成している。プリント基板１１．１２
上には夫々回路部品１４ａ、１４ｂを配設しており、回
路部品１４ａ、　１４ｂは夫々プリント配線板１１．１
２上に実装された接続用ビン１５ａ、１５ｂに電気的に
接続している。プリント配線板１１．１２上のダム枠１
３ａ、　１３ｂ内には、夫々エポキシ等の樹脂１６ａ。Dam frames 13 are installed at the ends of the printed wiring boards 11 and 12, respectively.
a, forming 13b. Printed circuit board 11.12
Circuit components 14a and 14b are arranged on the printed wiring board 11.1, respectively.
It is electrically connected to connection bins 15a and 15b mounted on 2. Dam frame 1 on printed wiring board 11.12
Resin 16a such as epoxy is in each of 3a and 13b.

１６ｂ（梨地部）を埋め込んで硬化している。樹脂１６
ａ、　１６ｂの表面は平滑化しており、各表面に夫々接
続用ピン１５ａ、１５ｂを一接続するための厚膜導体１
７ａ、　１７ｂを再配線層としてスクリーン印刷によっ
て形成し硬化している。厚膜導体１７ａ、　１７ｂとし
ては樹脂系Ａｇペースト等が採用される。なお、樹脂１
６ａ、１６ｂは硬化後において、厚膜導体１７ａ　、１
７ｂを形成のためのスクリーン印刷に絶え得る十分な硬
度を有する必要がある。16b (matte part) is embedded and hardened. resin 16
The surfaces of a and 16b are smoothed, and a thick film conductor 1 is provided on each surface for connecting connection pins 15a and 15b, respectively.
7a and 17b are formed as redistribution layers by screen printing and cured. A resin-based Ag paste or the like is used as the thick film conductors 17a and 17b. In addition, resin 1
6a and 16b are thick film conductors 17a and 1 after curing.
It is necessary to have sufficient hardness to withstand screen printing for forming 7b.

このようにして構成された実装基板１８ａ、　１８ｂは
、樹脂１６ａ、　１６ｂ形成側を対向させた状態で異方
性導電膜１９（斜線部）等を介挿して接続した多層構造
となっている。接続用ピン１５ａ、　１５ｂ同士は厚膜
導体１７ａ、　１７ｂの対向した部分の異方性導電膜１
９によって電気的に接続される。これにより、各回路部
品１４ａ、　１４ｂからの配線は近傍に実装された接続
用ビン１５ａ、１５ｂまで行えばよく、配線設計の自由
度を向上させて更に一層高密度化が可能になっている。The mounting boards 18a and 18b constructed in this manner have a multilayer structure in which the resin 16a and 16b forming sides are opposed to each other and connected through an anisotropic conductive film 19 (shaded area) and the like. The connecting pins 15a and 15b are connected to the anisotropic conductive film 1 of the opposing portions of the thick film conductors 17a and 17b.
It is electrically connected by 9. As a result, wiring from each circuit component 14a, 14b only needs to be carried out to connection bins 15a, 15b mounted nearby, which improves the degree of freedom in wiring design and enables even higher density.

ところで、前述したように、厚膜導体１７ａ。By the way, as mentioned above, the thick film conductor 17a.

１７ｂをスクリーン印刷するために、樹脂１６ａ。Resin 16a to screen print 17b.

１６ｂの硬化後の硬度を高くする必要がある。ところが
、例えばショア硬度が約９０以上の硬い樹脂を採用する
と、樹脂の熱膨脹係数及び硬化収縮率が大きいことから
、樹脂１６ａ　、　１６ｂの埋め込み及び硬化工程にお
いて、第５図に示すように、プリント基板１１．１２に
そりが発生してしまうことがある。（うづると、実装さ
れた回路部品１４ａ、１４ｂにストレスが加わり部品１
４ａ、１４ｂが破壊されてしまうことがあり、また、ス
クリーン印刷による再配線層の形成が不可能となってし
まうことがあるという問題があった。It is necessary to increase the hardness of 16b after curing. However, if a hard resin with a Shore hardness of about 90 or more is used, the thermal expansion coefficient and curing shrinkage of the resin are large, so in the process of embedding and curing the resins 16a and 16b, as shown in FIG. 11.12 Warpage may occur. (When it swells, stress is applied to the mounted circuit components 14a and 14b, causing component 1
4a and 14b may be destroyed, and it may become impossible to form a rewiring layer by screen printing.

なお、ショア硬度が約７０以下の柔らかい樹脂を採用し
た場合には、そりは発生しないが、スクリーン印刷によ
る再配線層の形成が困難となる。Note that when a soft resin with a Shore hardness of about 70 or less is used, warping does not occur, but it becomes difficult to form a rewiring layer by screen printing.

また、再配線層を形成することができた場合でも、異方
性導電膜１９による接続工程等において再配線層に断線
が生じゃ覆いという問題があった。Further, even if the rewiring layer can be formed, there is a problem in that the rewiring layer is covered with disconnections during the connection process using the anisotropic conductive film 19 and the like.

（発明が解決しようとする課題） このように、上述した従来の電子回路基板においては、
ダム枠内に埋め込む樹脂としては比較的硬度が高いもの
を使用する必要があり、樹脂の埋め込み及び硬化工程に
おいて基板にそりが発生し、回路部品が破壊されること
があり、また、再配線層の形成が困難となってしまうこ
とがあるという問題点があった。(Problems to be Solved by the Invention) As described above, in the conventional electronic circuit board described above,
It is necessary to use a relatively hard resin to be embedded in the dam frame, and the process of embedding and curing the resin may cause warpage on the board and damage the circuit components. There is a problem in that it may be difficult to form.

本発明はかかる問題点に鑑みてなされたしのであって、
」分な硬度を有してｓｌｌ上上再配線層を形成すること
を可能にすると共に、基板にそりが発生してしまうこと
を防止することができる電子回路基板を提供づることを
目的とする。The present invention was made in view of such problems, and includes:
It is an object of the present invention to provide an electronic circuit board that allows a rewiring layer to be formed on an SLL with sufficient hardness and that can prevent warpage from occurring on the board.

［発明の構成］ （ａ！！！題を解決するための手段） 本発明に係る電子回路基板は、実装部品及びこの実装部
品に接続される接続ピンとを実装し端部にダム枠を設け
るプリント配線板と、前記ダム枠内で前記実装部品を埋
め込むように形成づる第１の樹脂層と、この第１の樹脂
層よりも高い硬度を有し前記ダム枠内の前記第１の樹脂
層上に形成する第２の樹脂層と、この第２の樹脂層上に
スクリーン印刷する配線層と、によって構成される複数
の実装基板と、これらの実装基板相互間に形成し前記各
実装基板の配線層同士を接続づるコンタクト層とを具備
したものである。[Structure of the Invention] (Means for Solving Problem A!!!) The electronic circuit board according to the present invention is a printed circuit board having a mounted component and a connecting pin connected to the mounted component, and having a dam frame at the end. a wiring board, a first resin layer formed within the dam frame so as to embed the mounted component, and a first resin layer having a higher hardness than the first resin layer and on the first resin layer within the dam frame; a plurality of mounting boards formed of a second resin layer formed on the substrate, a wiring layer screen printed on the second resin layer, and wiring of each mounting board formed between these mounting boards; It is equipped with a contact layer that connects the layers.

（作用） 本発明においては、第１の樹脂層を低硬度の樹脂によっ
て形成する。この第１の樹脂層によって、高硬度の第２
の樹脂層の硬化時の収縮及び熱膨脹を相殺することがで
きる。これにより、第１及び第２の樹脂層の硬化工程に
おいて実装基板にそりが発生することを防止している。(Function) In the present invention, the first resin layer is formed of a low hardness resin. This first resin layer creates a highly hard second resin layer.
The shrinkage and thermal expansion of the resin layer during curing can be offset. This prevents warpage from occurring on the mounting board during the curing process of the first and second resin layers.

また、第２の樹脂層が高硬度であるので、スクリーン印
刷が容易であり、再配線層の形成が可能となっている。Furthermore, since the second resin layer has high hardness, screen printing is easy and a rewiring layer can be formed.

また、再配線層形成後において断線が発生することはな
い。Moreover, disconnection does not occur after the rewiring layer is formed.

（実施例） 以下、図面に基づいて本発明の実施例を詳細に説明する
。第１図は本発明に係る電子回路基板の一実施例を示す
説明図である。(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 is an explanatory diagram showing one embodiment of an electronic circuit board according to the present invention.

本実施例の電子回路基板３０は、実装基板２８ａ。The electronic circuit board 30 of this embodiment is the mounting board 28a.

２８ｂがコンタクト層２９を介して接続された多層構造
となっている。コンタクト層２９は異方性導電膜によっ
て構成しており、実装基板２８ａ、２８ｂの再配線層２
７ａ、　２７ｂをコンタクト層２９において一部分で相
互に対向して配置することにより、実装基板２８ａ、２
８ｂ相互の電気的な接続を行うようになっている。28b are connected via a contact layer 29 to form a multilayer structure. The contact layer 29 is made of an anisotropic conductive film, and is similar to the rewiring layer 2 of the mounting substrates 28a and 28b.
By arranging 7a and 27b so as to partially face each other in the contact layer 29, the mounting substrates 28a and 2
8b are electrically connected to each other.

実装基板２８ａ、２８ｂは、夫々プリント配線板２１ａ
、２１ｂに多層構造を可能にづる樹脂層を形成したもの
である。プリント配線板２１ａ、２Ｉｂ上には夫々実装
部品２２ａ、２２ｂを配設しており、回路部品２２ａ、
２２ｂは夫々プリント配線板２１ａ、２１ｂ上に実装さ
れた接続用ピン２３ａ、２３ｂに電気的に接続している
。プリント配線板２１ａ、２１ｂの端部には夫々ダム枠
２４ａ、２４ｂを形成している。ダム枠り４ａ内には第
１の樹脂層２５ａと第２の樹脂層２６ａとを形成してお
り、回路部品２２ａは第１の樹脂＠２５ａ内に埋め込ま
れている。一方、プリント配線板２１ｂ上のダム枠２４
ｂ内には、第１の樹脂層２５ｂと第２の樹脂層２６ｂと
を形成しており、回路部品２２ｂは第１の樹脂層２５ｂ
内に埋め込まれている。Each of the mounting boards 28a and 28b is a printed wiring board 21a.
, 21b is provided with a resin layer to enable a multilayer structure. Mounted components 22a and 22b are arranged on printed wiring boards 21a and 2Ib, respectively, and circuit components 22a,
22b are electrically connected to connection pins 23a and 23b mounted on printed wiring boards 21a and 21b, respectively. Dam frames 24a and 24b are formed at the ends of the printed wiring boards 21a and 21b, respectively. A first resin layer 25a and a second resin layer 26a are formed in the dam frame 4a, and the circuit component 22a is embedded in the first resin @25a. On the other hand, the dam frame 24 on the printed wiring board 21b
A first resin layer 25b and a second resin layer 26b are formed in the inside of b, and the circuit component 22b is formed in the first resin layer 25b.
embedded within.

ダム枠２４ａ、２４ｂ内の大部分を占有する第１の樹脂
層２５ａ、２５ｂは、例えばショア硬度が約２０の柔ら
かい樹脂によって形成しており、第２の樹脂層２６ａ、
２６ｂはショア硬度が９０以上の硬い樹脂によって形成
している。第２の樹脂層２６ａ。The first resin layers 25a, 25b occupying most of the inside of the dam frames 24a, 24b are made of soft resin having a Shore hardness of about 20, for example, and the second resin layers 26a,
26b is made of hard resin having a Shore hardness of 90 or more. Second resin layer 26a.

２６ｂの表面は平滑化しており、各表面には夫々接続用
ピン２３ａ、２３ｂに接続された状態で樹脂系へ〇ペー
スト等の再配線層２７ａ、２７ｂを所定の広さに形成し
ている。なお、前述したように、対向する再配線層２７
ａ　、　２７ｂはコンタクト層２９によって相互に電気
的に接続されるようになっている。The surface of 26b is smoothed, and rewiring layers 27a and 27b made of resin-based paste or the like are formed in a predetermined width on each surface while being connected to connection pins 23a and 23b, respectively. Note that, as described above, the opposing redistribution layer 27
a and 27b are electrically connected to each other by a contact layer 29.

このように構成された実施例においては、第２の樹脂層
２６ａ、２６ｂの硬度が高いことから、この表面におい
てスクリーン印刷が可能である。これにより、再配線層
２７ａ、　２７ｂをスクリーン印刷によって容易に形成
可能にしている。また、ダム枠２４ａ、２４ｂ内の大部
分には硬度が低い第２の樹脂＠２５ａ、　２５ｂを形成
している。すなわち、第２の樹脂層２５ａ、２５ｂの熱
膨脹係数及び硬化収縮率は小さく、第２の樹脂層２５ａ
、２．５ｂの硬化工程によって、プリント配線板２１ａ
、２１ｂがそってしまうことはない。In the embodiment configured in this manner, since the second resin layers 26a and 26b have high hardness, screen printing is possible on these surfaces. This allows the rewiring layers 27a and 27b to be easily formed by screen printing. Furthermore, a second resin @25a, 25b with low hardness is formed in most of the insides of the dam frames 24a, 24b. That is, the coefficient of thermal expansion and the curing shrinkage rate of the second resin layers 25a and 25b are small, and the second resin layer 25a
, 2.5b, the printed wiring board 21a
, 21b will not warp.

次に、第２図を参照して第１図の電子回路基板３０の製
造方法を説明する。第２図（ａ）乃至（ｆ）は電子回路
基板の製造方法を■程順に示１説明図である。なお、実
装基板２８ａ、２８ｂの製造方法は同一であるの゛Ｃ１
第２図では一方の実装基板２８ｂについてのみ小してい
る。Next, a method for manufacturing the electronic circuit board 30 shown in FIG. 1 will be explained with reference to FIG. FIGS. 2(a) to 2(f) are explanatory diagrams showing a method for manufacturing an electronic circuit board in order of steps (1). Note that the manufacturing methods of the mounting boards 28a and 28b are the same.C1
In FIG. 2, only one mounting board 28b is made smaller.

先ず、第２図（ａ＞に示ずように、プリント配線板２１
ｂ上に実装部品２２ｂを半田付Ｃ）等によって実装づる
と同時に、これらの実装部品２２ｂを接続するための接
東ピン２３ｂを半田付は等によって実装づる。First, as shown in FIG. 2 (a), the printed wiring board 21
At the same time, the mounting parts 22b are mounted on the mounting parts 22b by soldering C), and at the same time, the contact pins 23b for connecting these mounting parts 22b are mounted by soldering or the like.

次に、第２（ｂ）に示すように、プリント配線板２１ｂ
上の端部に、実装部品２２ｂを埋め込むのためのガラス
エポキシ樹脂等のダム枠２４ｂを接着して立設する。次
いで、第２図（Ｃ）に示すように、硬化時のシ」ア硬度
が約２０となる弾性エポキシ樹脂等をダム枠２４ｂ内に
実装部品２２ｂが完全に覆われるまで流し込み、硬化さ
せて第１の樹脂層２５ｂを形成づる。なお、この場合に
は、棺続ピン２３ｂの上端側を第１の樹脂層２５ｂから
露出させると共に、ダム枠２４ｂ内に樹脂を流し込む余
裕を残しておく。Next, as shown in 2nd (b), the printed wiring board 21b
A dam frame 24b made of glass epoxy resin or the like for embedding the mounted component 22b is adhered and erected at the upper end. Next, as shown in FIG. 2(C), an elastic epoxy resin or the like having a sear hardness of approximately 20 when cured is poured into the dam frame 24b until the mounted component 22b is completely covered, and cured. 1 resin layer 25b is formed. In this case, the upper end side of the coffin connecting pin 23b is exposed from the first resin layer 25b, and a margin is left for pouring the resin into the dam frame 24b.

第１の樹脂層２５ｂが硬化した後に、第２図（ｄ）に示
すように、ダム枠２４ｂ内の第１の樹脂層２５ｂ上に硬
化時のショア硬痕が９０以上の■ボキシ樹脂等を流し込
み、硬化させて第２の樹脂層２６ｂを形成する。なお、
第１の樹脂層２５ｂ及び第２の樹脂層２６ｂを同系の樹
脂で形成することにより、第１及び第２の樹脂層２５ｂ
、２６ｂ相互間の密着強度を向上させている。また、こ
の場合においても、接続ピン２３の上端側は第２の樹脂
層２６ｂから露出した状態となっている。After the first resin layer 25b is cured, as shown in FIG. 2(d), a boxy resin or the like with hard Shore marks of 90 or more during curing is applied to the first resin layer 25b inside the dam frame 24b. The second resin layer 26b is formed by pouring and curing. In addition,
By forming the first resin layer 25b and the second resin layer 26b with the same type of resin, the first and second resin layers 25b
, 26b is improved. Also in this case, the upper end side of the connection pin 23 is exposed from the second resin layer 26b.

次に、第２図（ｅ）に示すように、第２の樹脂１ｉ２６
ｂの表面をラッピング等によって平滑化する。Next, as shown in FIG. 2(e), the second resin 1i26
The surface of b is smoothed by lapping or the like.

次いで、第２図（ｆ）に示ずように、平滑された第２の
樹脂層２６ｂの表面に、樹脂系Ａｇペースト等をスクリ
ーン印刷し、硬化して再配線層２７ｂを形成する。こう
して、実装基板２８ｂが構成される。Next, as shown in FIG. 2(f), a resin-based Ag paste or the like is screen printed on the smoothed surface of the second resin layer 26b and hardened to form a rewiring layer 27b. In this way, the mounting board 28b is constructed.

最後に、このようにして作成した実装基板２８ａ。Finally, the mounting board 28a created in this way.

２８ｂを、再配線層２７ａ、　２７ｂ同士を対向させ、
異方性導電膜等のコンタクトＮ２９によって接続し多層
構造とする。28b, with the rewiring layers 27a and 27b facing each other,
A multilayer structure is formed by connecting through a contact N29 such as an anisotropic conductive film.

このように、本実施例においては、再配線層１の形成面
を高硬度の第２の樹脂層によって形成することにより再
配線層のスクリーン印刷を可能にすると共に、再配線層
の断線を防止しており、ダム枠内の大部分を低硬度の第
１の樹脂層で形成することにより、この第１の樹脂層に
よって第２の樹脂層の硬化収縮及び熱膨張を相殺して、
実装基板のそりを低減しでいる。As described above, in this embodiment, by forming the formation surface of the rewiring layer 1 with the second resin layer with high hardness, screen printing of the rewiring layer is made possible, and disconnection of the rewiring layer is prevented. By forming most of the inside of the dam frame with the first resin layer of low hardness, this first resin layer offsets the curing shrinkage and thermal expansion of the second resin layer.
The warpage of the mounting board is reduced.

［発明の効果］ 以上説明したように本発明によれば、第２の樹脂層が十
分な硬度を有しているので配線層を容易に形成すること
ができ、第１の樹脂層が低硬度であるので、実装基板に
そりが発生してしまうことを防止することができるとい
う効果を有する。[Effects of the Invention] As explained above, according to the present invention, since the second resin layer has sufficient hardness, a wiring layer can be easily formed, and the first resin layer has a low hardness. Therefore, it is possible to prevent warpage from occurring on the mounting board.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係る電子回路基板の一実施例を示す説
明図、第２図は第１図の電子回路基板の製造方法を工程
順に示す説明図、第３図は従来の電子回路基板を示す正
面図、第４図は従来の電子回路基板を示す説明図、第５
図は従来例の問題点を説明するための説明図である。 ２１ａ、　２１ｂ・・・プリント配線板、２２ａ　、　
２２ｂ　・・・実装部品、２３ａ　、　２３ｂ−接続ピ
ン、２４ａ　、　２４ｂ−、ダム枠、２５ａ　、　２５
ｂ　・・・第１の樹脂溜、２６ａ　、　２６ｂ−・・第
２の樹脂層、２７ａ　、　２７ｂ−・・再配線層、２８
ａ　、　２８ｂ−・・実ＲＩｔＮ、２９・・・コンタク
ト層、３０・・・電子回路基板。 ｂ ＋５ｂ 第５に１FIG. 1 is an explanatory diagram showing one embodiment of the electronic circuit board according to the present invention, FIG. 2 is an explanatory diagram showing the manufacturing method of the electronic circuit board of FIG. 4 is an explanatory diagram showing a conventional electronic circuit board, and 5 is a front view showing a conventional electronic circuit board.
The figure is an explanatory diagram for explaining the problems of the conventional example. 21a, 21b... printed wiring board, 22a,
22b...Mounted component, 23a, 23b-connection pin, 24a, 24b-, dam frame, 25a, 25
b...First resin reservoir, 26a, 26b--Second resin layer, 27a, 27b--Rewiring layer, 28
a, 28b--Real RItN, 29--Contact layer, 30--Electronic circuit board. b +5b 5th 1

Claims (1)

【特許請求の範囲】 実装部品及びこの実装部品に接続される接続ピンとを実
装し端部にダム枠を設けるプリント配線板と、前記ダム
枠内で前記実装部品を埋め込むように形成する第１の樹
脂層と、この第１の樹脂層よりも高い硬度を有し前記ダ
ム枠内の前記第１の樹脂層上に形成する第２の樹脂層と
、この第２の樹脂層上にスクリーン印刷する配線層と、
によって構成される複数の実装基板と、 これらの実装基板相互間に形成し前記各実装基板の配線
層同士を接続するコンタクト層とを具備したことを特徴
とする電子回路基板。[Scope of Claims] A printed wiring board on which a mounted component and a connection pin connected to the mounted component are mounted and a dam frame is provided at the end thereof, and a first printed wiring board formed so that the mounted component is embedded within the dam frame. a resin layer, a second resin layer having a higher hardness than the first resin layer and formed on the first resin layer within the dam frame, and screen printing on the second resin layer. a wiring layer,
What is claimed is: 1. An electronic circuit board comprising: a plurality of mounting boards configured by the following; and a contact layer formed between these mounting boards and connecting wiring layers of each of the mounting boards.
JP2081564A 1990-03-29 1990-03-29 Electronic circuit board Expired - Lifetime JP2693618B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2081564A JP2693618B2 (en) 1990-03-29 1990-03-29 Electronic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2081564A JP2693618B2 (en) 1990-03-29 1990-03-29 Electronic circuit board

Publications (2)

Publication Number Publication Date
JPH03280497A true JPH03280497A (en) 1991-12-11
JP2693618B2 JP2693618B2 (en) 1997-12-24

Family

ID=13749790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2081564A Expired - Lifetime JP2693618B2 (en) 1990-03-29 1990-03-29 Electronic circuit board

Country Status (1)

Country Link
JP (1) JP2693618B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175659A (en) * 1991-12-24 1993-07-13 Hitachi Ltd Multilayer thin film wiring board and module using the board
JP2010073785A (en) * 2008-09-17 2010-04-02 Alps Electric Co Ltd Multilayered wiring board, and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111246655B (en) * 2020-01-07 2021-01-26 深圳市江霖电子科技有限公司 Point contact type heat insulation PCB

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175659A (en) * 1991-12-24 1993-07-13 Hitachi Ltd Multilayer thin film wiring board and module using the board
JP2010073785A (en) * 2008-09-17 2010-04-02 Alps Electric Co Ltd Multilayered wiring board, and method of manufacturing the same

Also Published As

Publication number Publication date
JP2693618B2 (en) 1997-12-24

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